GB801781A - Improvements in or relating to electronic pulse delay circuits - Google Patents

Abstract

801,781. Pulse delaying circuits. BRITISH TABULATING MACHINE CO., Ltd. Dec. 30, 1954, No. 37655/54. Class 40 (6). A pulse delaying circuit comprises a coincidence circuit associated with an electric discharge tube which is normally conducting so that when a positive input pulse and a clock pulse are applied simultaneously the tube is rendered non-conducting and then conducts again after a predetermined period to produce a delayed output pulse across its anode load. Figs. 1 and 2 show a pulse delaying circuit in which if an input pulse train, Fig. 2 (a), to be delayed is applied at input 1 and a clock pulse train, Fig. 2 (g), to input 2 when pulses in the two trains coincide both diodes 3 and 4 are cutoff and positive pulses, Fig. 2 (d), appear at the junction of diodes 3, 4. These are differentiated by capacitor 5 and the low grid/cathode impedance of tube VI so that at the negative trailing edges VI is cut-off capacitor 5 re-charging slowly through resistor 6 until when a positive re-set pulse, Fig. 2 (c), appears at reset input 10 it recharges rapidly through diode 8. Thus the grid voltage of tube VI, as shown in Fig. 2 (e), is amplified in tube VI, squared by the clamping action of diodes 13, 14 and appears at the grid of V2, Fig. 2 (f), as a train of rectangular pulses which is a replica of the input pulse train, Fig. 2 (a), delayed by one clock pulse period. The voltage at the grid of V2 is amplified in tube V2 which produces an output at its cathode, or a pulse train of opposite polarity may be produced across an anode load, not shown. Capacitor 18 and resistor 17 may be such as to prevent a short pulse at the grid of tube V2 which appears between two longer pulses from being produced at the output, Fig. 2 (g).