GB8826919D0 - Cmos integrated circuit & method of making same - Google Patents

Cmos integrated circuit & method of making same

Info

Publication number
GB8826919D0
GB8826919D0 GB888826919A GB8826919A GB8826919D0 GB 8826919 D0 GB8826919 D0 GB 8826919D0 GB 888826919 A GB888826919 A GB 888826919A GB 8826919 A GB8826919 A GB 8826919A GB 8826919 D0 GB8826919 D0 GB 8826919D0
Authority
GB
United Kingdom
Prior art keywords
integrated circuit
making same
cmos integrated
cmos
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB888826919A
Other versions
GB2212660B (en
GB2212660A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intersil Corp
Original Assignee
Intersil Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intersil Inc filed Critical Intersil Inc
Publication of GB8826919D0 publication Critical patent/GB8826919D0/en
Publication of GB2212660A publication Critical patent/GB2212660A/en
Application granted granted Critical
Publication of GB2212660B publication Critical patent/GB2212660B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
GB8826919A 1987-11-18 1988-11-17 Cmos integrated circuit and method of making the same Expired - Lifetime GB2212660B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12213087A 1987-11-18 1987-11-18

Publications (3)

Publication Number Publication Date
GB8826919D0 true GB8826919D0 (en) 1988-12-21
GB2212660A GB2212660A (en) 1989-07-26
GB2212660B GB2212660B (en) 1991-02-13

Family

ID=22400831

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8826919A Expired - Lifetime GB2212660B (en) 1987-11-18 1988-11-17 Cmos integrated circuit and method of making the same

Country Status (4)

Country Link
JP (1) JPH01161756A (en)
DE (1) DE3837270A1 (en)
FR (1) FR2623332B1 (en)
GB (1) GB2212660B (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5671928A (en) * 1979-11-16 1981-06-15 Chiyou Lsi Gijutsu Kenkyu Kumiai Treatment for silicon substrate
JPS5788736A (en) * 1980-11-21 1982-06-02 Toshiba Corp Preparation of semiconductor device
JPS586140A (en) * 1981-07-03 1983-01-13 Nec Corp Manufacture of silicon wafer
JPH0612801B2 (en) * 1981-08-25 1994-02-16 三菱電機株式会社 Semiconductor device and manufacturing method thereof
US4548654A (en) * 1983-06-03 1985-10-22 Motorola, Inc. Surface denuding of silicon wafer
JPS60133734A (en) * 1983-12-21 1985-07-16 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS60148127A (en) * 1984-01-13 1985-08-05 Nec Corp Manufacture of semiconductor substrate

Also Published As

Publication number Publication date
JPH01161756A (en) 1989-06-26
FR2623332A1 (en) 1989-05-19
FR2623332B1 (en) 1994-09-23
DE3837270A1 (en) 1989-06-01
GB2212660B (en) 1991-02-13
GB2212660A (en) 1989-07-26

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 19961117