GB881378A - Improvements in logical switching devices - Google Patents

Improvements in logical switching devices

Info

Publication number
GB881378A
GB881378A GB1791959A GB1791959A GB881378A GB 881378 A GB881378 A GB 881378A GB 1791959 A GB1791959 A GB 1791959A GB 1791959 A GB1791959 A GB 1791959A GB 881378 A GB881378 A GB 881378A
Authority
GB
United Kingdom
Prior art keywords
core
state
cores
winding
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1791959A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US528594A external-priority patent/US2907987A/en
Priority claimed from US548581A external-priority patent/US2919354A/en
Priority claimed from US625826A external-priority patent/US2904779A/en
Priority claimed from US757482A external-priority patent/US3163771A/en
Priority claimed from US769838A external-priority patent/US3077585A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB881378A publication Critical patent/GB881378A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/383Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/02Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements
    • G11C19/04Digital stores in which the information is moved stepwise, e.g. shift registers using magnetic elements using cores with one aperture or magnetic loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/16Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Coils Or Transformers For Communication (AREA)
  • Dc Digital Transmission (AREA)
  • Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
  • Control Of Stepping Motors (AREA)
  • Electronic Switches (AREA)
  • Discharge By Other Means (AREA)

Abstract

881,378. Circuits employing bi-stable magnetic elements. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 26, 1959 [Aug. 27, 1958], No. 17919/59. Class 40 (9). In a logical switching circuit using magnetic cores with appreciable remanence and low coercivity and comprising a biased input core C1, a storage core S and an output core C2 all initially in the " 0 " remanent state, an input signal " 1 " applied to core C1 reverses the remanent state of cores C1 and C2 to state " 1," while automatic restoration of core C1 to the " 0 " state by the bias, following termination of the input signal, causes core S to change to state " 1," the cores S and C2 being subsequently restored to state " 0 " by a read-out clock pulse IB. As shown, the core C1 is biased by a current Id.c. in a winding 38 and has an output winding 12 connected in a series loop A with a control winding 10 and input winding 14 on cores S and C2 respectively. When the core C1 is driven to state " 1 " by the input signal, a pulse is induced in the loop which reverses C2 but is without effect on core S since it acts in the existing " 0 " sense. A further pulse of opposite polarity appears in the loop when C1 is automatically restored to state " 0," this pulse reversing core S to state " 1 " but having no restoring effect on core C2 as the control winding 10 has a larger number of turns than the input winding 14. Due to the presence of a diode D in the circuit of output winding 24 of C2, an effective output pulse is obtained only when the cores S and C2 are restored to state " 0 " by a pulse IB in windings 40, 42. This output pulse is applied over a loop B to set cores C3, C4 and C5 to state " 1 " and these cores are subsequently restored to state " 0 " by a clock pulse IA. In a modification, Fig. 3 (not shown), an inhibiting winding is included on core C2. The core C1 may have any number of input windings such as 16, 18 and 20 as shown, and the bias may be adjusted so as to provide OR or AND operation. Alternatively two input windings wound in opposite senses may be used, this arrangement with a bias value such that a single input may reverse the core state providing the logical operation NOT IF THEN.
GB1791959A 1955-08-16 1959-05-26 Improvements in logical switching devices Expired GB881378A (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US528594A US2907987A (en) 1955-08-16 1955-08-16 Magnetic core transfer circuit
US548581A US2919354A (en) 1955-11-23 1955-11-23 Magnetic core logical circuit
US625826A US2904779A (en) 1956-12-03 1956-12-03 Magnetic core transfer circuit
US757482A US3163771A (en) 1958-08-27 1958-08-27 Logical transfer circuit
US769838A US3077585A (en) 1958-10-27 1958-10-27 Shift register

Publications (1)

Publication Number Publication Date
GB881378A true GB881378A (en) 1961-11-01

Family

ID=27541848

Family Applications (4)

Application Number Title Priority Date Filing Date
GB2466256A Expired GB841619A (en) 1955-08-16 1956-08-13 Improvements in magnetic core shift registers
GB3550156A Expired GB843496A (en) 1955-08-16 1956-11-20 Improvements in magnetic core switching networks
GB1791959A Expired GB881378A (en) 1955-08-16 1959-05-26 Improvements in logical switching devices
GB3642359A Expired GB914348A (en) 1955-08-16 1959-10-27 Shift register

Family Applications Before (2)

Application Number Title Priority Date Filing Date
GB2466256A Expired GB841619A (en) 1955-08-16 1956-08-13 Improvements in magnetic core shift registers
GB3550156A Expired GB843496A (en) 1955-08-16 1956-11-20 Improvements in magnetic core switching networks

Family Applications After (1)

Application Number Title Priority Date Filing Date
GB3642359A Expired GB914348A (en) 1955-08-16 1959-10-27 Shift register

Country Status (4)

Country Link
DE (5) DE1142452B (en)
FR (3) FR1172001A (en)
GB (4) GB841619A (en)
NL (2) NL209697A (en)

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB706736A (en) * 1952-01-03 1954-04-07 British Tabulating Mach Co Ltd Improvements in or relating to electrical storage devices
US2781503A (en) * 1953-04-29 1957-02-12 American Mach & Foundry Magnetic memory circuits employing biased magnetic binary cores
US2784390A (en) * 1953-11-27 1957-03-05 Rca Corp Static magnetic memory
AT196644B (en) * 1955-08-16 1958-03-25 Ibm Circuit for forwarding information stored in a magnetic core

Also Published As

Publication number Publication date
DE1160891B (en) 1964-01-09
NL209697A (en)
DE1161311B (en) 1964-01-16
DE1142452B (en) 1963-01-17
DE1155169B (en) 1963-10-03
FR1172001A (en) 1959-02-04
GB843496A (en) 1960-08-04
DE1166256B (en) 1964-03-26
NL109283C (en)
FR1172057A (en) 1959-02-05
FR1194463A (en) 1959-11-10
GB914348A (en) 1963-01-02
GB841619A (en) 1960-07-20

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