DE1155169B - Magnetic core sliding memory - Google Patents

Description

In electronic calculating machines and other devices for automatic data processing are often, e.g. B. used for multiplying and dividing multi-part numbers, shift memory, the are constructed with magnetic cores, the material of which has an almost rectangular hysteresis loop. In an effort to increase the operational safety of such sliding memory, it is known that for Prevention of reverse transmission of the stored information, mostly used diodes to be replaced by other elements because of their susceptibility to failure.

In a known shift memory, for example, ferroelectric cells with almost rectangular hysteresis loop, which prevent reverse transmission and at the same time as Buffers are in effect. With this sliding memory, the information can be moved from left to right and are transmitted from right to left, if for the representation of the digits in the kernels resp. ferroelectric cells different magnetization or polarization directions can be selected and the polarity of one of the incremental pulses is reversed. This type of change in the direction of advance can be realized by suitable switching means, but requires the choice of a second one Magnetization direction two additional windings per core or for the choice of a second one Direction of polarization per stage a switching device, which the ferroelectric cells in the opposite direction to be allowed to switch into the electrical circuits.

In another known sliding store, magnetic cores are used as intermediate stores. The retransmission of the information in the blocking direction is avoided by blocking magnetic cores. the The output winding of a blocking magnet core is located in the connecting lines between the storage cores and the buffer cores and represents a variable impedance. The input windings All blocking magnet cores are positive or depending on the desired direction of displacement negative pulses are supplied, which increases the impedance in the direction to be blocked and in the desired direction Direction the impedance is lowered and thus the shift of the information only in in the desired direction. This sliding memory allows the direction of movement to be easily switched. However, it requires considerable effort; per level are a memory core, a Cache core and two locking cores required. In the known sliding stores described information is shifted from a magnetic core shift memory

Applicant:

International Business Machines Corporation, New York, N.Y. (V. St A.)

Representative: Dipl.-Ing. H. E. Böhmer, patent attorney, Böblingen, Sindelfinger Str. 49

Claimed priority:
V. St. v. America, October 27, 1958 (No. 769 838)

Sammy Ardeil Butler, Peekskill, N.Y. (V. St. A.) has been named as the inventor

Stage to the next in two separate and through each

^a 5 steps triggered by an incremental pulse. In the first step, a memory core is erased and at the same time written into the intermediate memory; in the second step, the intermediate memory is erased and simultaneously written into the memory core of the next stage.

In the case of the sliding store according to the invention, these two steps merge smoothly into one another. the The information is switched from one level to the next during a single shift pulse, deleting a memory core, writing to the next buffer and at the same time causes the charging of a capacitor, which, if necessary, supports it through its discharge by a clock pulse, the discharge of the intermediate memory and the writing into the memory core the subsequent stage causes.

The arrangement according to the invention also allows the information to be shifted in both directions. For this purpose, the displacement pulses are optionally fed to one of two sets of windings. The effort is low; Only two magnetic cores and one capacitor are required per stage.

The invention relates to a magnetic core sliding memory without diodes, in which the transmission the information between the individual levels takes place via coupling cores, the memory cores of the even-numbered steps from a first and those

309 6S0 / 129

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gen of the odd-numbered stages of a second characteristic curve, which are reset for the memory cores emergency clock pulse source and the two is manoeuvrable. But they should have a good ratio B _r / B _s clock pulse sources can be alternately actuated. Since these devices are used to control the invention, they are characterized in that one winding of the memory core and one winding element each work as a variable Im stage in each transfer of information pulses.

ment of the two between this memory core and in Fig. 2 are such connecting coupling cores

the storage cores of the preceding or next with K ₁ , K ₂ , K ₃ and K ± and the storage cores with S ₁ , the following stage and S ₂ , S ₃ and S ₄ arranged coupling cores. The transmission of information in a capacitor to a loop in succession takes place through the memory core S, which is switched so that these three windings have the same input information through the coupling cores and have the same winding direction and that this information is retained via the coupling of one of the two coupling cores can deliver together with the core of the following stage. The memory core of the relevant clock pulse _{source memory core S 1} is influenced by a control winding 10 in the same way. see that work as input and output winding

The invention is described in more detail with reference to some embodiments and examples with a winding 12 on the core K _1. In the drawings and shows a winding 14 on the core K ₂ via a

Fig. 1 the hysteresis loop of the used Ma capacitor C _{1 is} connected (loop A). The Koppgnetmaterials, lungskern K ₂ is further provided with a winding 16

Fig. 2, 6 and 7 see the _{exemplary embodiments, which via a capacitor C 2} with a winding

Fig. 3 and 4 each part of the arrangement according to so treatment 18 on the core K ₃ and a control winding 20 Fig. 2 and connected to the core S ₂ (loop B). Of the

5 and 8, the coupling core K ₃ in the exemplary embodiments is provided with a winding 22, and pulse trains are turned. the one through a capacitor C ₃ with a winding

In Fig. 1, the curve shown shows the dependence 24 on the core K ₄ ^ and a control winding 26 on speed of the power flux density (B) of the applied 25 is connected to the core S ₃ (loop C). The coupling field (El) for the magnetic material of a core, lungskern K ± is provided with a winding 28 which has a predominantly rectangular hysteresis characteristic over a capacitor C ₄ with a control winding. The two opposite remanents 30 on the core S _{4 are} connected to provide a signal to stages are usually used for the representation of a further logical stage which uses a feminine information; they are arbitrarily designated with "0" and "!" in the 30 direct coupling core K of a similar circuit diagram. If can hold. The coupling core K ₁ is stored with a "0", causes a pulse that is provided on winding 32, which is applied to winding 32 with a suitable winding direction during right-shift operation, binary input information is received and the loop is run through, and this information is obtained through the core K ₁ to the core S ₁ the remanence state "1" when the impulse ceases. 35 can transfer.

Such a pulse is hereinafter referred to as "input" - a clock pulse source I _A and a clock pulse-

Signal. In a similar way, a core is taken from source I _B is in each case with the midpoint terminal of a core or it is connected to two-pole double changeover switch 34 in the “0” state. One set back, where it can be determined which first terminal of the switch 34 is called R _A , information has been stored. This is done by 40 other terminal R _B , yet another L _A and an application of a pulse in the reverse row - another L _B. A sliding winding 36 a is provided tion on the same or a different winding. Such a pulse on each of the coupling cores with an odd index is referred to below as a "removal" signal (K ₁ , K ₃ ), while a sliding winding 36 b is designated on jebe. If a "1" has been saved, for which the coupling core with an even index (K ₂ , K ₄ ) , a strong change in the force flow occurs with the 45 provided. In the same way, there is a sliding winding shift from the “1” to the “0” state, and a development 38 α on each of the storage cores with an odd speaking high voltage is provided at the output winding index (S ₁ , S ₃ ) while a sliding winding is generated. If, on the other hand, a “0” should have been stored on each of the memory cores with a straight line, there is little change in the power flow, and index (S ₂ , S ₄ ) is provided. The two sliding turns, a negligible signal, is generated at the output 50 lungs36α on the cores ^ and K _z are generated with the winding. Sliding windings 38 a on the cores S ₁ and S ₃ in

2, 3, 4, 6 and 7, which are connected in series and to the terminal R _{A of} the switch, the winding direction is indicated, 36 & on the cores K ₂ and K ₁ with the sliding winding in which a 55 lungs 38 b directed into the marked ends on the cores S ₂ and S ₄ in series with a positive impulse seeks to switch a negative field and to the terminal R _{B of} the switch 34 or to store a "0" while a in is being carried out. When switch 34 is in a position, the unmarked ends conducted positive pulse that it seeks sources I _A and I _B with terminals R _A to store a "1". and R _B connects, the register can provide information

The arrangements shown use input shift 60 to the right.

and output coupling magnetic cores located between On each of the even-index coupling cores

So-called storage magnetic cores are arranged, (K ₂ , K ₄ ) a sliding winding 40 a is provided, which store certain logical information, and while a further sliding winding 40 b on each of these arrangements, the coupling cores with an odd index (K ₁ , K ₃ ) cores with other similar switching arrangements are provided. Another sliding winding 42 a is to be bound. The coupling cores can be made of ferrite in a similar way to the memory cores with an odd index, they (S ₁ , S ₃ ) are provided, while a further sliding need not, however, the rectangular hysteresis winding 42 & is provided on each of the memory cores.

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kernels with an even index (S ₂ , S ₄ ). The sliding wicks lead. Since the core X _{3 is} held in the "O" state by the 40 α hanging in its winding, the cores X ₂ and X ₄ are kept in the "O" state with the 44 / ^ clock pulse conducted, shift windings 42 α on the KeHKnS ₁ and S ₃ in, the core S _{2 is switched} completely from the "0" to the "1" series and switched to the switching state with terminal L _A. The connected in the loop A as a result of the ters 34, while the sliding windings 5 attempts to reset the core K ₉ to the "O" state before-40 b on the cores K ₁ and K ₃ with the sliding windings in a clockwise direction Konlungen 42 b on each of the memory _{cores S 2} and S ₄ in capacitor C ₁ to charge a higher voltage. Connected in series and with the terminal L _{B of} the switch After the core K _{2 is connected back} to the "O" state 34. When the switch 34 is set to the, the capacitor C ₁ discharges and adjustment is that it connects the sources I _A and I _B with the io causes a counterclockwise current in the terminals L _A and L _B , the register can In loop A, which moves the cores K ₁ , S ₁ and X "in the formations to the left. Furthermore, it wants to bring it to the "O" state. Since the cores K _1, K ₂ and each of the coupling kernels K _1, K _2, X ₃ and X ₄ is a _S1 already in the "O" state are, this current has no further shift winding 44 is provided. This wick effect. After the end of the I _A and 7 ^ clocks, the source I _{R is connected} in series. 15 impulses, all nuclei remain in the »O« state except for

These three clock pulse sources supply the core S ₂ in FIG. 5, which remains in the "1" state,
Pulse sequence shown. To make it understandable, then the / _ß -clock pulse source works and

how the register of FIG. 2 can carry out a removal signal into the windings 36 & shift operations, which of the cores K ₂ and Z ₄ and the windings 38 & are connected to the circuit of the register of FIG. 2 for the right 20 the cores S ₂ and S ₄ , which switches the core S ₂ from the "1" shift operation and in FIG. 4 the circuit of the into the "O" state, showing a voltage register for the left shift operation . induced in the control winding 20. This tension

Assume in Fig. 3 that the switch for seeks to set a clockwise current in shift right operation and to cause all of the loop B , which each of the cores in the lower remanent state or "0" - 25 cores K ₂ and Switch K ₃ to the "!." State and are in the state with the exception of the core S ₁ , which wants to charge the capacitor C _2. Since the nucleus K _{2 is} "1" state. When in Fig. 3 the / 4 clock pulse through the I _A source sent into its winding 36 b works, the clock pulse for windings 36 a and 38 a is kept in the "0" state, starts on the cores K ₁ , K ₃ , S ₁ and S ₃ a removal - the core K _{n is passed} from the "0" - to the "1" state to signal which switch the KeImS ₁ from the "1" to the 30, and the capacitor C ₂ begins to reset itself to the "0" state and thereby in the control load. Since the core K ₃ switches to the "!." State, winding 10 of the core S ₁ induces a voltage, a voltage is induced in the winding 22, which causes a clockwise current in the loop A , which seeks to cause the nuclei K _{1 to} loop C, which _{brings the nuclei S 3} and X ₄ and K ₂ to the "1" state and the 35 to the "0" state and the capacitor C. to load capacitor C _{3. 1} Since at this time one wants to charge the charge of the capacitor C ₂ in the core K ₁ in the "0" state through the opposite sense in its winding loop B. Since the clock pulse is held, at this point in time each of the cores S ₃ and X ₄ begins to charge the capacitor C ₁ , and the "0" state is no effect on them. Core C ₂ starts practicing from the "0" to the "1" state to 40, and the capacitor C ₃ is charged. When the switch. Since the core K ₂ switches to the "!" State, power flow change in the KeTnX _{3 reaches} its peak, a voltage is induced in the winding 16, reaches and begins to drop, the conweiche discharges a counterclockwise current into capacitor C ₃ and generates a current caused in the clockwise loop B , which seeks to senses the kernels in loop C. At this point in time S ₂ and K _{3 works} to switch the "0" state and the 45 the / ^ - clock pulse source and sends a removal capacitor C ₂ in a capacitor C ₁ corresponds signal in the winding 44 to charge to each of the cores C _1, to set "sense. at this time, K _2, K ₃ and X _4, which the resetting of the core, the cores S ₂ and K _{3 are} already in the "0" state, K ₃ from the "1" to the "0" state and there is no effect on them, and the con at causes a voltage in the winding of capacitor C ₂ is charged. When the power flow change 50 is induced 18 and 22. The one in the winding g 22 in the core K _{2 reaches} its peak and the deducted voltage wants to start a clockwise current, the capacitor C ₂ discharges and creates a sense in loop C, which generates a clockwise current in the current of the capacitor C ₃ and increases the discharge the cores X ₄ loop B. At this point in time the clock is working and S ₃ wants to bring it to the "1" state. Since the pulse source I _R and passes a sampling signal 55 core X ₄ at this time by the in its each of the windings 44 of the coupling cores X _1, X _2, winding 44 led / ^ - clock pulse in the "0" _-to-X3, and X ₄ , which begins to _{hold the core X 2} from the "1" -in stand, only the core S ₃ from the "0" - the "0" -state will be reset. When switched to the »!.« State switched. As a result of the return to the "0" state, the core X ₂ induces a tension of the core X ₃ to the "0" state in the voltage in the windings 14 and 16, which tries to induce a voltage induced by winding 18 Clockwise current in the two loops. Clockwise current in loop B, which produce the fen ^ i and B. The currents in loop B bring cores S ₂ and X ₂ into the "0" state and from the discharge of capacitor C ₂ and the capacitor C ₂ to a higher voltage switching into the "0" state of core X ₂ want to add load. Since the cores S ₂ and X ₂ to this Zeitsich, thus increasing the discharge current of the capacitor 65 point-by in the windings 36 b and 38 C _2, thereby causing a large current in the forwarded / ^ - clock pulse in the "0" state held clockwise in loop B, which seeks to be, the capacitor C ₂ is charged to a higher the cores X ₃ and S ₂ in the "!" state over-voltage. After the core X ₃ back-

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is set, the capacitor C ₂ discharges and a higher voltage is charged, and the cores S ₃ causes a counterclockwise current in the and X ₄ remain in the »Ck state. If the kernel loop B, which has the kernels K ₂ , S ₂ and K _s in the supply K ₃ completely reset to the "O" state, wants to bring "0" into existence. Since the cores K ₂ , S ₂ and K ₃ charges the capacitor C ₃ and causes it to be in the "O" state, there is no counterclockwise current in them that produces an effect. During the operation of the I _A , the cores K ₃ , K _i and S _{3 were brought} into the "O" state and I _ß clock pulse sources that originally wanted in the core S ₁ . Since the cores K ₃ , S ₃ and X _{4 are} already in the "O" -contained information from the core S ₁ to the core S ₂ , no effect is achieved with them. So and from there to core S ₃ , the information was left from core S ₃ to core S ₃ in the "1" state and all io S _{2 was} transferred, which is now in the "1"state; all other nuclei remained in the "O" state. The other cores register remained in the "O" state. performed such a right shift operation. After the operation of the / ^ - clock pulse source ar-

It is now assumed that the switch 34 is set for the / ß-clock pulse source and sends an Ent-left shift operation, and all cores took signal in the windings 40 b on the cores in the lower remanence or "O" state are up to 15 K ₁ and K ₃ and in the windings 42 b on the core S ₃ , _{the cores S 2} and S ₄ previously left in the "1" state. The core S ₂ is from the "1" -in became. In the following, the operation of the register "O" state is postponed, thereby inducing one of FIG. 2 explained with reference to FIG. At voltage in the control winding 20, which causes a current of the operation of the 7 _A clock pulse source, a counterclockwise direction in loop B , which took signal in the winding 40 a on the cores K ₂ 20 the cores K ₂ and K ₃ in the Bring "1" state and and 2C ₄ and in the windings 42 α on the cores S ₁ wants to charge the capacitor C _2. Since the core K ₃ and S ₃ conducts, which resets the core S ₃ from the "1" - to the / _B -clock- "0" state sent by its winding 40 b , in order to cause the impulse in the " 0 "state is held, the voltage induced in the control winding 26 core K _{2 is switched} from the" 0 "to the" 1 "state, which causes a clockwise current in 25 and the capacitor C ₂ is charged. When switching loop C causes the cores K ₃ and X ₄ in the "1" state, the core X ₂ induces a "!" State and the capacitor C ₃ voltage in the winding 14, which a current against want to charge. Since the core X _{4 is} caused by the clockwise / clock pulse in its clockwise direction in loop A , which brings the / ^ clock pulse in the "0" -to core K ₁ and S ₁ into the "((" state and the is held, the core K ₃ begins to charge from the “0” - 3 ° capacitor C ₁ with a polarity that wants to switch to the “1” state, and the capacitor is opposite to that _{of the capacitor C 2. Since the C 3} begins to be charged: Since the core K _{3 of} the “0” cores K ₁ and S _{1 are} already in the “0” state, the switch is made to the “1” state, in which only the capacitor C _{1 is} charged When the power winding 18 induces a voltage, which in the flux change in the core K _{2 reaches} its peak, loop B generates a current in the counterclockwise direction and begins to decrease, the capacitor C ₁ begins to generate the cores K ₂ and S ₂ wants to unload in the "0" state and generates a current in Uhrbringen and capacitor C ₂ charge. Since pointer in the sense Schleifet. at this At the point in time both cores K ₂ and S _{2 are} already in the "0" state, the / ^ clock pulse source works and sends a De-If no effect is achieved with them, and the acceptance signal to winding 44 on core K ₂ , capacitor C ₂ is charged with a polarity which is 4 ° which the core K ₂ from the "1" to the "0" state is opposite to _{that of the capacitor C 3.} resets and causes that in the windings 14 When the power flow change in the core K ₃ its maximum and 16 a voltage is induced. The voltage induced in the mum reaches and begins to decrease, winding 14 begins tending _{to discharge the capacitor C 2} and generates a clockwise current in the loop to produce a clockwise current in the loop B. The discharge current of the condensate works at this point in time the / ^ - clock pulse source sator C ₁ increases, which _{wants to bring the cores S 1} and K ₁ to the "1" - and sends a removal signal to the winding 44 state. Since the core K _{1 is} caused by the in on the cores K ₁ , K ₂ , K ₃ and Jf ₄ , which resets the / ^ clock pulse sent to its winding 40 b from the "1" to the "0" state " 0 «state is held, only the KeTnS ₁ and a voltage in the windings 18 and 5 ° are switched from the» 0 «to the» 1 «state. The induced as a result. The "voltage induced in the winding 16" caused by the resetting of the core of the resetting of the core K ₂ into the "0" state X ₃ into the "0" state in the winding 18 causes a current to flow in the clockwise direction in the voltage Clockwise in loop B, the one in loop B, which brings the discharge current of the condenser - the cores K ₃ and S ₂ to the "1" state and increases the sators C ₂ and the cores S ₂ and UC ₂ to the "1" - 55 will bring the capacitor C ₂ to a voltage higher on-state, since the core K. wishes to load by in Since the cores UC ₃ and S ₂ as a result of in its winding 40 a skillful / ^ _-.?. clock pulse in their windings 40 b and 42 & led / _ß -clock- "0" -state is held, if no we- pulse is kept in it in the "0" -state, the kung is achieved, and the core S ₂ is from the "0" - switched to a higher voltage "1" state in the capacitor C _2, which are charged as a result of the reset 60. After the core K ₂ vö If the core K _{3 is} in the "0" state in the winding, the capacitor C ₂ begins to discharge and the induced voltage causes a current in the generation of a counter-clockwise current in the loop C, which the cores K ₁ loop B, which wants to bring the cores K ₂ , S ₂ and K ₃ into the "0" - and S ₃ into the state "1" and bring the condensation state. Since the cores IC ₂ , S ₂ and K ₃ sator C ₃ wants to charge to a higher voltage. Since 65 are already in the "0" state, none of the cores S ₃ and X _{4 are} achieved by the action in the windings. Thus, by operation of the I _B - a and 40 a sent clock pulse I _A in the "0" -zu clock pulse source information from the core S ₂ to be maintained, the capacitor C _{3 is transferred} to core S ₁ .

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In FIG. 6 another embodiment of this lying case is shown the turns of each of the Wick invention, which is a simplified version of the 14 'and 16' hung on the core K ₂ equal to the reversible shift register shown in FIG. ensure that the current in loop B 'is omitted here the / ^ - clock pulse generator and the winding is smaller than the lungs 44 developed in loop A' on each of the coupling cores K ₁ , K ₂ , K ₃ 5 current, so that the capacitor C ₂ to a lower and K _v Assume that the switch 34 'is charged at the same level as the capacitor C ₁ . On a position is where he the I _A - and / g clock pulse - this way this circuit uses the energy generator with the terminals R / and R _B ' for the right loss, which connects such coupling cores between logical shift operations and that all cores in the see stages is peculiar to the fact that the capacitors are "O" -states except for the core S _1, which has different charges in the "1" - io or energy storage elements. In the following there will be shown in detail a demonstration. Since thus in the loop A ' due to the writing of the circuit for the right shift operation- discharge of the capacitor C ₁ at the same time, tion with reference to the clock shown in Fig. 8- where the capacitor C ₂ ' in the loop B ' unpulses I _A and I _B given. charges, is a larger current, the core K _{2 is} dated

During the operation of the / ^ - clock pulse generator 15 "1" - is reset to the "O" state and the core is switched to a removal signal in the windings 36 a 'on the S ₂ from "0" to the "1" state . In the case of BeKerne K ₁ and K ₃ ' and the windings 38''at the end of the / 4 clock pulse, all the cores remain sent in the cores S ₁ and S _s ' . The nucleus S ₁ ' becomes the "O" state, and the "1" is reset from the nucleus S ₁ to the nucleus from the "1" to the "O" state. It has been transmitted in S ₂ ' , which now in the "1" state reduces a voltage in the control winding 20.

10 ', which runs a clockwise current in Then the / _ß -clock pulse generator works to cause loop A' , which seeks to move the core S ₂ from the "1" to the "O" state to cores, ST ₁ 'and To bring X ₂ 'back to the state "1" and to charge as above for the / ^ clock pulse and the capacitor C ₁ . Since the core K _{1 has been} described, the "1" via the coupling _{core K 3} from the I _x - 25 memory core S ₂ ' sent through its winding 36a' to the memory _{core S 3} 'is kept in the "O" state via clock pulse will contribute.

has no effect, the core K ₂ ' begins when the switch 34' switches the I _A and / _ß clock pulse "0" to the "1" state, and the cone with the L terminals _A and L _B connect and capacitor C ₁ begins to charge. When switching all cores in the circuit of FIG. 6 in the "O" -Zuvom "0" - to the "!." - state induces the core K ₂ 30 standstill with the exception of the core S ₃ 'of the im a voltage in the Winding 16 ', which was left a "1" state, the circuit is ready for counterclockwise current in loop B' for the left shift operation.
causes, which seeks to the cores S ₂ and K ₃ ' During the operation of the / ^ - clock pulse generator is brought into the state "0" and the capacitor a removal signal in the windings 40 a' of the cores C ₂ with one polarity to charge which is opposite to that of the 35 K ₂ and K / and in the windings 42 α 'of the cores capacitor C _2'. As the cores S ₁ and S _{3 passed} . The core S ₃ ' is then "1" - S ₂ and K _{3 are} already in the "0" state, only that is reset to the "0" state and induces a capacitor C ₂ ' charged. When the power flow voltage in the control winding 26 ', which has reached its climax in a change in the core K _2, begins to cause and decrease clockwise current in the loop C, the condensate discharges gently, which the cores, ST ₃ ' and K _t ' in the state "1" capacitor C ₂ ' and causes a current to move clockwise and wants to charge _{the capacitor C 3 '.} Then in the loop B ', which wants to bring the cores K ₃ , S ₂ and K _{2 of} the core K / to the state "!" As a result of the α' in its winding 40. Since the core K ₃ ' conducted / ^ - clock pulse is kept in the "0" state by the I _A - sent into its winding 38 α', the core K _{3 is switched} from the "0" to the "1" Clock pulse is held in the "0" state, it is switched to stand at 45, and the capacitor C ₃ 'begins to have no effect. At the same time it begins to charge. When switching in the "!" -. State and the capacitor C ₁ in the loop A 'to induce the core K _3, a voltage in the winding unloading and causes a current to the clock lung 18' to which pointer sense a current in the counterclockwise direction in the loopΛ (', which causes the nuclei K ₁ , S ₁ in loop', which seeks to bring the and K ₂ into the "0" state. Since the 50 nuclei K ₂ and S _{2 are} in the state " 0 "and cores K ₁ and S _{1 are} already in the" 0 "state to _{charge the capacitor C 2} '. Since the cores K _{2 they} remain unaffected. The core K ₂ , however, is in and S ₂ ' is already in the" .! 0 «« state are only invites "- state and wants through the result of unloading the capacitor _C2 '. described above, dung is the capacitor C ₁ in the loop A' existing capacitor C ₂ 'with a lower voltage, in which the current is reset to the "0" state, is charged than the capacitor C ₃ ', since the energy is over. When the core S ₁ , as above b As described, an energy "1" was reset to the "0" state from the transfer by the coupling core K ₃ , which results in a loss of voltage that results from the resetting of the core S ₁ to the one when passing through the Capacitor C ₂ 'against loop A' transferred energy through the mirror. When the power flow change in the core K ₃ switch the core K ₂ into the "1" state and the 60 has reached its peak and decrease loading-charging of the capacitor C ₁ divided. When switching starts, the capacitors C ₃ 'and C ₂ ' begin to "1" state, the KeHiZ ₂ 'transfers the charged. During the discharge, the counter-energy to the loop B ' and from there to the capacitor C ₃ ' causes a counterclockwise current in capacitor C ₂ ', as described above. However, if one of the loop C, which the kernels K ₃ , S ₃ and K / is switched into the kernel, wants to bring about a certain state of "0". At the same time, which in the prior art was overcome by the fact that the capacitor C ₂ 'was slightly defeated on discharge, a greater number of turns of clockwise current in the loop B', which was provided for the output winding. Bring K ₃ , S ₂ and K ₂ ' into the state "1" in the fore-cores

11 12

tries. Since the cores K ₂ and .K ₄ 'are not influenced by the / ^ clock pulse sent to theirs at this point in time in the "O"-Zu-Windings40a' and which withstands. When discharging, the core S ₃ 'in the same way through which the capacitor C ₁ "conducts a current against the lung42α' / ^ clock pulse in the" O "state clockwise in the loop", which loops the core are held, no action occurs with these cores. 5 K ₂ " wants to reset to the" O "state. As above kung. Since the counterclockwise current in the described for the embodiment of FIG. 6, the loop C is larger as the current clockwise - the core K ₂ "is reset from the" 1 "- to the" O "state in loop B ', the core K ₃ ' is reset from the" 1 "because the capacitor C ₁ " as a result of being reset to the "O" state, while the current losses in core K ₂ " when transferring energy clockwise in the loop B ' the core S ₂ ' io after the capacitor C ₂ " to a higher potential completely from the " 0 «- switches to the» 1 «state. As charged as the capacitor C ₂ ", while the core S ₃ 'became the core S ₂ information stream is transmitted clockwise in the loop B " the core to the left. When the / _ß -clock- S ₂ "is actuated from the" 0 "to the"!. "State. With a pulse generator, the core S ₂ 'is reset, and at the end of the / ^ clock pulse, all cores remain from it taken so that ₂ 15 in the "O" state to the core S ₂ ", in which the Inin the core S ₁ 'in the manner described above infor- mation from the memory core ₁ S" wurformationen transmitted through the core K can be transmitted wherein said the. Thereafter, the / _B -Taktimpulsgeber and energy loss operates in the transmission of information sends a removal signal to the windings 16 ', by the Kopplungskem K ₂ for resetting 20 ", 28" and 30 "on the cores K _2" , S ₂ ", Κζ and this kernel at a later point in time uses 20 S ₄ ", which begins _{to reset the kernel S 2} "from the" 1 "to the" O "state, becoming a span in FIG Another embodiment induces voltage in the control winding 20 ″, which is shown in a shift register, which Konde nsators used a clockwise current in loop B " verin the transmission loop. Here are the causes. This switching of the core S ₂ "then causes separate sliding windings according to FIGS. 2 and 6 35 to flow a current through the capacitor C ₂ ", which has been omitted. A winding 18 ″ on core K ₃ ″ was produced with core K ₅ ″, which adds the further transmission circuit whose core K _s ″ wants to transfer to the state “1” and winding 60 with capacitor C ₄ ″ and the one Voltage in the winding 22 "induced, control winding 30" on the core S ₄ "and its which caused a counterclockwise current in the winding 62 with a winding 64 on a white 3 ° loop C" which tries to pull the cores S ₃ "lower coupling core K ₆ through a capacitor C ₃ and X ₄ " in the state "0" and charge the and a control winding 66 on a further capacitor C ₃ ". When the core S ₂ " storage _{core S 5 are} connected. The one discussed here is completely reset and the core IC, "on the shift register can shift information to the right in the" 1 "state, takes the / _B clock pulse. The path for the operation of the register after 35 takes the path that the Windings 16 "and 20" necessary on the Fig. 7 pulse train is shown in Fig. 8. Cores K ₂ " and S ₂ " includes, and the condenser input is assumed to be all cores in the "0" -sators C ₂ " and C ₃ "begin to discharge. With the exception of the core S ₁ ", which causes the discharge in the state, the capacitor C ₃ ""!. "state is. a clockwise current in the loop C",

When the Z _A clock pulse generator is operated, a 40 is activated which tries _{to bring the cores X 4} ", S ₃ " and K ₃ " removal signal into the windings 12", 10 ", 22" and into the state "1" while the Kon-26 "on the cores K ₁ ", S ₁ ", K ₃ " and S ₃ "sent, the capacitor C ₂ " when discharging a current in which the switching of the core S ₁ "from the" 1 "-in counterclockwise direction in the loop B " , the" 0 "state begins and thereby a voltage which resets the core K ₃ " into the "0" state induces in the control winding 10 ", which this 45 wants. Since the / ß clock pulse begins to work against each of the cores K ₂ ", S ₂ " impressed signal. If and K / ' holds in the "0" state by sending a signal in the core S ₁ "from the" 1 "to the" 0 "state to its windings 16", 20 "and 28", If the / ^ clock pulse signal starts to reset, these cores remain unchanged. The core X ₃ "is then placed clockwise into the loop A", which then resets it from the "1" to the "0" state, while trying to charge the capacitor C ₁ "and the core S ₃ " from the "0" - to the "" -. state is core K ₂ "in the""-!... convert state the will is Thus, the memory core S _2" "then switches over the core K ₂ from" 0 «- in the»!. «- to- coupling core K ₃ " in the storage _{core S 3} "information stand and induces a voltage in the windings transmitted, lung 16", which is a counterclockwise current. Finally, one possible Dimensioning

meaning in the loop B " which tries to bring the 55 such shift registers with ferrite cores attached coresS ₂ " and K ₃ " to the state" 0 ", but it should be noted that also and the capacitor C ₂ " reverse as the con- other individual parts, values and current intensities to charge capacitor C ₁ ". If the core S ₁ " can be turned back. If the clock pulses I _A , I _{B are} set and no further power flow change takes place and I _R deliver a constant current of 1.0 A, the signal from the / ^ - clock pulse generator selects the 60, the windings 36 a, 36 b, 38a, 40 a, 40 b, path that includes the windings 12 "and 10" on the 42 a and 42 b ten turns and the windings cores K ₁ " and S ₁ ", and the condensate 44 comprise five turns. In the coupling sators C ₁ ″ and C ₂ ″ begin to discharge. In circuits that cause the storage and coupling cores verder discharge, the capacitor C ₂ "binds one, the windings 10, 12, 14, 16, 18, current can clockwise in the loop B", which 6 ₅ 20, 22, 24 , 26, 28, 30, 32, 60, 62, 64 and 66 fifteen tried to include the cores K ₃ ", S ₂ " and K ₂ " in the to-windings and the capacitors C ₁ , C ₂ , stood» 1 The core K ₃ " will have a capacitance of 5 nanofarads due to the C ₃ , C ₄ and C ₅ on its winding 22" clock pulse.

Each of the storage and coupling cores can be a toroid made of a manganese-magnesium-ferrite compound with an outside diameter of 3 mm, an inside diameter of 2 mm and a height of 1.5 mm.

It is important that each of the windings in the transmission loops have the same number of turns making such circuits easy to manufacture. Furthermore, since the number of turns of the Windings on the coupling cores is the same, the circuits for the flow of information can can be used in two directions.

Claims (4)

PATENT CLAIMS: 1. Magnetic core shift memory without diodes, in which the information is transmitted between the individual stages via coupling cores, the memory cores of the even-numbered stages are reset by a first and those of the odd-numbered stages are reset by a second clock pulse source and the two clock pulse sources can be operated alternately because characterized in that in each stage one winding (20 ') of the storage core (S ₂ '), one winding (16 'or 18') of the two between this storage core (S ₂ ') and the storage cores (S ₁ ' or . S ₃ ') of the preceding or next stage arranged coupling cores (K ₂ or K ₃ ) and a capacitor (C ₂ ) are connected in series to form a loop (B') that these three windings (16 ', 18', 20 ') have the same number of turns and the same winding direction and that one of the two coupling cores (K ₂ ' or K ₃ ') together with the memory _{core (S 2} ') from the relevant clock pulse source (I _B ) in the same S is influenced inside (Fig. 6). 2. Arrangement according to claim 1, characterized in that in each stage for the right shift (Fig. 3) a winding (36 ft) of the preceding coupling core (K ₂ ) and for the left shift (Fig. 4) a winding (40 b) of the next Coupling core (K ₃ ) one behind the other with a winding (38 b or 42 b) of the storage _{core (S 2} ) can be connected to the relevant clock pulse source (Iß) . 3. Arrangement according to claim 2, characterized in that the series connection of the windings (16 "or 20") of a coupling core (K ₂ ") and the memory core (S ₂ ") of each stage - one behind the other with the corresponding series connections of the other even-numbered or odd-numbered stages - can be connected to the relevant clock pulse source (I _B ) as well as - one behind the other with the winding (18 ") of the other coupling core (K ₃ ") and the capacitor (C ₂ ") - in the loop (B") the stage in question is arranged (Fig. 7). 4. Arrangement according to one of the preceding claims, characterized in that the coupling cores (K) are reset by a further clock pulse (/ ^) on one of their windings (44), which occurs together with each clock pulse (I _A and I _B ) , but only begins with a specified time delay. Considered publications:
German Patent No. 1030071;
U.S. Patent No. 2,781,503. 1 sheet of drawings © 309 690/129 9.63