GB8811703D0 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
GB8811703D0
GB8811703D0 GB8811703A GB8811703A GB8811703D0 GB 8811703 D0 GB8811703 D0 GB 8811703D0 GB 8811703 A GB8811703 A GB 8811703A GB 8811703 A GB8811703 A GB 8811703A GB 8811703 D0 GB8811703 D0 GB 8811703D0
Authority
GB
United Kingdom
Prior art keywords
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB8811703A
Other versions
GB2206730A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gazelle Microcircuits Inc
Original Assignee
Gazelle Microcircuits Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gazelle Microcircuits Inc filed Critical Gazelle Microcircuits Inc
Publication of GB8811703D0 publication Critical patent/GB8811703D0/en
Publication of GB2206730A publication Critical patent/GB2206730A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
GB8811703A 1987-05-19 1988-05-18 Semiconductor circuit device parameter optimization Withdrawn GB2206730A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5209887A 1987-05-19 1987-05-19

Publications (2)

Publication Number Publication Date
GB8811703D0 true GB8811703D0 (en) 1988-06-22
GB2206730A GB2206730A (en) 1989-01-11

Family

ID=21975461

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8811703A Withdrawn GB2206730A (en) 1987-05-19 1988-05-18 Semiconductor circuit device parameter optimization

Country Status (3)

Country Link
JP (1) JPS6489338A (en)
DE (1) DE3817114A1 (en)
GB (1) GB2206730A (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02189607A (en) * 1989-01-18 1990-07-25 Seiko Instr Inc Voltage regulator
EP0685887B1 (en) * 1994-05-30 1998-07-01 STMicroelectronics S.r.l. A device for selecting design options in an integrated circuit
US6100747A (en) * 1994-05-30 2000-08-08 Stmicroelectronics, S.R.L. Device for selecting design options in an integrated circuit
EP0856893B1 (en) 1996-12-31 2002-05-02 STMicroelectronics, Inc. Structure and device for selecting design options in an integrated circuit
ITMI20110844A1 (en) 2011-05-13 2012-11-14 St Microelectronics Srl ELECTRONIC TRIMMING CIRCUIT

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA997868A (en) * 1972-12-20 1976-09-28 David J. Fullagar Digital adjustment of linear circuits
US4306246A (en) * 1976-09-29 1981-12-15 Motorola, Inc. Method for trimming active semiconductor devices
US4238839A (en) * 1979-04-19 1980-12-09 National Semiconductor Corporation Laser programmable read only memory
US4412241A (en) * 1980-11-21 1983-10-25 National Semiconductor Corporation Multiple trim structure
JPS5846174B2 (en) * 1981-03-03 1983-10-14 株式会社東芝 semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS6489338A (en) 1989-04-03
GB2206730A (en) 1989-01-11
DE3817114A1 (en) 1988-12-15

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)