GB2206730A

GB2206730A - Semiconductor circuit device parameter optimization

Info

Publication number: GB2206730A
Application number: GB8811703A
Authority: GB
Inventors: Andrew C Graham; Mark E Fitzpatrick
Original assignee: Gazelle Microcircuits Inc
Current assignee: Gazelle Microcircuits Inc
Priority date: 1987-05-19
Filing date: 1988-05-18
Publication date: 1989-01-11
Also published as: DE3817114A1; JPS6489338A; GB8811703D0

Description

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SEMICONDUCTOR DEVICE DESCRIPTION

This invention relates to a semicond.jc:-k-o-- device and more specifically to the optimization of such a device.

In the prior art, fusible links have been used to interconnect circuitry for a variety of reasons. For example, the development of very large scale integrated memory arrays introduced a need for spare rows and columns of memory cells in addition to the, primary memory array to assure reasonable yields. R. Smith et al. "Laser Programmable Redundancy and Yield Improvement in a 64K DRJUM," I= J. of Solid-State Circuits, SC- 16, No. 5, October, 1981. The spare rows and columns are connected to the primary memory array through fusible links. If a defectIve row is detected in the primary Mlemory arrayr appropriate fuses are blown to replace the defective row with one of the spare rows. Similarly, one of the spare columns of memory cells may be used to replace a defective column of memory cells in the primary memory array.

For a silicon-based integrated circuit, the fuses may be either electrically fusible links or laser prcgrammable links. Robert T. Smith, et al., "Redundancy Ccnsiderations in High Density memory Devices," Professional Program Session Record 26, Electro/82. A electrically fusible link means a fuse which is blown by a means of an electrical current while a laser prcgra.Tzable 'Link is one which is blown by means of a laser beam. The speed of a memory array is adversely affected when electrically f,-,sible links are used to add redundant rows or columns to the primary array while primary memory arrays with spare rows or columns added by blowing laser programmable links show no degradation of circuit performance. R. T. Smith, "Using a Laser Beam to Substitute Good Cells For Bad," Electronics, pp. 131-134, July 28, 1981. In either case, the performance of the circuit is not enhanced with respect to speed or power consumption, only the yield of usable die is enhanced.

Another approach using 'fusible links is a silicon-based circuit comprised of various gate arrays interconnected by fusible links (see Laser Path Application Note AN-1 dated June 1986 and entitled "One Day Laser Programmed Gate Arrays"). Based upon a custcrierls specification, fusible links are blown using a laser to create a specific circuit which will perform the function desired by the customer. Actually, this device is a large silicon-based circuit comprised of transistors which are interconnected with laser programmable links and various gr(:-,ms of these transistors are further interconnected with laser programmable links. To program the circuit, the links connecting the transistors are blown so that the transistors form a desired gate. Then, the programmable links connecting the group of transistors comprising the gate with other groups of transistors comprising other-gates are blown to provide the user-specified gate interconnections. The various combinations of transistors to form gates and combinations of cates to form a gate array circuit require a large number or programmable links and a large circuit.

While the large circuit provides flexibility, the size of the circuit degrades its speed in comparison to the typical gate array circuit. Also, the size of the circuit diminishes the yield per wafer. The flexibility in specifying the gate array circuit also introduces additional problems. The fuses are in close proximity to other fuses and comiDonents. With the close proximity and the iarge number of fuses, the probability that a fuse will not be blown properly increases and each circuit, which malfunctions because the fuses have been i.-,,r)rcDeriv blown, decreases the yield. Also, errors in programming the fuses cannot be detected until the device is completely programmed and tested to determine whether it performs the proper logical function. Hence, the fusible links provide flexibility, but they ate not used to enhance the performance of the circuit by providing a means to compensate for process variations.

The performance of certain silicon-based integrated circuits has been enhanced using laser trimming of capacitors and resistors. E. J. Swenson, 11Nd:YAG Lasers in Semiconductor Processing," Lasers & Anclicat-lons, 115-118, May, 1985. For example, analog circuits almost always require capacitors, but integrated circuit capacitors are difficult to fabricate to precise values. Hence, a capacitor array larger than that n ' eeded for the final circuit is fabricated. The camacitor plate area consists of many small interconnected plates. The precise capacitance needed is achieved by first using a laser to cut the interconnections between so,-ne of the plates. Then fine trimming is achieved by using the laser to drill holes in one or more of the remainina connected Dlates. Techniques such as this have been in. Dlemented only for passive elements in siliconbased integrated circuits.

In comiDound s emi condu ctor -based devices, such as GaAsbased input buffers., output buffers, memory arrays, etc., trimming of passive elements is not sufficient to enhance circuit performance. Process variations create substantial performance variaticns oil the active co.Tpnents. The variations affect the current in the circuit which in turn affects the sneed, power and functionality of the circuit. Hence, process variations may cause rejection of a chip not only for gross functionality failure, but a'so for failure with resDect to speed and power soecifications.

To successfully ccmoete with silicon-based devices, comiDound se.-nic--nt-,-,ctor-based devices must offer. a berfor- mr con at a ance better than, or at least comparable to, sili commarable cost. If the ccnpound semiconductcr-based device yield is maximized with respect to funct-;onal.;t.vr speed and power# or any one of these attributest more good die per wafer will be produced which obviously lowers the cost. Thus, process variations must be addressed in the develonment of a commercial comp-cund semi conduc tor -based die.

The effect of process variations on the operation of a compound semiconductor-based circuit is best understood by considering Figure 1. The circuit block in Figure 1 has five metal semiconductor field effect transistors (MESFET). Four of the MESFETs 10, 20, 40, 50 are enhancement type MESFETs, while one 30 is a depletion type MESFET. The circuit's input signal is applied to the gate of a first MESFET 10. The gate of the MESFET 10 is connected to the gate of a second MESFET 20. The source of both the MESFET 10 and the MESFET 20 is connected to ground. The drain of the MESFET 10 is connected to the source of a third MES-CET 30. The gate of the MES.FET 30 is connected to its source. The drain of the IMESFET 30 is connected to a supply voltage line. The drain of the MES-FET 20 is connected to the source of a fourth MESFET 40. The cate of the MESFET 40 is connected to the source of the MESFET 30 while the drain of the MESE'ET 410 is connected II..o a supply voltage line. One end of a first dicde 60 is connected to the source of the IMESFET 40 and the second end of the diode 60 is connected to the firsIC end of a second diode 61. The second end cf the diode 61 is connected to the gate cf a fifth MESFEET 50. The diode 60 and the dic-de 61 are forward biased in the d-4------t-4on from the v--'-,,-age supply terminal 47 to ground. A capacitor 62 is connected across the diode 60 and the diode 61. The source of the MESFET 50 is connected to ground and tChe drain is connected to a voltage sum ply line, typically through a load device. The drain of the MESI_= 50 -is also connected to the outmut terminal cf the ci.-cu-t.

Assuniing that the gates of the MEESFETs 10, 20 are held low, then and as the gate cf the IMESFEET 40 rises, the source of the IMESFET. 40 follows. As the MESFET 40 conductso current flows through the d-;ode 60 and the diode 61 and then the gate of the MESFET 50 becomes high which turns on the MESFET 50.

An inherent diode exists between the gate-to-source of the MESFET 40 and also an inherent diode exists between the gate-to-source of the MESFET 50. Thus, a hard clamp limit of four diodes is imposed from the gate of the MESFET 40 to ground. When this clam-p limit is reached, the power dissipated by the circuit is determined by the source current of the MESFET 40 since this current will flow through all the diodes. The exact value of the source current of the MESFET 40 is primarily determined by the threshold voltage of the MES-FET 40. If the threshold voltage of the MESFET 40 drops, the power goes up and the source current of the MESFET 40 will increase because the drop between its gate and source is set at a diode by the inherent diode.

A MESFET's inherent diode drop changes with process variations, but the changes are small and since the voltage drop across the diode is logarithmically dependent on the current, these variatlons are not significant. Elcwever, the threshold voltage of a MESFET is difficult to control both with resiDect to teziperature and with respect to orccessing variations. The poor control over the threshold voltage makes control of the current through a MESFE'T also difficult. Thus, the performance with respect to =wer and speed of a MES-FEET- is subject to significant variations. The cc-npound semi conduct c: rbased circuit designer must take into account the effects of temperature and process variations upon the threshold voltage.

The process variations make it difficult to design an ef,-'-"-4cient compound se=,-;ccnduct-,r-based circuit. For example, to spec_;_,'y the size of the MES-CET 40 in Figure 1, the circuit desicner determines the acceptable buffer speed bandwidth, i.e., the sic.,;est and highest acceptable oneratinc sr)eed f--.r the buffer. The designer then selects the size of the 1.0 such -that for the highest threshold voltage anticinated frcm process vari ations, a current is achieved 'which corresponds to the slowest acceotable sceed. After specifying the size in this manner, -6the designer may discover that process variations results in a lower threshold voltage, which generates a higher currenz through the MESFET 40. The increased current through the MESFET 40 will increase the speed and the power consumptic-n of the circuit because the source current of the MESFET 40 controls the power dissipated by the circuit. Hence, the circuit is slow at one end of the threshold voltage spectrum and burns a lot of power at the other end of the threshold voltage spectrum. The product therefore has a very broad distribution of power and speed. Efficient commercial cc.-inound semiconductor-based circuits should operate within a tight (narrow) power and speed distribution.

While the problem described here has focused on a specific circuit whose operating characteristics were determined by a single enhancement type MESFET, similar problems are encountered with the pinch-off voltage of a comiDound semiconductor demletion type MESFET, and with resistors and implant layers in compound semiconductors.

0 In accordance with the invention, a commound semiconduct-or-based device which can be olDtimized with respect to gross functionality, power specifications, and speed snecifications is provided. Cc-ilDonents within the devce, which are affected by process Variations and which affect the performance of the device, are each comprised c,.: a first- conductor, a second conduct-cr, first means interconnecting said first and secznd conductors cc.-..iDris-Jng first conducting element connected to the first conductor, first comiDonent connected to the first conducting element# and a seccnd conductIng element connected to the second conductor and to said firs-- comr)--nent, and second means interconnecting the first and second conductors comprisina a third ccnduct-;-a element ccnneczed to the first conductor, a second cz- -nent, similar to the first comnonent, connected to the third conducting element, and a fourth conductIng element connected to the second conductor and to the second component, wherein the first conducting element comprises a c 1 Q first disconnectable link, and the third conducting element comprises a second disconnectable link. The components may be transistors, resistors, capacitors, diodes or other electrical components. The compound semiconductor-based device has a first electrical state prior to programming of the multiple components and an irreversible different second electrical state after programming.

In one embodimen11-, laser programmable links comprise the disconneCtable links and programming is accomplished by using a laser to blow the fuses. Selective blowing of the fuse links permits tailoring the circuit to overcome the process variations inherent in compound semiconductor device fabrication, and permits development of a circuit with a very tight distribution with respect to power and speed. Also, if an active or passive component is defective, one of the secondary components can be used to preserve the gross functionality of the compound semi conductorbased circuit.

The invention thus provides means to overcome the degradations of circuit performance caused by processing variations by including laser programmable electrical devices in the circuit.

The present invention is further described below with reference to the accompanying drawings. These show specific embodiments but the invention is susceptible of embodiment in many different forms, so it is to be understood that the present disclosure is by way of example and is not intended to limit the scope of the invention.

In the drawings:

Figure 1 illustrates a circuit which is adversely affected by process variations, discussed above; Figure 2 illustrates the method used to permit X optimization in accordance with the invention; Figure 3a, 3b, and 3c illustrate alternative placements of laser programmable fuses in a electrical device; Figure 4 illustrates the layout for a typical laser programmable fuse; and Figures Sa, 5b and Sc illustrate passive components implemented according to the present invention.

1 Q" One embodiment of this invention is shown in Figure 2. The circuit's input signal is applied to the gate of a first MESFET 10A. The gate of the MESFET IOA is connected to the gate of a second MESFET 20A. The source of both the MESFET 10A and the MESFET 20A is connected to ground. The drain of the MESFET 10A is connected to the source of a third MESFET 30A. The gate of the MESFET 30A is connected to its source. The drain of the MESFET 30A is connected to a supply voltage line. The drain of the second MESFET 20A connected to a conductor, the source line 71 of MESFET 40A. Unlike the prior art shown in Figure 1 where the fourth MES.PET 40 is a single device, IMESFET 40A is comprised of four senarate MESFETs 41, 42, 43, 44. The drains of MESFETs 41, 42, 43, 44 are each c:;nnected to a first conductor, common supply voltage line 70, throuch respective conducting elements, metal lines 72, 73, 74, 75 and the a rst.-7,r l gates are all connected together. The source of M_---'I is connected to the first end of a conductIng element, i.e.

a disconnectable link comprised of a laser programmable fuse 80. The second end of the conducting element, the second end of laser programmable fuse 80, is connected to a second conductor, the cc.-non source line 71. The sources of the MES-FETs 42, 43, 44 are also each connected to the second conductor, cc,-r,.-ion source line 71, through a conduc-,ng element, a disconnectable link comprised of a laser programmable fuse 80. One end of a first diode 60A is connected to the common source line 71 of the MESFET 40A and the second end of the diode 60A is connected to the first end of a second diode 61A. The diode 60A and the diode 61A are forward biased in the from the voltage sur)nly terminal 47A to cround. The second end of the dicde 61A is connected to the gate of a fifth MESFET 50A. A capacitcr 62A is connected across the diode 60A and the diode 61A.

The source of the MESFET 50A is connected to ground and the drain is connected to a voltage supply line, typically through a load device. The drain of the MESFE71 SOA is also connected to the output terminal of the circuit. As used in this description, a compound semiconductor such as GaAs is generally contemplated, but this invention's novel optimization of circuit performance may be implemented in any semiconductor-based device.

The laser programmable fuse 80 in Figure 2 is comDrised of the same metal that is used to make one of the other metal layers in the circuit. As used in this descripticn, metal layers such as gold are generally contemplated, but other types of conductive layers can be used and are, hence, included in the expression "metal layers" The fuse may alternatively be placed in the drain line of each MESFET comprising MESFET 40A as shown in Figure 3a, or in both the drain and the source lines as shown in Figure 3b or in the gate lines as shown in Figure 3c. The phlilsical placement of the fuses on the chip is determin-d by the layout of the circuit because sufficient clear space must be allocated about the fuse to allow reliable blowing of the fuse wil-hzut the possibility of damage to other elements of the circuit. As shown in Figure 4, this typically requires a fuse of at least 12 microns in length and at most 2 micrcns in width. There should be approximately a 12 micron by 6 micron region of clear space on each side of the fuse.

In an actual compound semiconduc'L-.or-based-integrated circu-;t, a component whose zerf,:5r,-ance may be a.Efected adversely by process variations can be comprised of a first conductor, a second conductor, first means interconnecting the first- and second conductors comprising a first conducting element, which is a disconnectable link, a first comr)cnent affected adversely by process variations connected to the disconnectable link, and a second conducting element, such as either a d-; scc-,nectable link or a metal line, ccnnected t-o the C--.-.zcnent and the second conductor and a second means inzercnnect-;ng the first and second conductors comr)risina a third conduct-Ing element, which is a disconnectable l-lnk, a secc-,d cz:nmcnent, s--m-;lar to the 1 Qt first component, connected to the disconnectable link, and a fourth conducting element, such as either a disconnectable link or a metal line, connected to the comDonent and the second conductor.

For example, Figures 5a, 5b and Sc show passive components of a compound semiconductor-based device implemented according to the present invention. The ccmponents are arranged such that they may be combined so as to optimize the performance of the particular compound semiconductorbased cevice. The optimization of the MES-FET 40A in Figure 2 will make optimization of the other embodiments obvious to one skilled in the art.

In practice the number of interconnecting means selected is a trade-off based upon the anticipated variability of the fabrication process, the nature of the speed and power distributions for the carticular device, and the cost and complexity of adding each additional interconnecting means. For the MESFET 40A in thi. particular circuit, a MES17= with a nominal size of 40 microns should meet the speed and 1Dower swec-J-'--ca"- Jcns, but since the current through the MESFET 40A de:ermines the performance of the circuit, as explained in cc-nsidering Figure 1, MESFET 40A is comnrised of four IMES-FEE'Ts 41, 42, 43, 44. MES-FET 41 is referred to as the primary component while MES.FETS 42, 43, 44 are called secondary c--.mponents. The primary component 41 is a 40 micron MES-PET- while the second comoonent 42 is a 20 micron MESFET. The th-,--d cc-l, r)onent 43 is a 10 micron MESFET and t-he fourth ccmoonent 44 is a five micron MESFET. This configuratIon provides a MESFEET 40A with a size that may range frcm 5 microns to 75 microns and the MESFET 40A is such that the size can be incremented in 5 The mrecise sizes of the components here are not essential to the invention. The sizes are shown to best illustrate the principles of the i, nven,.-.-4cn. The sizes selected for the ccToonents should be such that the primary cc.Tzonent is sufficient if the process variations are nominal. The size and number of the secondary components should be selected based upon the micron segments described anticipated process variations and the performance specifications. For example, if the performance sDecifications are tight, then the commonents should be designed such that the resulting component may be chanced by small increments over a wide rance similar to that described here for MESFET 40A.

As the MESFET 40A becomes larger, the current out of the MESFET 40A increases which in turn increases the speed of the device. Thus, for the circuit in Figure 2, a desired speed at a given power level may be achieved by selecting an appropriate size for the MESFET 40A.

For a particular die if an initial inspection indicates that the threshold voltage for the MESFEET 40A is very high which implies a small current through the device and consequently a slower circuit speed, more of the secondary commonents will be left connected thereby increasing the current through the MESFET 40A and also thereby pulling the speed at a given power level. ' However, if it is determined that the voltage thresnold is low for the MES-FE'T 40A, which iir.m1-4es a larce current thr--uch the device and consequently a higher circuit power, a few cf the secondary commonents of the MESFET 40A will be selectively removed by blowing out the appropriat-e fuses to bring the power back to its original specification. This procedure allows cp,l,,, the circuit so as to retain a fairly constant izing L. power level and consequently speed over wide variations in threshold voltage.

To blow the fuses and select a given size for a device the die is placed on an ESI 8000B Laser Programming System. A ccniDuter, which has been programmed to compute the fuse r)ositions to be blown, provides positioning information to a Q switched YAG laser. When the laser is properly aligned to the die, the fuse is blown with a laser pulse which has a wave length of 1.06Lm and a beam diameter of 6 microns. The device imc-lemented in accordance with this invention has a first electrical state prior to program,m.nc and an irreversible different second electrical state after programming.

IP is

Claims

1. A semiconductor device having means for optimization of an operating parameter of the device comprising first means interconnecting a first conductor and a second conductor and comprising a first conducting element connected to the first conductort a first circuit element connected to the first conducting element, and a second conducting element connected to the second conductor and to the first circuit element, and second means interconnecting the first and second conductors and comprising a third conducting element connected to the first conductor, a second circuit element connected to the third conducting element, and a fourth conducting element connected to the second conductor and to the second circuit element, wherein the first conducting element comprises a first disconnectable link, and 'the third conducting element comprises a second disconnectable link.

2. A device as claimed in claim 1 wherein the first and second circuit elements each comprise a transistor.

3. A device as claimed in claim 2 wherein the or each transistor is a field effect transistor.

4. A device as claimed in claim 1 wherein the first and second circuit elements each comprise a. diode.

5. A device as claimed in claim 1 wherein the first and second circuit elements each comprise a resistor.

6. A device as claimed in claim 1 wherein the first and second circuit elements each comprise a capacitor.

7. A device as claimed in any preceding claim wherein the second conducting element comprises a third disconnectable linke and the fourth conducting element comprises a fourth disconnectable link.

8. A device as claimed in any one of claims 1-6 wherein the second conducting element and the fourth conducting element each comprise a metal line.

9. A device as claimed in any preceding claim wherein the disconnectable links each comprise a laser programmable fuse.

10. A device as claimed in any preceding claim, the device comprising a compound semi conductor-ba sed device.

11. A semiconductor device having means for optimization of an operating parameter thereof substantially as herein described with reference to Figure 2, Figure 3a, Figure 3b, Figure 3c, Figure 4, Figure 5a, Figure 5b or Figure Sc of the accompanying drawings.

ubl.ished 19813 at The Paten: Off,e- State House. 6671 High Hoborn, LondonIATC1R 4TP Further copies may be obtainel, from The Paterit office. SaleS Brarch. St Mary Cray. Orpington, 7Zent BRZ- 3RD Frinted by 11,.L. tiplex ecb-mcpips ltd. St Mary Cray. Ker- Con. 187