GB8727958D0 - Improved process in manufacture of integrated circuits - Google Patents
Improved process in manufacture of integrated circuitsInfo
- Publication number
- GB8727958D0 GB8727958D0 GB878727958A GB8727958A GB8727958D0 GB 8727958 D0 GB8727958 D0 GB 8727958D0 GB 878727958 A GB878727958 A GB 878727958A GB 8727958 A GB8727958 A GB 8727958A GB 8727958 D0 GB8727958 D0 GB 8727958D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- manufacture
- integrated circuits
- improved process
- wafer
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/60—Substrates
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
A step and repeat process using a mask transfers circuit information onto a die forming a portion of a wafer (Fig 3). The circuit information is confined within the mask which is of octagonal shape to maximise the number of steps across a given surface area of wafer and to provide a maximum area of transferred circuits. <IMAGE>
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8727958A GB2212944B (en) | 1987-11-30 | 1987-11-30 | Improved process in the manufacture of integrated circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB8727958A GB2212944B (en) | 1987-11-30 | 1987-11-30 | Improved process in the manufacture of integrated circuits |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8727958D0 true GB8727958D0 (en) | 1988-01-06 |
GB2212944A GB2212944A (en) | 1989-08-02 |
GB2212944B GB2212944B (en) | 1991-10-23 |
Family
ID=10627745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB8727958A Expired - Fee Related GB2212944B (en) | 1987-11-30 | 1987-11-30 | Improved process in the manufacture of integrated circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB2212944B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2590700B2 (en) * | 1993-09-16 | 1997-03-12 | 日本電気株式会社 | Projection exposure equipment |
-
1987
- 1987-11-30 GB GB8727958A patent/GB2212944B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2212944A (en) | 1989-08-02 |
GB2212944B (en) | 1991-10-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE2961204D1 (en) | Process for manufacturing integrated implanted logic circuits with a hardened photoresist mask | |
KR900015344A (en) | Process of forming high and low voltage CMOS transistors on a single integrated circuit chip | |
DE3270560D1 (en) | Semiconductor intregrated circuits and manufacturing process thereof | |
EP0242744A3 (en) | Method of manufacturing an integrated circuit semiconductor device comprising a lithography step | |
KR900015317A (en) | The process of forming a vertical bipolar transistor and a high-voltage CMOS transistor in a chip of a single integrated circuit | |
EP0092871A3 (en) | Semiconductor integrated circuits and method of manufacturing | |
EP0234387A3 (en) | Method of removing photoresist on a semiconductor wafer | |
GB2163901B (en) | A semiconductor integrated circuit device and a process for manufacturing such a device | |
EP0443857A3 (en) | A method for producing a layout of element portions for a semiconductor integrated circuit | |
DE3068823D1 (en) | A method of fabricating a semiconductor integrated circuit device | |
GB9105973D0 (en) | Method of forming a fine pattern on a semiconductor having a step therein | |
SG82390G (en) | A semiconductor integrated circuit device and method of production thereof | |
JPS558097A (en) | Method of manufacturing semiconductor ic | |
EP0121412A3 (en) | Method of forming by projection an integrated circuit pattern on a semiconductor wafer | |
GB2228619B (en) | Method of fabricating semiconductor integrated circuits | |
DE3270064D1 (en) | Electron beam pattern transfer device and method for aligning mask and semiconductor wafer | |
FR2531812B1 (en) | "BI-CMOS-IC" TYPE INTEGRATED SEMICONDUCTOR CIRCUIT DEVICE AND ITS MANUFACTURING PROCESS | |
IT7919830A0 (en) | MOLD AND PROCEDURE FOR TRANSFER ENCAPSULATION OF SEMICONDUCTOR ELECTRONIC DEVICES. | |
IL82436A0 (en) | Process of forming a positive pattern in a photoresist layer | |
GB2212944B (en) | Improved process in the manufacture of integrated circuits | |
EP0239060A3 (en) | Method for manufacturing semiconductor integrated circuits including cmos and high-voltage electronic devices | |
JPS5585052A (en) | Semiconductor integrated circuit and method of fabricating same | |
JPS5664464A (en) | Method of manufacturing semiconductor integrated circuit | |
EP0485303A3 (en) | Process for fabricating an integrated circuit by a repetition of exposure of a semiconductor pattern | |
JPS57204033A (en) | Formation of fine pattern |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19981130 |