GB868840A - Improvements in or relating to circuit arrangements for dividing binary numbers - Google Patents
Improvements in or relating to circuit arrangements for dividing binary numbersInfo
- Publication number
- GB868840A GB868840A GB2135756A GB2135756A GB868840A GB 868840 A GB868840 A GB 868840A GB 2135756 A GB2135756 A GB 2135756A GB 2135756 A GB2135756 A GB 2135756A GB 868840 A GB868840 A GB 868840A
- Authority
- GB
- United Kingdom
- Prior art keywords
- dividend
- gate
- delay
- gates
- delays
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
868,840. Digital electric calculating-apparatus. NATIONAL RESEARCH DEVELOPMENT CORPORATION. July 8, 1957 [July 10, 1956], No. 21357/56. Class 106 (1). An electrical binary series-mode divider is adapted to effect division by a small odd integer of the form 2<SP>n</SP>+1. As shown, Fig. 5, for effecting division by five, the dividend x on a lead 40 passes via a mix 43 in true form to a line 10 and simultaneously after inversion at 12 to a line 11. The lines 10 and 11 supply respective gates a, b which control entry to five unit delays 13-17. The output from the delay 13 conditions the gate b of the delay 13 and the gate a of the delay 15. The other four delays each condition two entry gates as shown. The dividend is applied twice to the mix 43, the first application of the dividend being followed by a " gap signal " of two " 0 " digits applied through a gate 44 to the mix 43, which gap signal is followed directly by a second application of the dividend derived from a delay 41. A pulse on a lead 60 in synchronism with the first digit pulse of the second application of the dividend conditions gates 47, 48, 49 which are arranged to recede in binary form the output of that one of the delays 14-17, which is activated and which represents the decimal remainder 1-4, the serial binary form of this remainder appearing at an output R. During the second application of the dividend a gate 54 is opened to pass the quotient which appears serially from gates 21, 23 controlled respectively by the complement of x and by x, the gates 21, 23 controlling outputs from the respective delays 14, 16 and 13, 15, 17. The apparatus is reset by a pulse DV4 which inhibits a gate 56 to cut off the signals applied to the delays 14-17 when no signal is applied to the lead 40 and opens the gate b of delay 13 representing " 0," which is then maintained activated by feed-back. An arrangement for division by three is described (Figs. 2 and 3, not shown). The mathematical principles underlying the invention are set forth in detail in the Specification. Specification 789,207 is referred to.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2135756A GB868840A (en) | 1956-07-10 | 1956-07-10 | Improvements in or relating to circuit arrangements for dividing binary numbers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2135756A GB868840A (en) | 1956-07-10 | 1956-07-10 | Improvements in or relating to circuit arrangements for dividing binary numbers |
Publications (1)
Publication Number | Publication Date |
---|---|
GB868840A true GB868840A (en) | 1961-05-25 |
Family
ID=10161540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2135756A Expired GB868840A (en) | 1956-07-10 | 1956-07-10 | Improvements in or relating to circuit arrangements for dividing binary numbers |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB868840A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2179770A (en) * | 1985-08-28 | 1987-03-11 | Plessey Co Plc | Method and digital circuit for fixed coefficient serial multiplication |
GB2555459A (en) * | 2016-10-28 | 2018-05-02 | Imagination Tech Ltd | Division synthesis |
-
1956
- 1956-07-10 GB GB2135756A patent/GB868840A/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2179770A (en) * | 1985-08-28 | 1987-03-11 | Plessey Co Plc | Method and digital circuit for fixed coefficient serial multiplication |
GB2555459A (en) * | 2016-10-28 | 2018-05-02 | Imagination Tech Ltd | Division synthesis |
GB2555459B (en) * | 2016-10-28 | 2018-10-31 | Imagination Tech Ltd | Division synthesis |
US10409556B2 (en) | 2016-10-28 | 2019-09-10 | Imagination Technologies Limited | Division synthesis |
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