GB1147539A - Method and apparatus to effect binary to decimal conversion - Google Patents

Abstract

1,147,539. Binary to decimal conversion. KOZPONTI FIZIKAI KUTATO INTEZET. 18 April, 1966, No. 16964/66. Heading G4A. Binary digital words are converted rapidly to decimal form by adding or subtracting a power of ten to the binary number or its complement until overflow or zero is reached, registering the number of these operations less one, incrementing or decrementing the result in unit binary steps until said power of ten or its complement is reached and separately registering the number of these unit binary steps. In a first embodiment (Fig. 1), the binary number K(0<K<2<SP>N</SP>) to be converted is initially entered into an accumulator unit 6. On receiving a Start signal a the binary number is complemented and by means of a control unit 3 a binary quantity equal to 10<SP>m</SP>(0<m<N log 2 10) is added (once for each pulse from a clock pulse generator 1) into the accumulator unit 6 which has provision for end-around-carry until the resulting sum overflows. For each addition of 10<SP>m</SP> to the number in unit 6, the control unit 3 increments by one the 10 m stage of a decimal counter 10 in which the result is generated. On detecting overflow from unit 6, overflow indicator 7 closes gates 2 and 4 and opens gates 5 and 9, the timing being such that the closing of gate 4 blocks the final pulse from unit 3 to counter 10. Clock pulses through now open gate 5 cause accumulator unit 6 and counter 10 (units input) to be incremented in step until the number in unit 6 equals 10<SP>m</SP> as detected by comparator 8. This causes gate 5 to be closed and a comparison completed signal b to be generated. In a worked example N=6 and m=1. In a modified embodiment the following differences apply: the binary number in unit 6 is not complemented, the quantity 10<SP>m</SP> is subtracted (by addition of complements), change of sign is detected by unit 7 and the intermediate result in unit 6 is decremented until equal to the complement of 10<SP>m</SP>. The addition of 10<SP>m</SP> or its complement may be in parallel or serial mode.