GB984147A - Reversible decade for an electronic decimal counter - Google Patents

Reversible decade for an electronic decimal counter

Info

Publication number
GB984147A
GB984147A GB2510563A GB2510563A GB984147A GB 984147 A GB984147 A GB 984147A GB 2510563 A GB2510563 A GB 2510563A GB 2510563 A GB2510563 A GB 2510563A GB 984147 A GB984147 A GB 984147A
Authority
GB
United Kingdom
Prior art keywords
stage
gates
decimal counter
inhibiting
june
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB2510563A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel CIT SA
Original Assignee
CIT Compagnie Industrielle des Telecommunications SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CIT Compagnie Industrielle des Telecommunications SA filed Critical CIT Compagnie Industrielle des Telecommunications SA
Publication of GB984147A publication Critical patent/GB984147A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers

Landscapes

  • Exchange Systems With Centralized Control (AREA)
  • Logic Circuits (AREA)

Abstract

984, 147. Electronic counters. C.I.T. COMPAGNIE INDUSTRIELLE DES TELECOMMUNICATIONS. June 24, 1963 [June 28, 1962], No. 25105/63. Heading G4A. A reversible binary-coded decimal counter has each stage controlled by inhibiting gates. Impulses to be counted are applied to input terminals E 0 , E 1 , according to whether addition or subtraction is required as terminal U 1 or U 2 is marked. Each stage except the second has four inhibiting gates such as VN1-VN which receive inputs from the corresponding side 0,1 of the associated stage such as A. Only one of the four gates is not inhibited and passes a pulse. The counter operates in binary fashion except that stage B has five inhibiting gates, three of which VN7-VN9 are conrolled by outputs from S 0 D, S 1 D, S 0 C, respectively.
GB2510563A 1962-06-28 1963-06-24 Reversible decade for an electronic decimal counter Expired GB984147A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR902254A FR1360158A (en) 1962-06-28 1962-06-28 Reversible decade for electronic decimal counter

Publications (1)

Publication Number Publication Date
GB984147A true GB984147A (en) 1965-02-24

Family

ID=8782021

Family Applications (1)

Application Number Title Priority Date Filing Date
GB2510563A Expired GB984147A (en) 1962-06-28 1963-06-24 Reversible decade for an electronic decimal counter

Country Status (3)

Country Link
DE (1) DE1210915B (en)
FR (1) FR1360158A (en)
GB (1) GB984147A (en)

Also Published As

Publication number Publication date
DE1210915B (en) 1966-02-17
FR1360158A (en) 1964-05-08

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