GB8304462D0 - Semiconductor structure - Google Patents
Semiconductor structureInfo
- Publication number
- GB8304462D0 GB8304462D0 GB838304462A GB8304462A GB8304462D0 GB 8304462 D0 GB8304462 D0 GB 8304462D0 GB 838304462 A GB838304462 A GB 838304462A GB 8304462 A GB8304462 A GB 8304462A GB 8304462 D0 GB8304462 D0 GB 8304462D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- semiconductor structure
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US35243982A | 1982-02-25 | 1982-02-25 |
Publications (3)
Publication Number | Publication Date |
---|---|
GB8304462D0 true GB8304462D0 (en) | 1983-03-23 |
GB2115609A GB2115609A (en) | 1983-09-07 |
GB2115609B GB2115609B (en) | 1986-04-30 |
Family
ID=23385144
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08304462A Expired GB2115609B (en) | 1982-02-25 | 1983-02-17 | Semiconductor structure manufacturing method |
Country Status (3)
Country | Link |
---|---|
JP (1) | JPS58158943A (en) |
DE (1) | DE3306702A1 (en) |
GB (1) | GB2115609B (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2206994A (en) * | 1987-06-08 | 1989-01-18 | Philips Electronic Associated | Semiconductor device |
GB2323706B (en) * | 1997-03-13 | 2002-02-13 | United Microelectronics Corp | Method to inhibit the formation of ion implantation induced edge defects |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL173110C (en) * | 1971-03-17 | 1983-12-01 | Philips Nv | METHOD FOR MANUFACTURING A SEMI-CONDUCTOR DEVICE APPLICATING ON A SURFACE OF A SEMI-CONDUCTOR BODY AT LEAST TWO PART-LAYERS OF DIFFERENT MATERIAL COATING. |
JPS5361285A (en) * | 1976-11-15 | 1978-06-01 | Hitachi Ltd | Production of semiconductor device |
US4187125A (en) * | 1976-12-27 | 1980-02-05 | Raytheon Company | Method for manufacturing semiconductor structures by anisotropic and isotropic etching |
CA1090006A (en) * | 1976-12-27 | 1980-11-18 | Wolfgang M. Feist | Semiconductor structures and methods for manufacturing such structures |
JPS5731153A (en) * | 1980-08-01 | 1982-02-19 | Nec Corp | Manufacture of semiconductor device |
-
1983
- 1983-02-17 GB GB08304462A patent/GB2115609B/en not_active Expired
- 1983-02-25 JP JP3068083A patent/JPS58158943A/en active Pending
- 1983-02-25 DE DE19833306702 patent/DE3306702A1/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
JPS58158943A (en) | 1983-09-21 |
GB2115609A (en) | 1983-09-07 |
GB2115609B (en) | 1986-04-30 |
DE3306702A1 (en) | 1983-09-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940217 |