GB822095A - Improvements in computing devices - Google Patents
Improvements in computing devicesInfo
- Publication number
- GB822095A GB822095A GB1714557A GB1714557A GB822095A GB 822095 A GB822095 A GB 822095A GB 1714557 A GB1714557 A GB 1714557A GB 1714557 A GB1714557 A GB 1714557A GB 822095 A GB822095 A GB 822095A
- Authority
- GB
- United Kingdom
- Prior art keywords
- winding
- source
- input
- core
- energized
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/16—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using saturable magnetic devices
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/383—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Physics (AREA)
- Measuring Magnetic Variables (AREA)
Abstract
822,095. Circuits employing bi-stable magnetic cores. SPERRY RAND CORPORATION. May 30, 1957, No. 17145/57. Class 40 (9). An exclusive OR gate comprises a core with a power winding 21 energized by a train of pulses in one sense and energized in the other sense by a source of D.C. in the intervals between pulses so as to switch the core to and fro between its remanent saturated states, two input windings, 22 and 23, being such that an input to either inhibits switching of the core in one sense so that the consequent low impedance of the winding 21 causes the generation of an output but the coincidence of inputs produces no inhibition and no output. As shown, an alternating source of square waveform seen at A in Fig. 3 is applied to terminal 24 so that positive half-cycles energize winding 21 over diode D3 and resistor R2 to negative D.C. source- V and, if only magnetizing current flows, this does not appear across R2 due to an equal reverse current from -V to earth over rectifier D4. During half-cycles when terminal 24 is disconnected, the source - V switches the core back over rectifier D4, winding 21 and resistor R1. The input windings comprise the halves 22, 23 of a centre-tapped winding and the sources of input signals are of low impedance and deliver inputs to terminals 26 and 27 coincident with negative half-cycles of the square wave source as seen at B and C, Fig. 3. Either input finds an earth with the other source so that if both inputs are present at once neither input winding is energized. If one input is present the flux due to D.C. source -V in winding 21 is neutralized so that the subsequent positive half-cycle of the square wave source finds low impedance in winding 21 and develops an output across resistor R2 which is extracted over rectifier D5 from terminal 25 as seen at D in Fig. 3.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US458038A US2913594A (en) | 1954-09-24 | 1954-09-24 | Quarter adder |
DES53675A DE1063411B (en) | 1957-05-29 | 1957-05-29 | Adding device |
GB1714557A GB822095A (en) | 1957-05-30 | 1957-05-30 | Improvements in computing devices |
CH361937D CH361937A (en) | 1957-05-30 | 1957-07-11 | Quarter adders on computing devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB1714557A GB822095A (en) | 1957-05-30 | 1957-05-30 | Improvements in computing devices |
Publications (1)
Publication Number | Publication Date |
---|---|
GB822095A true GB822095A (en) | 1959-10-21 |
Family
ID=10090074
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB1714557A Expired GB822095A (en) | 1954-09-24 | 1957-05-30 | Improvements in computing devices |
Country Status (2)
Country | Link |
---|---|
CH (1) | CH361937A (en) |
GB (1) | GB822095A (en) |
-
1957
- 1957-05-30 GB GB1714557A patent/GB822095A/en not_active Expired
- 1957-07-11 CH CH361937D patent/CH361937A/en unknown
Also Published As
Publication number | Publication date |
---|---|
CH361937A (en) | 1962-05-15 |
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