GB728113A - Improvements in or relating to pulse width discriminator circuits - Google Patents
Improvements in or relating to pulse width discriminator circuitsInfo
- Publication number
- GB728113A GB728113A GB2327653A GB2327653A GB728113A GB 728113 A GB728113 A GB 728113A GB 2327653 A GB2327653 A GB 2327653A GB 2327653 A GB2327653 A GB 2327653A GB 728113 A GB728113 A GB 728113A
- Authority
- GB
- United Kingdom
- Prior art keywords
- input
- pulses
- pulse width
- gate
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/08—Separation of synchronising signals from picture signals
- H04N5/10—Separation of line synchronising signal from frame synchronising signal or vice versa
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Manipulation Of Pulses (AREA)
Abstract
728,113. Pulse width discriminating circuits. STANDARD TELEPHONES & CABLES, Ltd. Aug. 24, 1953, No. 23276/53. Class 40 (6). A pulse width discriminating circuit for responding only to pulses of a predetermined minimum duration comprises a gate to one input of which the incoming pulses are applied via a delay circuit and to the other of which they are applied via an integrating circuit so that the gate produces an output only when the output of the integrating circuit has an amplitude exceeding a predetermined level. The Figure shows a pulse width discriminating circuit in which the input pulses at terminal 4 are applied via cathode-follower stage 5 and delay network 7 to the control grid of gating valve 1 and also via integrating circuit. 9, 10 to the suppressor grid of valve 1. The gate is normally closed but when due to a pulse of long duration being applied at the input the voltage at the integrating circuit 9, 10 exceeds a predetermined amplitude, Fig. 2 (not shown), the gate opens and a portion of this longer duration pulse after being delayed by network 7 is passed to the output terminal 18. The delay time of network 7 is less than the duration of the wider pulses it is required to pass and preferably greater than that of the narrower pulses in the input train. Rectifier 20 is poled to expedite the discharge of capacitor 10 in the absence of any input at terminal 4. Reference has been directed by the Comptroller to Specification 582,330.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2327653A GB728113A (en) | 1953-08-24 | 1953-08-24 | Improvements in or relating to pulse width discriminator circuits |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB2327653A GB728113A (en) | 1953-08-24 | 1953-08-24 | Improvements in or relating to pulse width discriminator circuits |
Publications (1)
Publication Number | Publication Date |
---|---|
GB728113A true GB728113A (en) | 1955-04-13 |
Family
ID=10193043
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2327653A Expired GB728113A (en) | 1953-08-24 | 1953-08-24 | Improvements in or relating to pulse width discriminator circuits |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB728113A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3558916A (en) * | 1968-02-28 | 1971-01-26 | Tektronix Inc | Responsive to input signals of a selectable duration |
-
1953
- 1953-08-24 GB GB2327653A patent/GB728113A/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3558916A (en) * | 1968-02-28 | 1971-01-26 | Tektronix Inc | Responsive to input signals of a selectable duration |
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