GB2583197A - Hybrid insulated gate multi-structure and multi-material transistor - Google Patents

Abstract

This document defines the characteristics of Hybrid Insulated Gate Multi-structure and multi-material Transistor, that is to say "Hybrid IGMT", as power electronics transistor. This transistor is characterized with a structure of internal conduction substrate composed of vertical channels, distinguishing between channels with high electrical conductivity and insulated channels. This peculiarity distinguishes Hybrid IGMT from any other power electronics transistor and brings many advantages, most of all the significant reduction, till absence, of switching losses. Within description a specific implementation of conductive channels is introduced, consisting in a composite structure called "Si // C", which allows the fulfillment of constant and very low conduction power losses in a wide operating electrical and thermal range. Hybrid IGMT is intended for application in vehicle electric traction, also in low-voltage or medium- voltage electric systems requiring DC-AC or AC-DC conversion with high stability, long operating life and low power losses.

Claims (2)

1. Claim n.l: Hybrid Insulated Gate Multi-structure and multi-material Transistor (called "Hybrid IGMT") is a power electronic transistor with three electric contacts, exactly gate, emitter and collector, referring to vocabulary for power electronics transistors, such as Trench IGBTs, where gate contact is electrically insulated (prior art portion). Hybrid Insulated Gate Multi-structure and multi-material Transistor internal structure consists in following superimposed regions, which are in electric contact one another and which are here described from top layer to bottom layer of the transistor: â ¢ Electrical contacts of insulated gate and emitter on the same plane â ¢ N+ doped semiconductor region under emitter contact â ¢ P doped semiconductor region in electrical contact with gate, which may include also a buried part of insulated gate â ¢ "Composite conduction substrate" â ¢ P+ doped semiconductor region for collector contact â ¢ Collector electrical contact And it is characterized in that: â ¢ The "composite conduction substrate", which is the region placed under gate and emitter contacts plane and above collector contact and which lets emitter and collector be in electrical contact, is completely included under p-type doped region in contact with insulated gate and above p+-type doped region for collector contact and is implemented with a structure of vertical channels, which may be classified as electrical conductive channels with high value of conductivity, called "conduction channels", and electrically insulated or very-low conductive channels, called "lateral channels"; â ¢ Vertical channels composing the "composite conduction substrate", as reported in previous sentences, are so characterized: â   There is only one electrically insulated or very-low conductive channel placed under the gate contact and above the collector contact and this channel is called "left lateral channel" (only for quicker understanding, reference sign A.7 in FIG. n.l may be watched); â   There are one or many electrically high-conductive vertical channels placed under the emitter region and above the collector contact, called "conduction channels" (only for quicker understanding, reference sign A.6 in FIG. n.l may be watched).

2. Claim n.2: Hybrid Insulated Gate Multi-structure and multi-material Transistor, as claimed in Claim n.l, is characterized with a substrate called "composite conduction substrate" made of vertical channels placed under the emitter region and above the collector region, called "conduction channels", which might be implemented using materials with high electrical conductivity and whose structure has been already explained in previous Claim n.l. In the best implementation of Hybrid Insulated Gate Multi-structure and multi-material Transistor, intended as reference but not exclusive implementation, "conduction channels" are implemented through "Si // C", where "Si // C" identifies a vertical structure consisting of n- type highly-doped extrinsic silicon and carbon connected in electrical parallel. Electrical conductivity of "Si // C" composite structure is a function of transistor operating temperature T and it is described through following formula (Equationl,Equation 2,Equation3): â where: â ¢ aSi(T) = q*ND * Î1⁄4Î , â ¢ aSi(T2) = Osi(Ti) * T!m/T2m, â ¢ psi(T) is the upper limit of pSi//c(T) and pSi(T) « pc(T), â ¢ Equation 2: If Ti < T < T2, psi//c(T) = « « Ï , meaning in this way that resistivity, as well as conductivity, of extrinsic silicon and resistivity, as well as conductivity, of carbon have the same value in the specified thermal range, Equation 3: If T > T2, psl//c(T = psi(^pc (^ â Pc( ) , pc(T) is the upper limit " Psi(.U+Pc(.U of psi//c(T), pc(T) « psi(T), where: â ¢ Psi // c(T) = "Si // C" electrical resistivity as a function of transistor operating temperature T â ¢ psi(T) = Silicon electrical resistivity as a function of transistor operating temperature T â ¢ pc(T) = Carbon electrical resistivity as a function of transistor operating temperature T â ¢ osi(T) = Silicon electrical conductivity as a function of transistor operating temperature T â ¢ q = Electron charge of nominal value equal to 1.60 · 10 19 C â ¢ ND = Concentration of doping in silicon â ¢ Î1⁄4Î = Electron mobility of nominal value equal to 1500 cm2/(V-s) at T = 300 K â ¢ m = Parameter of nominal value equal to 1,5 â ¢ Ti and T2 = threshold temperature values, which are a function of ND and for which shall result Ti < Ϊ2. Resistivity formula, as reported above, expresses and is implemented through electrical parallel of highly-doped extrinsic silicon and carbon. Hybrid Insulated Gate Multi-structure and multi-material Transistor which implements conduction channels as per above formula is called "Hybrid IGMT Si // C".