WO2019082220A1 - Hybrid insulated gate multi-structure and multi-material transistor - Google Patents

Hybrid insulated gate multi-structure and multi-material transistor

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Publication number
WO2019082220A1
WO2019082220A1 PCT/IT2018/050203 IT2018050203W WO2019082220A1 WO 2019082220 A1 WO2019082220 A1 WO 2019082220A1 IT 2018050203 W IT2018050203 W IT 2018050203W WO 2019082220 A1 WO2019082220 A1 WO 2019082220A1
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WO
WIPO (PCT)
Prior art keywords
hybrid
transistor
channels
electrical
conduction
Prior art date
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PCT/IT2018/050203
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French (fr)
Inventor
Valentina DADDI
Original Assignee
Daddi Valentina
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Publication date
Application filed by Daddi Valentina filed Critical Daddi Valentina
Priority to GB2007371.4A priority Critical patent/GB2583197B/en
Publication of WO2019082220A1 publication Critical patent/WO2019082220A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
    • H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs

Definitions

  • Hybrid IGMT Hybrid Insulated Gate Multi-structure and multi-material Transistor
  • Hybrid IGMT use is tailored for implementation of converters and inverters for drive and control of electric machines, it is especially thought for applications requiring fast dynamic, stability for wide temperature range, low power conduction losses and low switching losses. Therefore, Hybrid IGMT is intended mainly as power electronics transistor to be applied in electric and hybrid vehicle traction systems and may be used also in low-voltage or medium-voltage energy conversion applications.
  • IGBT is currently applied in many fields, such as in industry machinery, in electric vehicles and for energy conversion purposes; its implementation is tailored for each peculiar application through proper dimension evaluation and characterisation of extrinsic silicon, generally for applications with voltage level V ⁇ 1600V.
  • Main feature of current IGBTs is high level of conductivity, as long as thermal stability is provided through a proper dissipation system; electrical operating stability and thermal stability are strictly connected and, when instability happens, it involves both aspects, preventing transistor from correct operation.
  • the other kind of transistor, MOSFET is used as power electronics transistor in applications requiring higher operating voltage level, i.e.
  • IGBT Interconnective Biharmonic Device
  • Typical IGBT internal structure is composed of superimposed layers of semiconductor, mainly extrinsic silicon, from bottom layer to top layer consisting in: collector region, substrate made of a single and homogeneous material (n-type doped silicon with medium doping level, for example), emitter and buried insulated gate.
  • Hybrid IGMT structure differs from typical trench IGBT structure because of a characterising peculiar substrate, here called “composite conduction substrate”, which is comprised with collector layer and gate-emitter layer and is composed of multiple vertical channels, which might be electrically high conductive or electrically insulated.
  • composite conduction substrate which is comprised with collector layer and gate-emitter layer and is composed of multiple vertical channels, which might be electrically high conductive or electrically insulated.
  • Each vertical channel depending from its electrical conductivity property, is here called “conduction channel” or “lateral channel”: “conduction channel” is referred to vertical channel characterized with high electrical conductivity, “lateral channel” refers to an electrically insulated, or very-low conductive, vertical channel which sides the conduction channel.
  • Hybrid IGMT is physically structured through superposition of multiple layers [1], which are here described; FIG. n.l may be used as description support and verification, Table 1 might be referred as guide for interpretation of FIG n.l.
  • Hybrid IGMT structure from top layer to bottom layer is so composed:
  • Composite conduction substrate which is a substrate composed of vertical channels, placed under the p type region; inside the “composite conduction substrate” at least one high-electrical- conductive "conduction channel” shall be implemented, characterising transistor electrical conductivity; “conduction channels”, or channel if only one is implemented, are sided with electrically insulated (or very-low conductive) vertical “later channels”, as above described, whose first objective is conduction region delimitation. Additional functionalities, for which "lateral channels” are arranged, are device bandwidth characterisation (that is filtering and dynamic determination), internal temperature monitoring, fault monitoring.
  • FIG. n.l Hybrid IGMT implementation is represented with one “conduction channel” and “two lateral channels”, as better explained in following "BRIEF DESCRIPTION OF DRAWINGS” section;
  • N+ type region for emitter contact is implemented with following features: n+ type region transversal section shall be aligned with transversal section of "composite conduction substrate"; maximum transversal area of n+ type region shall cover totally or almost totally conduction channel transversal area and only partially “lateral channel” transversal area. As graphical reference, attached FIG. n.l might be referred. Transversal area of n+ type region may cover a part of "left lateral channel” or “right lateral channel” transversal area; “left lateral channel” is the “lateral channel” placed below the insulated gate and above the collector region and might be seen on the left of "conduction channel” in FIG. n.
  • Hybrid IGMT For the sake of identification of a transistor as Hybrid IGMT, opposite doping concentration than scheme in [1] may be also considered, if it might ever be necessary to implement it. Therefore, following structure from top to bottom layer might be also considered as a possible implementation of Hybrid IGMT: p+ type region for emitter contact, n type region, "composite conduction substrate", n+ region for collector contact. In following description, however, Hybrid IGMT structure reference is as described in [1].
  • Hybrid IGMT in comparison with current IGBTs is the presence of electrically insulated "lateral channels" inside the "composite conduction substrate", as previously described, through which a dramatic reduction of gate-collector energy losses in switching phase, an increase in electric current density inside emitter transversal section and more directivity applied to electric charge movement between collector and emitter might be achieved; gate-collector losses may be considered as absent. This property is especially achieved through the insulated "lateral channel” placed under gate contact and above collector contact.
  • "lateral channels” may be implemented with high- insulating dielectric materials selected to gain fast switching dynamic. For this purpose, intrinsic silicon may be adopted, as explained in following "BEST MODE FOR CARRYING OUT THE INVENTION" section.
  • Conduction channels inside “composite conduction substrate” shall be implemented using materials characterized with high electrical conductivity, so that the main advantages of their presence are the determination of high-speed electrical conduction path between emitter and collector, as well as low conduction power losses.
  • “conduction channels” might be implemented through a vertical structure consisting of extrinsic silicon and carbon connected in electrical parallel; this composite structure is here called “Si // C”, whose main advantages consist in:
  • FIG. n.l shows a sample CAD Hybrid IGMT design solution and takes account of legend in Table 1.
  • FIG. n.l implies that p-type region under gate contact is filled with high doping concentration, so as to build depletion region with sufficient thickness for conduction blocking between collector and emitter; charge movement due to gate-emitter electric field relies mainly on surface layers.
  • depletion region thickness should be proportional to maximum voltage applied between collector and gate, taking account of real application in which transistor is implemented.
  • structure as per FIG.2 might be considered, where A.10 and A.ll represent a whole depletion region between gate and collector.
  • A.12 represents substrate, part of p-type region, where doping concentration is high, as to let current flow through "conduction channel” and "left lateral channel” towards emitter; in this case, "lateral channel” is used for additional functionalities, as above described.
  • Hybrid IGMT hybrid induction substrate
  • lateral channels which are vertical channels siding “conduction channels” and whose transversal section is almost completely external to emitter region, shall result electrically insulated. Consequently, channels composing the "composite conduction substrate” shall be implemented using different materials.
  • the choice of materials, combined with peculiar structure of Hybrid IGMT “composite conduction substrate”, should aim to significant operating stability in a wide thermal range, as well as to a dramatic reduction in power dissipation developed during operation. In this way, it is easier to guarantee thermal and electrical stability, avoidance of thermal and electrical runaway and increase in product operating life.
  • Hybrid IGMT structure is implemented using intrinsic silicon Si, or very-low doped Si, in “lateral channels” and a “Si//C” composite structure, consisting of carbon and highly-doped n-type extrinsic silicon connected in electrical parallel, in “conduction channels”.
  • This peculiar implementation of Hybrid IGMT is identified with acronym "Hybrid IGMT Si // C”.
  • junction between p+ type Si and conduction channel silicon at junction is expected to be highly doped, as a function of maximum reverse voltage which is intended to be applied to device; therefore, the imposition of high doping concentration leads to chip realisation for IGMT also when high voltages are required;
  • “Lateral channels” shall be made of intrinsic silicon Si, or Si with extremely low n-type doping, as previous description; attached FIG. n.l might be used as graphical reference. In this way, a significant depletion region in Junction Si n - Si p is expected at gate side, resulting in conduction losses reduction between collector and gate; • "Conduction channels” placed under emitter contact and above collector contact shall be implemented with materials for high-speed electrical conduction; here the peculiar composite structure of "Si // C", intended as electrical parallel of carbon and highly-doped extrinsic silicon, is described as "conduction channel” implementation method.
  • Hybrid IGMT "Si // C” electrical characteristic equation is here mathematically explained, taking account of following Equation 1, Equation 2 and Equation 3, where psi // c resistivity of "Si // C" conduction channel is a function of transistor operating temperature T:
  • Equation l lf T ⁇ Ti, PsiiO, where:
  • ° psi(T) is the upper limit of psi//c(T) and psi(T) « pc(T),
  • resistivity value psi // c of conduction channel made of "Si // C" is extremely low and results in approximatively constant value for T > Ti.
  • Si // C behaviour is defined through two threshold temperature values Ti and Tr, these values are a function of silicon doping level N D and are calculated during transistor design phase.
  • Si // C composite structure consisting of electrical parallel of carbon and extrinsic silicon, as above explained, defines following Hybrid IGMT properties:
  • Hybrid IGMT Si // C consists in efficient exploiting of carrier movement, both at high and low temperatures.
  • conduction is mainly demanded to highly-doped extrinsic silicon (semiconductor)
  • carbon becomes the primary conduction mean; in this way, semiconductor carrier mobility reduction due to thermal effect movements is avoided, so conductivity value may be considered constant over a wide temperature range.
  • Hybrid IGMT may be designed and produced as single transistor, as in FIG.n.l or in FIG.n.2, so as to design on futher steps inverter or converter units; otherwise, it may be produced as a device gathering three units together, a unique collector contact with three gate inputs and three emitter outputs.
  • Hybrid IGMT use is intended for implementation in converters and inverters for electric motor drive, especially for applications requiring fast dynamic, stability for wide temperature range and low power losses. Therefore, Hybrid IGMT industrial application includes vehicle traction systems and electric energy conversion systems, where electric machines are used as motors and/or generators.

Abstract

This document defines the characteristics of Hybrid Insulated Gate Multi-structure and multi-material Transistor, that is to say "Hybrid IGMT", as power electronics transistor. This transistor is characterized with a structure of internal conduction substrate composed of vertical channels, distinguishing between channels with high electrical conductivity and insulated channels. This peculiarity distinguishes Hybrid IGMT from any other power electronics transistor and brings many advantages, most of all the significant reduction, till absence, of switching losses. Within description a specific implementation of conductive channels is introduced, consisting in a composite structure called "Si // C", which allows the fulfillment of constant and very low conduction power losses in a wide operating electrical and thermal range. Hybrid IGMT is intended for application in vehicle electric traction, also in low-voltage or medium- voltage electric systems requiring DC-AC or AC-DC conversion with high stability, long operating life and low power losses.

Description

TITLE OF THE INVENTION
"Hybrid Insulated Gate Multi-structure and multi-material Transistor"
DESCRIPTION
TECHNICAL FIELD
This document is primarily intended to define description and implementation features, that are physical, electrical and structural characteristics of a novel power electronics transistor, identified with the name of Hybrid Insulated Gate Multi-structure and multi-material Transistor (that is to say "Hybrid IGMT"), subsequently to introduce one of its possible implementations using a composite structure characterized with electrical parallel of highly-doped extrinsic silicon and carbon, the structure is here called "Si // C" and better explained hereafter. Hybrid IGMT use is tailored for implementation of converters and inverters for drive and control of electric machines, it is especially thought for applications requiring fast dynamic, stability for wide temperature range, low power conduction losses and low switching losses. Therefore, Hybrid IGMT is intended mainly as power electronics transistor to be applied in electric and hybrid vehicle traction systems and may be used also in low-voltage or medium-voltage energy conversion applications.
BACKGROUND ART
Most-used and market-available product categories in the field of power electronics for electric motor drive consist in IGBT and MOSFET. IGBT is currently applied in many fields, such as in industry machinery, in electric vehicles and for energy conversion purposes; its implementation is tailored for each peculiar application through proper dimension evaluation and characterisation of extrinsic silicon, generally for applications with voltage level V < 1600V. Main feature of current IGBTs is high level of conductivity, as long as thermal stability is provided through a proper dissipation system; electrical operating stability and thermal stability are strictly connected and, when instability happens, it involves both aspects, preventing transistor from correct operation. The other kind of transistor, MOSFET, is used as power electronics transistor in applications requiring higher operating voltage level, i.e. 3kV; if MOSFET conductivity is generally lower than in IGBT, on the other hand the MOSFET shows greater stability towards thermal variations, voltage variations and conduction time, that is switching frequency, variations. Power MOSFET, for technical field as above, is currently produced using Si or SiC. As to understand Hybrid IGMT peculiarity, Trench IGBT internal structure should be considered in comparison. Typical IGBT internal structure is composed of superimposed layers of semiconductor, mainly extrinsic silicon, from bottom layer to top layer consisting in: collector region, substrate made of a single and homogeneous material (n-type doped silicon with medium doping level, for example), emitter and buried insulated gate.
DISCLOSURE OF INVENTION
Hybrid IGMT structure differs from typical trench IGBT structure because of a characterising peculiar substrate, here called "composite conduction substrate", which is comprised with collector layer and gate-emitter layer and is composed of multiple vertical channels, which might be electrically high conductive or electrically insulated. Each vertical channel, depending from its electrical conductivity property, is here called "conduction channel" or "lateral channel": "conduction channel" is referred to vertical channel characterized with high electrical conductivity, "lateral channel" refers to an electrically insulated, or very-low conductive, vertical channel which sides the conduction channel.
Specifically, Hybrid IGMT is physically structured through superposition of multiple layers [1], which are here described; FIG. n.l may be used as description support and verification, Table 1 might be referred as guide for interpretation of FIG n.l. Hybrid IGMT structure from top layer to bottom layer is so composed:
• Insulated gate and emitter contacts, which are placed in the same plane
• n+ type region for emitter contact
• p type region, surrounding emitter n+ type region and eventually including the buried part of the insulated gate
• "Composite conduction substrate", which is a substrate composed of vertical channels, placed under the p type region; inside the "composite conduction substrate" at least one high-electrical- conductive "conduction channel" shall be implemented, characterising transistor electrical conductivity; "conduction channels", or channel if only one is implemented, are sided with electrically insulated (or very-low conductive) vertical "later channels", as above described, whose first objective is conduction region delimitation. Additional functionalities, for which "lateral channels" are arranged, are device bandwidth characterisation (that is filtering and dynamic determination), internal temperature monitoring, fault monitoring. In FIG. n.l Hybrid IGMT implementation is represented with one "conduction channel" and "two lateral channels", as better explained in following "BRIEF DESCRIPTION OF DRAWINGS" section;
• p+ type characterisation for collector contact;
• Collector contact.
N+ type region for emitter contact is implemented with following features: n+ type region transversal section shall be aligned with transversal section of "composite conduction substrate"; maximum transversal area of n+ type region shall cover totally or almost totally conduction channel transversal area and only partially "lateral channel" transversal area. As graphical reference, attached FIG. n.l might be referred. Transversal area of n+ type region may cover a part of "left lateral channel" or "right lateral channel" transversal area; "left lateral channel" is the "lateral channel" placed below the insulated gate and above the collector region and might be seen on the left of "conduction channel" in FIG. n. 1; "right lateral channel" is the "lateral channel" placed on the right of the "conduction channel" instead, as confirmed by FIG. n. 1. Portion of transversal area of "lateral channel" to be covered shall be calculated taking account of desired additional functionalities for "lateral channel", functionalities as reported above.
For the sake of identification of a transistor as Hybrid IGMT, opposite doping concentration than scheme in [1] may be also considered, if it might ever be necessary to implement it. Therefore, following structure from top to bottom layer might be also considered as a possible implementation of Hybrid IGMT: p+ type region for emitter contact, n type region, "composite conduction substrate", n+ region for collector contact. In following description, however, Hybrid IGMT structure reference is as described in [1].
The main advantage of Hybrid IGMT in comparison with current IGBTs is the presence of electrically insulated "lateral channels" inside the "composite conduction substrate", as previously described, through which a dramatic reduction of gate-collector energy losses in switching phase, an increase in electric current density inside emitter transversal section and more directivity applied to electric charge movement between collector and emitter might be achieved; gate-collector losses may be considered as absent. This property is especially achieved through the insulated "lateral channel" placed under gate contact and above collector contact. Moreover, "lateral channels" may be implemented with high- insulating dielectric materials selected to gain fast switching dynamic. For this purpose, intrinsic silicon may be adopted, as explained in following "BEST MODE FOR CARRYING OUT THE INVENTION" section.
"Conduction channels" inside "composite conduction substrate" shall be implemented using materials characterized with high electrical conductivity, so that the main advantages of their presence are the determination of high-speed electrical conduction path between emitter and collector, as well as low conduction power losses. For this purpose, "conduction channels" might be implemented through a vertical structure consisting of extrinsic silicon and carbon connected in electrical parallel; this composite structure is here called "Si // C", whose main advantages consist in:
1. Electrical auto-stability: Constant and low conduction power losses in the whole range of device operating temperature;
2. Thermal auto-stability.
"Si // C" is described in the following "BEST MODE FOR CARRYING OUT THE INVENTION" section. "Si //C" electrical behaviour is specified in Equation 1, Equation 2 and Equation 3. BRIEF DESCRIPTION OF DRAWINGS
Attached FIG. n.l shows a sample CAD Hybrid IGMT design solution and takes account of legend in Table 1.
Figure imgf000006_0001
Table 1
FIG. n.l implies that p-type region under gate contact is filled with high doping concentration, so as to build depletion region with sufficient thickness for conduction blocking between collector and emitter; charge movement due to gate-emitter electric field relies mainly on surface layers.
However, available depletion region thickness should be proportional to maximum voltage applied between collector and gate, taking account of real application in which transistor is implemented. So as to provide Hybrid IGMT with proper isolation between collector and emitter when high voltage is applied, structure as per FIG.2 might be considered, where A.10 and A.ll represent a whole depletion region between gate and collector. A.12 represents substrate, part of p-type region, where doping concentration is high, as to let current flow through "conduction channel" and "left lateral channel" towards emitter; in this case, "lateral channel" is used for additional functionalities, as above described.
BEST MODE FOR CARRYING OUT THE INVENTION
As explained in the "DISCLOSURE OF INVENTION" section, vertical channels composing Hybrid IGMT "composite conduction substrate" shall have different electrical properties, as a function of their positioning. "Conduction channels" placed under emitter contact and above collector region shall be electrically highly conductive; vice versa, "lateral channels", which are vertical channels siding "conduction channels" and whose transversal section is almost completely external to emitter region, shall result electrically insulated. Consequently, channels composing the "composite conduction substrate" shall be implemented using different materials. The choice of materials, combined with peculiar structure of Hybrid IGMT "composite conduction substrate", should aim to significant operating stability in a wide thermal range, as well as to a dramatic reduction in power dissipation developed during operation. In this way, it is easier to guarantee thermal and electrical stability, avoidance of thermal and electrical runaway and increase in product operating life.
Therefore, as primary but not exclusive choice, Hybrid IGMT structure is implemented using intrinsic silicon Si, or very-low doped Si, in "lateral channels" and a "Si//C" composite structure, consisting of carbon and highly-doped n-type extrinsic silicon connected in electrical parallel, in "conduction channels". This peculiar implementation of Hybrid IGMT is identified with acronym "Hybrid IGMT Si // C".
Detailed explanation of Hybrid IGMT structure is reported here below:
• Junction between p+ type Si and conduction channel: silicon at junction is expected to be highly doped, as a function of maximum reverse voltage which is intended to be applied to device; therefore, the imposition of high doping concentration leads to chip realisation for IGMT also when high voltages are required;
• "Lateral channels" shall be made of intrinsic silicon Si, or Si with extremely low n-type doping, as previous description; attached FIG. n.l might be used as graphical reference. In this way, a significant depletion region in Junction Si n - Si p is expected at gate side, resulting in conduction losses reduction between collector and gate; • "Conduction channels" placed under emitter contact and above collector contact shall be implemented with materials for high-speed electrical conduction; here the peculiar composite structure of "Si // C", intended as electrical parallel of carbon and highly-doped extrinsic silicon, is described as "conduction channel" implementation method. Hybrid IGMT "Si // C" electrical characteristic equation is here mathematically explained, taking account of following Equation 1, Equation 2 and Equation 3, where psi // c resistivity of "Si // C" conduction channel is a function of transistor operating temperature T:
Equation l: lf T < Ti, PsiiO, where:
Figure imgf000008_0001
o psi(T) = 1 / osi(T), ° osi(T) = q*ND * μΝ,
° osi(T2) = osi(Ti) * Tim/T2 m,
° psi(T) is the upper limit of psi//c(T) and psi(T) « pc(T),
• Equation 2: If Ti < T < T2, psi//c(T) = « £ l « ψ, meaning in this way that resistivity, as well as conductivity, of extrinsic silicon and resistivity, as well as conductivity, of carbon have the same value in the specified thermal range,
Equation 3: If T > T2, psl//c(T = psi(^pc (^ → Pc( ) , pc(T) is the upper limit
" Psi(.U+Pc (.U
of psi//c(T), pc(T) « psi(T), where:
• Psi -c(T) = "Si // C" electrical resistivity as a function of transistor operating temperature T
• psi(T) = Silicon electrical resistivity as a function of transistor operating temperature T
• pc(T) = Carbon electrical resistivity as a function of transistor operating temperature T
• cFsi(T) = Silicon electrical conductivity as a function of transistor operating temperature T
• q = Electron charge of nominal value equal to 1.60 · 10 19 C
• ND = Concentration of doping in silicon
• μΝ = Electron mobility of nominal value equal to 1500 cm2/(V-s) at T = 300 K
• m = Parameter of nominal value equal to 1,5.
Therefore, resistivity value psi // c of conduction channel made of "Si // C" is extremely low and results in approximatively constant value for T > Ti.
"Si // C" behaviour is defined through two threshold temperature values Ti and Tr, these values are a function of silicon doping level ND and are calculated during transistor design phase.
"Si // C" composite structure consisting of electrical parallel of carbon and extrinsic silicon, as above explained, defines following Hybrid IGMT properties:
• Carbon resistivity, as well as conductivity, characteristics:
° Stable value of resistivity as a function of operating temperature
° Material applicability in a wide temperature range
° Less possible value of resistivity currently measured among conductors
° Crystalline structure, which is suitable for implementation in chips, also with composite structure peculiar of Hybrid IGMT
• Extrinsic silicon conductivity characteristic:
° Highly doped silicon guarantees for high conductivity value, but it would be available only at lower temperatures and in a restricted operating range, if only silicon were present.
Main peculiarity of "Hybrid IGMT Si // C" consists in efficient exploiting of carrier movement, both at high and low temperatures. At low temperatures conduction is mainly demanded to highly-doped extrinsic silicon (semiconductor), at high temperatures carbon becomes the primary conduction mean; in this way, semiconductor carrier mobility reduction due to thermal effect movements is avoided, so conductivity value may be considered constant over a wide temperature range.
Requested doping level ND, calculated as per above formula, allows "Hybrid IGMT Si // C" to be produced in smaller dimensions in comparison with current IGBTs.
To sum up, relevant properties deriving from "Si // C" implementation consist in:
• High-speed carrier conduction and no impact on channel resistance;
• Constant cut-off current value as a function of temperature;
• Electrical stability with constant and reduced conduction power losses; • Thermal auto-stability properties in a wide thermal range;
• Decrease in probability of overtemperature faults; other kind of faults are easily detectable and may be prevented;
• As far as signal behaviour between collector and emitter is concerned, simultaneous presence of intrinsic Si "lateral channels" and "Si // C" "conduction channel" provides for additional functionalities consisting in bandwidth filtering, external and internal fault monitoring, device internal temperature monitoring, without compromising the peculiarity of high-speed conduction channel.
Hybrid IGMT may be designed and produced as single transistor, as in FIG.n.l or in FIG.n.2, so as to design on futher steps inverter or converter units; otherwise, it may be produced as a device gathering three units together, a unique collector contact with three gate inputs and three emitter outputs.
INDUSTRIAL APPLICABILITY
Hybrid IGMT use is intended for implementation in converters and inverters for electric motor drive, especially for applications requiring fast dynamic, stability for wide temperature range and low power losses. Therefore, Hybrid IGMT industrial application includes vehicle traction systems and electric energy conversion systems, where electric machines are used as motors and/or generators.

Claims

1. Claim n.l: Hybrid Insulated Gate Multi-structure and multi-material Transistor (called "Hybrid IGMT") is a power electronic transistor with three electric contacts, exactly gate, emitter and collector, referring to vocabulary for power electronics transistors, such as Trench IGBTs, where gate contact is electrically insulated (prior art portion).
Hybrid Insulated Gate Multi-structure and multi-material Transistor internal structure consists in following superimposed regions, which are in electric contact one another and which are here described from top layer to bottom layer of the transistor:
• Electrical contacts of insulated gate and emitter on the same plane
• N+ doped semiconductor region under emitter contact
• P doped semiconductor region in electrical contact with gate, which may include also a buried part of insulated gate
• "Composite conduction substrate"
• P+ doped semiconductor region for collector contact
• Collector electrical contact
And it is characterized in that:
• The "composite conduction substrate", which is the region placed under gate and emitter contacts plane and above collector contact and which lets emitter and collector be in electrical contact, is completely included under p-type doped region in contact with insulated gate and above p+-type doped region for collector contact and is implemented with a structure of vertical channels, which may be classified as electrical conductive channels with high value of conductivity, called "conduction channels", and electrically insulated or very-low conductive channels, called "lateral channels";
• Vertical channels composing the "composite conduction substrate", as reported in previous sentences, are so characterized:
■ There is only one electrically insulated or very-low conductive channel placed under the gate contact and above the collector contact and this channel is called "left lateral channel" (only for quicker understanding, reference sign A.7 in FIG. n.l may be watched);
■ There are one or many electrically high-conductive vertical channels placed under the emitter region and above the collector contact, called "conduction channels" (only for quicker understanding, reference sign A.6 in FIG. n.l may be watched).
2. Claim n.2: Hybrid Insulated Gate Multi-structure and multi-material Transistor, as claimed in Claim n.l, is characterized with a substrate called "composite conduction substrate" made of vertical channels placed under the emitter region and above the collector region, called "conduction channels", which might be implemented using materials with high electrical conductivity and whose structure has been already explained in previous Claim n.l. In the best implementation of Hybrid Insulated Gate Multi-structure and multi-material Transistor, intended as reference but not exclusive implementation, "conduction channels" are implemented through "Si // C", where "Si // C" identifies a vertical structure consisting of n- type highly-doped extrinsic silicon and carbon connected in electrical parallel. Electrical conductivity of "Si // C" composite structure is a function of transistor operating temperature T and it is described through following formula (Equationl,Equation 2,Equation3): → where:
Figure imgf000012_0001
• aSi(T) = q*ND * μΝ,
• aSi(T2) = Osi(Ti) * T!m/T2 m,
• psi(T) is the upper limit of pSi//c(T) and pSi(T) « pc(T),
• Equation 2: If Ti < T < T2, psi//c(T) = « « ψ, meaning in this way that resistivity, as well as conductivity, of extrinsic silicon and resistivity, as well as conductivity, of carbon have the same value in the specified thermal range,
Equation 3: If T > T2, psl//c(T = psi(^pc (^ → Pc( ) , pc(T) is the upper limit
" Psi(.U+Pc(.U
of psi//c(T), pc(T) « psi(T), where:
• Psi // c(T) = "Si // C" electrical resistivity as a function of transistor operating temperature T
• psi(T) = Silicon electrical resistivity as a function of transistor operating temperature T
• pc(T) = Carbon electrical resistivity as a function of transistor operating temperature T • osi(T) = Silicon electrical conductivity as a function of transistor operating temperature T
• q = Electron charge of nominal value equal to 1.60 · 10 19 C
• ND = Concentration of doping in silicon
• μΝ = Electron mobility of nominal value equal to 1500 cm2/(V-s) at T = 300 K
• m = Parameter of nominal value equal to 1,5
• Ti and T2 = threshold temperature values, which are a function of ND and for which shall result Ti < Ϊ2.
Resistivity formula, as reported above, expresses and is implemented through electrical parallel of highly-doped extrinsic silicon and carbon.
Hybrid Insulated Gate Multi-structure and multi-material Transistor which implements conduction channels as per above formula is called "Hybrid IGMT Si // C".
PCT/IT2018/050203 2017-10-23 2018-10-21 Hybrid insulated gate multi-structure and multi-material transistor WO2019082220A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396085A (en) * 1993-12-28 1995-03-07 North Carolina State University Silicon carbide switching device with rectifying-gate
WO2001045146A1 (en) * 1999-12-16 2001-06-21 Koninklijke Philips Electronics N.V. Superior silicon carbide integrated circuits and method of fabricating
US20140042593A1 (en) * 2012-08-10 2014-02-13 Infineon Technologies Austria Ag Semiconductor device including a trench in a semiconductor substrate and method of manufacturing a semiconductor device
US20140264582A1 (en) * 2013-03-13 2014-09-18 Icemos Technology Ltd. 800 v superjunction device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5396085A (en) * 1993-12-28 1995-03-07 North Carolina State University Silicon carbide switching device with rectifying-gate
WO2001045146A1 (en) * 1999-12-16 2001-06-21 Koninklijke Philips Electronics N.V. Superior silicon carbide integrated circuits and method of fabricating
US20140042593A1 (en) * 2012-08-10 2014-02-13 Infineon Technologies Austria Ag Semiconductor device including a trench in a semiconductor substrate and method of manufacturing a semiconductor device
US20140264582A1 (en) * 2013-03-13 2014-09-18 Icemos Technology Ltd. 800 v superjunction device

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