GB2557485A - Color filter array substrate and liquid crystal display panel - Google Patents
Color filter array substrate and liquid crystal display panel Download PDFInfo
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- GB2557485A GB2557485A GB1802130.3A GB201802130A GB2557485A GB 2557485 A GB2557485 A GB 2557485A GB 201802130 A GB201802130 A GB 201802130A GB 2557485 A GB2557485 A GB 2557485A
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- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 12
- 239000002184 metal Substances 0.000 claims abstract description 114
- 229910052751 metal Inorganic materials 0.000 claims abstract description 114
- 238000002161 passivation Methods 0.000 claims abstract description 44
- 239000011521 glass Substances 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims description 24
- 230000005669 field effect Effects 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000004642 Polyimide Substances 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 6
- 238000000034 method Methods 0.000 description 4
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000003086 colorant Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B5/00—Optical elements other than lenses
- G02B5/20—Filters
- G02B5/201—Filters in the form of arrays
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136222—Colour filters incorporated in the active matrix substrate
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Optics & Photonics (AREA)
- Mathematical Physics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Optical Filters (AREA)
Abstract
A color filter array substrate comprises a glass substrate (101), a first metal layer (102), an insulation layer (103), an active layer (104), an ohmic contact layer (105), a second metal layer (106), a first passivation layer (107), a color filter layer (108), a second passivation layer (109), and a pixel electrode layer (110). A channel (111) is formed in the color resistance overlapping position of the color filter layer (108), a common electrode wire (112) is disposed on the first metal layer (102) corresponding to the channel (111), and a metal wire (113) is disposed on the second metal layer (106) corresponding to the channel (111). The array substrate can effectively shield light from leaking, and can also increase circulation of PI and liquid crystals.
Description
(56) Documents Cited:
CN 104808411 A CN 104656330 A CN 102269834 A US 20040233352 A1
CN 104698713 A CN 104597656 A US 20070296894 A1 (86) International Application Data:
PCT/CN2015/087619 Zh 20.08.2015 (58) Field of Search:
INT CL G02F
Other: CNPAT, EPODOC, WPI, CNKI (87) International Publication Data:
WO2017/028298 Zh 23.02.2017 (71) Applicant(s):
Shenzhen China Star Optoelectronics Technology Co., Ltd.
No.9-2, Tangming Road, Guangming New District, Shenzhen City 518132, Guangdong, China (72) Inventor(s):
Yanxi Ye (74) Agent and/or Address for Service:
Urquhart-Dykes & Lord LLP
Arena Point, Merrion Way, LEEDS, LS2 8PA,
United Kingdom (54) Title of the Invention: Color filter array substrate and liquid crystal display panel Abstract Title: Color filter array substrate and liquid crystal display panel (57) A color filter array substrate comprises a glass substrate (101), a first metal layer (102), an insulation layer (103), an active layer (104), an ohmic contact layer (105), a second metal layer (106), a first passivation layer (107), a color filter layer (108), a second passivation layer (109), and a pixel electrode layer (110). A channel (111) is formed in the color resistance overlapping position of the color filter layer (108), a common electrode wire (112) is disposed on the first metal layer (102) corresponding to the channel (111), and a metal wire (113) is disposed on the second metal layer (106) corresponding to the channel (111). The array substrate can effectively shield light from leaking, and can also increase circulation of PI and liquid crystals.
no
109 108 /
/ 103 102 101
104
Μ i
1/2
2/2
FIG. 2
Color Filter Array Substrate and Liquid Crystal Display Panel
BACKGROUND OF THE INVENTION Field of the Invention [0001] The present invention relates to a field of display technology, and more particularly to a color filter array substrate and a liquid crystal display (LCD) panel.
Description of Prior Art [0002] Black column space (BCS) or BM (Black Matrix)-less technology applied to LCD panels can reduce a process using BM, and thus cost can be saved. In the BCS technique, black materials are used in periphery to have an effect of being directly substituted for the BM to function for light shielding. Besides, another effect is to support a thickness of a ceil of an LCD panel when the black materials are used in an AA (active area). The light shielding for a scanning line and a data line in the AA relies on mutuality of color resist stacking and metals to carry it out. The stacking of color resists generally employs a red color resist and a blue color resist to be overlapped since the spectrums of these two colors are not overlapped. In this manner, the optical effect would be better, [0003] Current display products applying BCS/BM-less technology on the market use IPS (In-Plane Switching) technology. A layer of planarization layer (PFA) Is used in the iPS technology to flatten out a projection generated by overlapping of color resists. However, costs will increase for display products applying BCS/BM-less technology in HVA (high transmittance vertical alignment) mode if the planarization layer is used. Consequently, the planarization layer is not employed in HVA technology. The problem, in which projections around sides are generated due to overlapping of color resists when the HVA-mode display products apply BCS/BM-less technology, is raised, so that a phenomenon is generated about irregular Polyimide (PI) and liquid crystal flow during the processes of PI coating and liquid crystal filling due to the retaining projections around sides and thereby display performance is affected.
[0004] Therefore, it is necessary to propose a new technical solution to solve the foregoing technical problems.
SUMMARY OF THE INVENTION [0005] It is an object of the present invention to provide a color filter array substrate and an LCD panel for the purpose of solving a problem existing in the conventional HVA-mode display products applying BCS/BM-less technology, wherein projections around sides are generated due to overlapping of color resists so that a phenomenon of irregular Pi and liquid crystal flow is caused during the processes of PS coating and liquid crystal filling and thereby display performance is affected.
[0006] To solve the above problems, technical solutions of the present invention are as follows;
[0007] According to an embodiment of the present invention, a color filter array substrate comprises a glass substrate; a first metal layer disposed on the glass substrate, the first metal layer comprising a scanning line and a gate of a thin-film fieldeffect transistor (FET); an insulating layer disposed on the first metal layer; an active layer disposed on the insulating layer; an ohmic contact layer disposed on both ends of the active layer; a second metal layer disposed on the ohmic contact layer, the second metal layer comprising a data line, the source and the drain of the thin-film FET; a first passivation layer disposed on the second metal layer for isolating the second metal layer and a color filter layer; the color filter layer disposed on the first passivation layer, the color filter layer including, sequentially arranged, a first color resist, a second color resist, and a third color resist; a second passivation layer disposed on the color filter layer for isolating the color filter layer and a pixel electrode layer; and a pixel electrode layer disposed on the second passivation layer; wherein channels are formed at locations where color resists overlap in the color filter layer, a common electrode Sine is disposed on the first metal layer corresponding to the channels in a Y-axis direction, and a metal line is disposed on the second metal layer corresponding to the channels in a X-axis direction.
[0008] Preferably, in the above color filter array substrate, the metal line is an extended portion of the drain.
[00091 Preferably, in the above color filter array substrate, the channels are respectively formed at the locations where the color resists overlap in the Y-axis direction.
[0010] Preferably, in the above color filter array substrate, the channels are respectively formed at the locations where the color resists overlap in the X-axis direction.
[0011] According to another embodiment of the present invention, a color filter array substrate comprises a glass substrate; a first metal layer disposed on the glass substrate, the first metal layer comprising a scanning line and a gate of a thin-film FET; an insulating layer disposed on the first metal layer; an active layer disposed on the insulating layer; an ohmic contact layer disposed on both ends of the active layer; a second metal layer disposed on the ohmic contact layer, the second metal layer comprising a data line, the source and the drain of the thin-film FET; a first passivation layer disposed on the second metal layer for isolating the second metal layer and a color filter layer; the color filter layer disposed on the first passivation layer, the color filter layer including, sequentially arranged, a first color resist, a second color resist, and a third color resist; a second passivation layer disposed on the color filter layer for isolating the color filter layer and a pixel electrode layer; and a pixel electrode layer disposed on the second passivation layer; wherein channels are formed at locations where the color resists overlap in the color filter layer, a common electrode line is disposed on the first metal layer corresponding to the channels for achieving lightshielding, and the locations where the color resists overlap are regions where adjacent color resists overlap.
[0012] in the above color filter array substrate, the channels are respectively formed at the locations where the color resists overlap in the Y-axis direction.
10013] Preferably, in the above color filter array substrate, the channels are further respectively formed at the locations where the color resists overlap in the X-axis direction, and a metal Sine is disposed on the second metal layer corresponding to the channels for achieving light-shielding.
[0014] Preferably, in the above color filter array substrate, the metal Sine is an extended portion of the drain.
[0015] Preferably, in the above color filter array substrate, the locations where the color resists overlap are locations where a red color resist and a blue color resist overlap, locations where a red color resist and a green color resist overlap, or locations where a blue color resist and a green color resist overlap.
[0016] According to yet another embodiment of the present invention, a color filter array substrate comprises a color filter array substrate includes a glass substrate; a first metal layer disposed on the glass substrate, the first metal layer comprising a scanning Sine and a gate of a thin-film FET; an insulating layer disposed on the first metal layer; an active layer disposed on the insulating layer; an ohmic contact layer disposed on both ends of the active layer; a second metal layer disposed on the ohmic contact layer, the second metal layer comprising a data line, the source and the drain of the thin-film FET; a first passivation layer disposed on the second metal layer for isolating the second metal layer and a color filter layer; the color filter layer disposed on the first passivation layer, the color filter layer including, sequentially arranged, a first color resist, a second color resist, and a third color resist; a second passivation layer disposed on the color filter layer for isolating the color filter layer and a pixel electrode layer; and a pixel electrode layer disposed on the second passivation layer; wherein channels are formed at locations where the color resists overlap in the color filter layer, a metal line is disposed on the second metal layer corresponding to the channels for achieving light-shielding, and the locations where the color resists overlay are regions where adjacent color resists overlap.
[0017] Preferably, in the above color filter array substrate, the metal line is an extended portion of the drain.
[0018] Preferably, in the above color filter array substrate, the channels are respectively formed at the locations where the color resists overlay in the X-axis direction.
[0019] Preferably, in the above color filter array substrate, the width of the metal is greater than or equal to the width of the channels.
[0020] Preferably, in the above color filter array substrate, the locations where the color resists overlap are locations where a red color resist and a blue color resist overlap, locations where a red color resist and a green color resist overlap, or locations where a blue color resist and a green color resist overlap.
[0021] According to yet another embodiment of the present invention, a liquid crystal display panel is provided comprising the above color filter array substrate.
[0022] Compared with the prior art, the present invention changes a stacking structure of color resists to enhance liquidity of the Pi and LCD on the basis of without increase of a planarization layer for not increasing costs. That is, channels are formed at locations which color resists overlap in a color filter layer, at this time, and light shielding does not function because there is only one layer of the color resists existing at the channels. In this case, there is a risk of light leakage, so the present invention provides a common electrode line on a first metal layer corresponding to the channels in a Y-axis direction and a metal line on a second metal layer corresponding to the channels in an X-axis direction to prevent the light leakage. The embodiments of the present invention can not only effectively shield the Sight leakage, but also increase liquidity of the PS and LCD.
[00231 To allow the foregoing summary of the present invention to be more clearly understood, there are preferred embodiments, which proceed with reference to the accompanying drawings, and are described in detail as follows.
BRIEF DESCRIPTION [0024] FIG. 1 illustrates a schematic diagram of a structure of a color filter array substrate according to an embodiment of the present invention.
[0025] FIG. 2 illustrates a schematic view of shielding the channels by adoption of a common electrode line according to an embodiment of the present invention.
[0026] FIG. 3 illustrates a schematic view of shielding the channels by adoption of an additional metal Sine at the drain of the FET according to another embodiment of the present invention,
DETAILED DESCRIPTION [0027] The terms as used in this specification, “an embodiment” means that the description in connection with the embodiment serves as an example, instance, or illustration of the disclosure. Furthermore, the articles “a and “an” as used in this specification and the appended claims should generally be construed to mean one or multiple, unless specified or clear from context to be directed to be a singular form.
[0028] According to an embodiment of the present invention, a stacking structure of color resists would be changed to increase liquidity of the PI and LCD on the basis of without an increase of a planarization layer for not increasing costs. That is, channels are formed at locations where color resists overlay in a color filter layer, at this time, and a function of shielding light does not work because there is only one layer of the color resists existing at the channels. In this case, there is a risk of Sight leakage, so the present invention provides a common electrode line on a first metal layer corresponding to the channels in a Y-axis direction and a metal line on a second meta! layer corresponding to the channels in an X-axis direction to prevent the light leakage.
[00291 To illustrate the technical solutions of the present invention, the following description is illustrated by specific embodiments.
[0030] Refer to FIG. 1, which illustrates a schematic diagram of a structure of a color filter array substrate according to an embodiment of the present invention. For ease of illustration, only related parts of the embodiment of the present invention are illustrated.
[0031] The color filter array substrate comprises a giass substrate 101, a first metal layer 102, an insulating layer 103, an active layer 104, an ohmic contact layer 105 a second metal layer 106, a first passivation layer 107, a color filter layer 108, a second passivation layer 109, and a pixel electrode layer 110. The first metal layer 102 is disposed on the giass substrate 101, and the first metal layer 102 includes a scanning line, and a gate of a thin-film FET. The insulating layer 103 is disposed on the first metal layer 102. The active layer 104 is disposed on the insulating layer 103 for conducting charges from the source of the thin-film FET to the drain of the thin-film FET when the first metal layer 102 is formed. The ohmic contact layer 105 is disposed on both ends of the active layer 104 for letting a contact resistance between the second meta! layer 106 and the active layer 104 be smaller and more easily conducted. The second meta! layer 106 is disposed on the ohmic contact layer 105, and the second metal layer 106 includes a data line, the source and the drain of the thin-film FET. The first passivation layer 107 is disposed on the second meta! layer 106 for isolating the second metal layer 106 and the color filter layer 108. The color filter layer 108 is disposed on the first passivation layer 107, and the color filter layer 108 includes, sequentially arranged, a first color resist, a second color resist, and a third color resist. The second passivation layer 109 is disposed on the color filter layer 108 for isolating the color filter layer 108 and the pixel electrode layer 110. The pixel electrode layer 110 is disposed on the second passivation layer 109.
[0032] Refer to FIG. 2, which illustrates a schematic view of shielding the channels by adoption of a common electrode line according to an embodiment of the present invention. Channels 111 are formed at locations of color resists overlay in the color filter layer 108. A common eiectrode Sine 112 is disposed on the first metal layer 102 corresponding to the channels 111 to achieve light-shielding. The locations where the color resists overlay are regions where adjacent color resists overlap.
[0033] In the embodiment of the present invention, the channels 111 are formed at the locations where the color resists overlay in the Y-axis direction. The common eiectrode line 112 is disposed on the first metal layer 102 corresponding to the channels in the Y-axis direction to achieve light-shielding. That is, a width of the common electrode Sine corresponding to the channelssW is widened in a direction of the data line in order to achieve light-shielding. Preferably, the width of the common eiectrode line corresponding to the channels is greater than or equal to the width of the channels.
[0034] In the embodiment of the present invention, the locations where the color resists overlap can be locations where a red color resist and a blue color resist overlap, locations where a red color resist and a green color resist overlap, or locations where a blue coior resist and a green coior resist overlap. Take an example of a red color resist and a blue color resist which are overlapped, the color resist that is dug to form a channel may be the blue color resist, and also may be the red color resist.
[0035] Please refer to FIG. 1 in conjunction with FIG. 3, a schematic view of shielding the channels by adoption of an additional metal line at the drain of the FET is illustrated in FIG. 3 according to another embodiment of the present invention.
[0036] The coior filter array substrate comprises a glass substrate 101, a first metal layer 102, an insulating iayer 103, an active layer 104, an ohmic contact layer 105, a second metal iayer 106, a first passivation iayer 107, a coior filter layer 108, a second passivation layer 109, and a pixel electrode iayer 110, The first metal layer 102 is disposed on the glass substrate 101, and the first metal layer 102 includes a scanning line, and a gate of a thin-film FET. The insulating layer 103 is disposed on the first metal 8 layer 102. The active layer 104 is disposed on the insulating layer 103 for conducting charges from the source of the thin-film FET to the drain of the thin-film FET when the first metal layer 102 is formed. The ohmic contact layer 105 is disposed on both ends of the active layer 104 for letting a contact resistance between the second meta! layer 106 and the active layer 104 be smaller and more easily conducted. The second metal layer 106 is disposed on the ohmic contact layer 105, and the second metal layer 106 includes a data line, the source and the drain of the thin-film FET. The first passivation layer 107 is disposed on the second metal layer 106 for isolating the second metal layer 106 and the color filter layer 108. The color filter layer 108 is disposed on the first passivation layer 107, and the color filter layer 108 includes, sequentially arranged, a first color resist, a second color resist, and a third color resist. The second passivation layer 109 is disposed on the color filter layer 108 for isolating the color filter layer 108 and the pixel electrode layer 110. The pixel electrode layer 110 is disposed on the second passivation layer 109.
[00371 In this embodiment of the present invention, channels 111 are formed at locations where color resists overlay in the color filter layer 108. A metal line 113 is disposed on the second metal layer 106 corresponding to the channels in the X-axis direction to achieve light-shielding. The locations where the color resists overlap are regions where adjacent color resists overlap.
[0038] In this embodiment of the present invention, the channels 111 are formed at the locations where the color resists overlay in the X-axis direction. The metal line 113 is disposed on the second meta! layer 106 corresponding to the channels in the Xaxis direction to achieve light-shielding. In the embodiment, the metal line 113 is an extended portion of the drain. That is, in a direction of the scanning line, the extended portion of the drain can shield the channels by extending the drain line to the locations of the channels to achieve light shielding. The width of the metal 113 is greater than or equal to the width of the channels.
[0039] in this embodiment of the present invention, the locations where the color resists overlay can be locations where a red color resist and a blue color resist overlap, 9 locations where a red color resist and a green color resist overlap, or locations where a blue color resist and a green color resist overlap. Take an example of a red color resist and a blue color resist which are overlapped, the color resist that is dug to form a channel may be the blue color resist, and also may be the red color resist.
[0040] According to another the embodiment of the present invention, there is an
LCD panel is further provided. The LCD panel comprises includes a color filter array substrate and a liquid crystal layer. The color filter array substrate comprises a glass substrate 101, a first metal layer 102, an insulating layer 103, an active layer 104, an ohmic contact layer 105, a second metal layer 106, a first passivation layer 107, a color filter layer 108, a second passivation layer 109, and a pixel electrode layer 110. The first meta! layer 102 is disposed on the glass substrate 101, and the first metal layer 102 includes a scanning Sine, and a gate of a thin-film FET. The insulating layer 103 is disposed on the first metal layer 102. The active layer 104 is disposed on the insulating layer 103 for conducting charges from the source of the thin-film FET to the drain of the thin-film FET when the first metal layer 102 is formed. The ohmic contact layer 105 is disposed on both ends of the active layer 104 for letting a contact resistance between the second metal layer 106 and the active layer 104 be smaller and more easily conducted. The second meta! layer 106 is disposed on the ohmic contact layer 105, and the second metal layer 106 includes a data line, the source and the drain of the thin-film FET. The first passivation layer 107 is disposed on the second meta! layer 106 for isolating the second meta! layer 106 and the color filter layer 108. The color filter layer 108 is disposed on the first passivation layer 107, and the color filter layer 108 includes, sequentially arranged, a first color resist, a second color resist, and a third color resist. The second passivation layer 109 is disposed on the coior filter layer 108 for isolating the color filter layer 108 and the pixel electrode layer 110. The pixel electrode layer 110 is disposed on the second passivation layer 109.
[0041] in this embodiment of the present invention, channels 111 are formed at locations where color resists overlay in the color filter layer 108. Specifically, the channels 111 are respectively formed at the locations where the coior resists overlay in the Y-axis direction, and the channels 111 are further respectively formed at the locations where the color resists overlay in the X-axis direction. The locations where the coior resists overlay are regions where adjacent color resists overiap.
[0042] in this embodiment of the present invention, a common electrode line 112 is disposed on the first metal layer 102 corresponding to the channels in the Y-axis direction to achieve light-shielding. That is, a width of the common electrode Sine corresponding to the channels 111 is widened in a direction of the data line in order to achieve Sight-shielding. Preferably, the width of the common electrode line corresponding to the channels is greater than or equal to the width of the channels.
[0043] In this embodiment of the present invention, a metal line 113 is disposed on the second metal layer 106 corresponding to the channels in the X-axis direction to achieve light-shielding. In the embodiment, the metal line 113 is an extended portion of the drain. That is, in a direction of the scanning line, the extended portion of the drain can shield the channels by extending the drain line to the locations of the channels to achieve tight shielding. The width of the metai 113 is greater than or equal to the width of the channels.
[0044] In this embodiment of the present invention, the locations where the color resists overlay can be locations where a red color resist and a blue color resist overiap, locations where a red color resist and a green coior resist overlap, or locations where a blue color resist and a green color resist overlap. Take an example of a red color resist and a blue color resist which are overlapped, the color resist that is dug to form a channel may be the blue color resist, and also may be the red color resist.
[0045] In short, the present invention changes a stacking structure of color resists to enhance liquidity of the PI and LCD on the basis of without increase of a planarization layer for not increasing costs. Namely, channels is formed at iocations where color resists overlay in a color filter layer , and a function of shielding light does not work at this time because only one layer of the color resists is existent at the locations of the channeis. in this case, there is a risk of light leakage. Accordingly, the present invention provides a common electrode line on a first metal layer corresponding to the channels in a Y-axis direction and a metal line on a second metal layer corresponding to the channels in an X-axis direction to prevent the Sight leakage. The embodiments of the present invention not only can effectively shield the Sight leakage, but also increase liquidity of PS and LCD.
[00461 Despite one or more preferred embodiments of the present invention having been illustrated and described, those having ordinary skills in the art may easily contemplate equivalent changes and modifications according io the disclosure and drawings of the present invention. All such modifications and variations are considered to be encompassed in the scope defined by the claims of the present invention. Particularly with regard to the various functions performed by the above-described components, the terms used to describe such components that are intended to perform the specified function, which may be performed by any other components (functionally equivalent unless otherwise indicated), even though other components are not the same in the structure as shown in the exemplary implementations of this specification. Furthermore, although a particular feature relating io a number of embodiments has been disclosed in this specification, this feature may be combined with one or more other features to have other embodiments which are desirable and advantageous to a given or particular application. Moreover, the terms including, having, containing, or variations thereof are used in the detailed description or the claims with a meaning similar to the term comprising”.
[0047] In summary, while the present invention has been described with the aforementioned preferred embodiments, it is preferable that the descriptions relating to the above embodiments should be construed as exemplary rather than as limiting of the present invention. One of ordinary skill in the art can make a variety of modifications and variations without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (15)
1. A color filter array substrate comprising: a glass substrate;
a first metal layer disposed on the glass substrate, the first metal layer comprising a scanning line and a gate of a thin-film field-effect transistor (FET);
an insulating layer disposed on the first metal layer;
an active layer disposed on the insulating layer;
an ohmic contact layer disposed on both ends of the active layer;
a second metal layer disposed on the ohmic contact layer, the second metal layer comprising a data line, a source and a drain of the thin-film FET;
a first passivation layer disposed on the second metal layer for isolating the second metal layer and a color filter layer;
the color filter layer disposed on the first passivation layer, the color filter layer including, sequentially arranged, a first color resist, a second color resist, and a third color resist;
a second passivation layer disposed on the color filter layer for isolating the color filter layer and a pixel electrode layer; and the pixel electrode iayer disposed on the second passivation layer; wherein channels are formed at locations where color resists overlap in the color filter layer, a common electrode line is disposed on the first metal layer corresponding to the channels in a Y-axis direction for shielding lights, and a metal Sine is disposed on the second metal layer corresponding to the channels in a X-axis direction for shielding lights, the locations where the color resists overlap are regions where adjacent color resists overlap, the locations where the color resists overlap are locations where a red color resist and a blue color resist overlap, locations where a red color resist and a green color resist overlap, or locations where a blue color resist and a green color resist overlap.
2. The color filter array substrate according to claim 1, wherein the metal Sine is an extended portion of the drain.
3. The color filter array substrate according to claim 1, wherein the channels are respectively formed at the iocations where the color resists overlap in the Y-axis direction.
4. The color filter array substrate according to claim 1, wherein the channels are respectively formed at the locations where the color resists overlap in the X-axis direction.
5. A color filter array substrate comprising: a glass substrate;
a first meta! layer disposed on the glass substrate, the first metal layer comprising a scanning line and a gate of a thin-film FET;
an insulating layer disposed on the first metal layer;
an active layer disposed on the insulating layer;
an ohmic contact layer disposed on both ends of the active layer;
a second metal layer disposed on the ohmic contact layer, the second metal layer comprising a data line, the source and the drain of the thin-film FET;
a first passivation layer disposed on the second metal layer for isolating the second metal layer and a color filter layer;
the color filter layer disposed on the first passivation layer, the color filter layer including, sequentially arranged, a first color resist, a second color resist, and a third color resist;
a second passivation layer disposed on the color filter layer for isolating the color filter layer and a pixel electrode layer; and the pixel electrode layer disposed on the second passivation layer;
wherein channels are formed at locations where the color resists overlap in the color filter layer, a common electrode line is disposed on the first metal layer corresponding to the channels for achieving Sight-shielding, and the locations where the color resists overlap are regions where adjacent color resists overiap.
6. The color filter array substrate according to claim 5, wherein the channels are respectively formed at the locations where the color resists overlap in the Y-axis direction.
7. The color filter array substrate according to claim 6, wherein the channels are further respectively formed at the locations where the color resists overlap in the X-axis direction, and a metal line is disposed on the second metal layer corresponding to the channels for achieving light-shielding.
8. The color filter array substrate according to claim 7, wherein the metal line is an extended portion of the drain,
9. The color filter array substrate according to claim 7, wherein the locations where the color resists overlay are locations where a red color resist and a blue color resist overlap, locations where a red color resist and a green color resist overlap, or locations where a blue color resist and a green color resist overlap.
10. A color filter array substrate comprising: a glass substrate;
a first metal layer disposed on the glass substrate, the first meta! layer comprising a scanning line and a gate of a thin-film FET;
an insulating layer disposed on the first metal layer;
an active layer disposed on the insulating layer;
an ohmic contact layer disposed on both ends of the active layer:
a second meta! layer disposed on the ohmic contact layer, the second metal layer comprising a data line, the source and the drain of the thin-film FET;
a first passivation layer disposed on the second metal layer for isolating the second metai layer and a color filter layer;
the color filter layer disposed on the first passivation layer, the color filter layer including, sequentially arranged, a first color resist, a second color resist, and a third color resist;
a second passivation layer disposed on the color filter layer for isolating the color filter layer and a pixel electrode layer; and a pixel electrode layer disposed on the second passivation layer;
wherein channels are formed at locations where color resists overlay in the color filter layer, a metal line is disposed on the second metal layer corresponding to the channels for achieving light-shielding, and the locations where the color resists overlay are regions where adjacent color resists overlap.
11. The color filter array substrate according to claim 10, wherein the metal line is an extended portion of the drain.
12. The color filter array substrate according to claim 10, wherein the channel is respectively formed at the locations where the color resists overlay in the X-axis direction.
13. The color filter array substrate according to claim 10, wherein the width of the metal is greater than or equal to the width of the channel.
14. The color filter array substrate according fo claim 10, wherein the locations where the color resists overlay are locations where a red color resist and a blue color resist overlap, locations where a red color resist and a green color resist overlap, or locations where a blue color resist and a green color resist overlap.
15. A liquid crystal display panel comprising the color filter array substrate according to any one claim of claim 5 to claim 9.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510504676.9A CN105068346B (en) | 2015-08-17 | 2015-08-17 | A kind of colorful filter array substrate and liquid crystal display panel |
| PCT/CN2015/087619 WO2017028298A1 (en) | 2015-08-17 | 2015-08-20 | Color filter array substrate and liquid crystal display panel |
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| GB201802130D0 GB201802130D0 (en) | 2018-03-28 |
| GB2557485A true GB2557485A (en) | 2018-06-20 |
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| GB1802130.3A Active GB2557485B (en) | 2015-08-17 | 2015-08-20 | Color filter array substrate and liquid crystal display panel |
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| JP (1) | JP6564526B2 (en) |
| KR (1) | KR102032488B1 (en) |
| CN (1) | CN105068346B (en) |
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| CN105425487A (en) * | 2015-12-25 | 2016-03-23 | 深圳市华星光电技术有限公司 | Thin-film transistor array substrate |
| CN110579919B (en) * | 2019-08-08 | 2020-12-04 | 深圳市华星光电技术有限公司 | Array substrate and liquid crystal panel |
| CN115933244A (en) * | 2022-12-22 | 2023-04-07 | 惠科股份有限公司 | Display mother board, preparation method thereof, liquid crystal display panel and electronic paper |
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- 2015-08-20 JP JP2018507732A patent/JP6564526B2/en active Active
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Also Published As
| Publication number | Publication date |
|---|---|
| CN105068346B (en) | 2017-11-28 |
| GB2557485B (en) | 2021-03-31 |
| EA034149B1 (en) | 2020-01-09 |
| JP6564526B2 (en) | 2019-08-21 |
| KR20180041696A (en) | 2018-04-24 |
| KR102032488B1 (en) | 2019-10-15 |
| EA201890517A1 (en) | 2018-07-31 |
| WO2017028298A1 (en) | 2017-02-23 |
| GB201802130D0 (en) | 2018-03-28 |
| CN105068346A (en) | 2015-11-18 |
| JP2018527614A (en) | 2018-09-20 |
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