EA034149B1 - Color filter array substrate and liquid crystal display panel - Google Patents

Abstract

Disclosed is a color filter array substrate. This color filter array substrate comprises a glass substrate, a first metal layer, an insulation layer, an active layer, an ohmic contact layer, a second metal layer, a first passivation layer, a color filter layer, a second passivation layer and a pixel electrode layer. Channels are formed in the color resistance overlapping position of the color filter layer, a common electrode wire is disposed on the first metal layer corresponding to the channels, and a metal wire is disposed on the second metal layer corresponding to the channels. The present invention can effectively shield light from leaking, and can also increase circulation of PI and liquid crystals.

Description

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to the field of display technology and, in particular, to the substrate of a filter matrix and a liquid crystal display (LCD) panel.

Description of the Related Art

Space technology with black columns (BCS), or technology without a black matrix (no-VM), when applied to LCD panels, can shorten the process relative to the one in which the VM is used, and thus can save costs. In the BCS technique, black materials are used around the perimeter of the pixels to obtain a result in which they directly replace the VM, performing the function of screening light. In addition, another result is the maintenance of the thickness of the cell LCD panel when using black materials in the active region (AA). Light shielding for the scan line and data line in AA is due to the interdependence of the stacking of color resistors and metals for its implementation. When laying color resistors, a red resist and a blue resist are usually used for overlapping, since the spectra of these two colors do not overlap. Thus, the optical effect will be improved.

The BCS / No-VM technology on the market today displays flat-panel switching technology (IPS). IPS uses a smoothing layer (PFA) to align the protrusion formed by overlapping color resistors. However, for display products that use BCS / without VMM when using a smoothing layer in the High-Molecule Vertical Orientation (HVA) mode, costs will increase. As a result, a smoothing layer is not used in HVA technology. A problem arises that when using BCS / no-VM technology in HVA display products, protrusions form around the sides due to the overlap of color resistors, and thus the phenomenon of an uneven flow of polyimide (PI ) and liquid crystal during PI coating and liquid crystal filling processes due to retaining protrusions, and thus the display performance is affected.

Therefore, to solve the above technical problems, it is necessary to propose a new technical solution.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a substrate for a filter matrix and an LCD panel in order to solve a problem existing in traditional HVA display products for which BCS / no-VM technology is applied, and protrusions are formed around the sides due to overlapping color resistors , which, therefore, cause the phenomenon of uneven flow of PI and liquid crystal during the processes of coating PI filling liquid crystal, which, thus, affects the performance of the display.

To solve the above problems, the technical solutions of the present invention are as follows.

In accordance with one embodiments of the present invention, the filter matrix substrate comprises a glass substrate; a first metal layer located on a glass substrate, the first metal layer comprising a scan line and a gate of a thin film field effect transistor (FET); an insulating layer located on the first metal layer; an active layer located on an insulating layer; an ohmic contact layer located at both ends of the active layer; a second metal layer located on the ohmic contact layer, the second metal layer containing a data line, as well as the source and drain of a thin-film FET; a first passivation layer located on the second metal layer to isolate the second metal layer from the filter layer; a filter layer located on the first passivating layer, wherein the filter layer contains sequentially ordered first color resist, second color resist and third color resist; a second passivating layer located on the filter layer to isolate the filter layer from the pixel electrode layer; and a pixel electrode layer located on the second passivating layer; wherein the channels are formed in the filter layer at positions where the color resistes overlap, the common electrode line is located on the first metal layer in accordance with the indicated channels in the Y-axis direction, and the metal line is located on the second metal layer in accordance with the specified channels in the X-axis .

Preferably, in the above-described matrix filter substrate, said metal line is an elongated portion of the drain.

Preferably, in the above-described matrix filter substrate, channels are formed in accordance with positions in which color resistors overlap in the direction of the Y axis.

Preferably, in the above-described matrix filter substrate, channels are formed in accordance with positions in which color resistors overlap in the X-axis direction.

In accordance with one embodiments of the present invention, the filter matrix substrate comprises a glass substrate; first metal layer located on glass

- 1 034149 substrate, wherein the first metal layer comprises a scan line and a gate of a thin film field effect transistor (FET); an insulating layer located on the first metal layer; an active layer located on an insulating layer; an ohmic contact layer located at both ends of the active layer; a second metal layer located on the ohmic contact layer, the second metal layer containing a data line, as well as the source and drain of a thin-film FET; a first passivation layer located on the second metal layer to isolate the second metal layer from the filter layer; a filter layer located on the first passivating layer, wherein the filter layer contains sequentially ordered first color resist, second color resist and third color resist; a second passivating layer located on the filter layer to isolate the filter layer from the pixel electrode layer; and a pixel electrode layer located on the second passivating layer; while in the positions where the color resistes overlap, channels are formed in the filter layer, to perform light shielding, the common electrode line is located on the first metal layer in accordance with the indicated channels, and the positions in which the color resistes overlap are the positions in which adjacent color resists.

In the above-described matrix filter substrate, channels are formed in accordance with positions in which color resistors overlap in the direction of the Y axis.

Preferably, in the above-described matrix filter substrate, the channels are further formed in accordance with the positions in which the color resistors overlap in the X-axis direction, and, to perform light shielding, the metal line is located on the second metal layer in accordance with the channels.

Preferably, in the above-described matrix filter substrate, said metal line is an elongated portion of the drain.

Preferably, in the above filter mat substrate, the positions at which the color resistors overlap are the positions at which the red resist and the blue resist overlap, the positions at which the red resist and the green resist overlap, or the positions at which the blue resist overlap and a green resist.

According to another embodiment of the present invention, the filter matrix substrate comprises a glass substrate; a first metal layer located on the glass substrate, wherein the first metal layer comprises a scanning line and a gate of a thin-film FET; an insulating layer located on the first metal layer; an active layer located on an insulating layer; an ohmic contact layer located at both ends of the active layer; a second metal layer located on the ohmic contact layer, the second metal layer containing a data line, as well as the source and drain of a thin-film FET; a first passivation layer located on the second metal layer to isolate the second metal layer from the filter layer; a filter layer located on the first passivating layer, wherein the filter layer contains sequentially ordered first color resist, second color resist and third color resist; a second passivating layer located on the filter layer to isolate the filter layer from the pixel electrode layer; and a pixel electrode layer located on the second passivating layer; and characterized in that in the positions where the color resists overlap, channels are formed in the filter layer, for performing light shielding, the metal line is located on the second metal layer in accordance with the indicated channels, and the positions in which the color resists overlap are the positions in which overlapping adjacent color resistors.

Preferably, in the above-described matrix filter substrate, said metal line is an elongated portion of the drain.

Preferably, in the above-described matrix filter substrate, channels are formed in accordance with positions in which color resistors overlap in the X-axis direction.

Preferably, in the above matrix filter substrate, the width of the metal is greater than or equal to the width of the channels.

Preferably, in the above filter mat substrate, the positions at which the color resistors overlap are the positions at which the red resist and the blue resist overlap, the positions at which the red resist and the green resist overlap, or the positions at which the blue resist overlap and a green resist.

According to yet another embodiment of the present invention, there is provided a liquid crystal display panel comprising the above-described filter matrix substrate.

Compared with the prior art, in the present invention, in order to improve the fluidity of PI and liquid crystal, the arrangement of color resistors has been changed, which does not involve an increase in the size of the smoothing layer, so as not to increase costs. That is, this time, the channels are formed in the filter layer at the positions where the color resistors overlap and the light shielding does not function, since the channels have only one layer of color resist. In Dan

- 2,034149 In the present case, there is a risk of light leakage, and therefore, in order to avoid light leakage, the present invention provides for matching the common electrode line on the first metal layer to the channels in the Y axis direction and matching the metal line on the second metal layer to the channels in the X axis direction. of the present invention not only effectively shields light leakage, but also improves the fluidity of PI and liquid crystal.

To provide a clearer understanding of the above description of the essence of the present invention, preferred embodiments are given with reference to the accompanying graphic materials and are described in detail below.

Short description

In FIG. 1 is a schematic diagram of a structure of a substrate of a filter matrix in accordance with one embodiment of the present invention.

In FIG. 2 is a schematic illustration of channel shielding by selecting a common electrode line in accordance with one embodiment of the present invention.

In FIG. 3 is a schematic illustration of channel shielding by selecting an additional metal line at the FET drain in accordance with another embodiment of the present invention.

Detailed description

Terms used in this description, terms, as one of the embodiments, means that the description in connection with this embodiment serves as an example, special case or illustration of the invention. In addition, the expressions one and one in the context of the present description and the attached claims in general should be regarded as denoting one or more, unless the context indicates or the singular explicitly follows from the context.

In accordance with one embodiment of the present invention, in order to improve the fluidity of PI and liquid crystal, the color resist stacking design has been changed, which does not involve increasing the size of the smoothing layer so as not to increase costs. That is, this time, the channels are formed in the filter layer at the positions where the color resistors overlap, and the light shielding function does not work, since there is only one layer of color resistors in the channels. In this case, there is a risk of light leakage, and therefore, in order to avoid light leakage, the present invention provides for matching the common electrode line on the first metal layer to the channels in the Y axis direction and matching the metal line on the second metal layer to the channels in the X axis direction.

To illustrate the technical solutions of the present invention, the following description is illustrated using specific embodiments.

Turning to FIG. 1, which shows a schematic diagram of a structure of a substrate of a filter matrix in accordance with one embodiment of the present invention. For simplicity of illustration, only parts related to this embodiment of the present invention are shown.

The filter matrix substrate comprises a glass substrate 101, a first metal layer 102, an insulating layer 103, an active layer 104, an ohmic contact layer 105, a second metal layer 106, a first passivation layer 107, a filter layer 108, a second passivation layer 109 and a pixel electrode layer 110. The first metal layer 102 is located on the glass substrate 101, and the first metal layer 102 contains a scanning line and a gate of a thin film FET. An insulating layer 103 is located on the first metal layer 102. An active layer 104 is located on the insulating layer 103 to conduct charges from the source of the thin-film FET to the drain of the thin-film FET when the first metal layer 102 is formed. At both ends of the active layer 104 is an ohmic contact layer 105 that reduces contact resistance between the second metal layer 106 and the active layer 104 and conducive to conductivity. A second metal layer 106 is located on the ohmic contact layer 105, and the second metal layer 106 contains a data line, as well as the source and drain of the thin-film FET. A second passivation layer 107 is located on the second metal layer 106 to isolate the second metal layer 106 from the filter layer 108. A filter layer 108 is located on the first passivating layer 107, and the filter layer 108 comprises a first color resist, a second color resist, and a third color resist. A second passivation layer 109 is arranged on the filter layer 108 to isolate the filter layer 108 from the pixel electrode layer 110. On the second passivating layer 109 is a layer of pixel electrodes 110.

Turning to FIG. 2, which shows a schematic representation of channel shielding by selecting a common electrode line in accordance with one embodiment of the present invention. The channels 111 are formed at the overlapping positions of the color resists in the filter layer 108. To perform light shielding, a common electrode line 112 is arranged on the first metal layer 102 in accordance with the channels 111. The positions in which the color resists overlap are those in which adjacent color resists overlap.

- 3 034149

In this embodiment of the present invention, the channels 111 are formed at positions where the color resistes overlap in the direction of the Y axis. To perform light shielding, the common electrode line 112 is located on the first metal layer 102 in accordance with the channels in the direction of the Y axis. That is, to perform light shielding the line width of the common electrode corresponding to the channels 111, increased in the direction of the data line. Preferably, the line width of the common electrode corresponding to the channels is greater than or equal to the channel width.

In this embodiment of the present invention, the positions in which the color resistors overlap may be the positions in which the red resist and the blue resist overlap, the positions in which the red resist and the green resist overlap, or the positions in which the blue resist overlap colors and green resist. Taking as an example the overlapping red resist and the blue resist, the color resist embedded in the channel may be a blue resist, and also a red resist.

Turning to FIG. 1 together with FIG. 3, a schematic representation of channel shielding by applying an additional metal line to the FET drain is shown in FIG. 3 in accordance with another embodiment of the present invention.

The filter matrix substrate comprises a glass substrate 101, a first metal layer 102, an insulating layer 103, an active layer 104, an ohmic contact layer 105, a second metal layer 106, a first passivation layer 107, a filter layer 108, a second passivation layer 109 and a pixel electrode layer 110. The first metal layer 102 is located on the glass substrate 101, and the first metal layer 102 contains a scanning line and a gate of a thin film FET. An insulating layer 103 is located on the first metal layer 102. An active layer 104 is located on the insulating layer 103 to conduct charges from the source of the thin-film FET to the drain of the thin-film FET when the first metal layer 102 is formed. At both ends of the active layer 104 is an ohmic contact layer 105 that reduces contact resistance between the second metal layer 106 and the active layer 104 and conducive to conductivity. A second metal layer 106 is located on the ohmic contact layer 105, and the second metal layer 106 contains a data line, as well as the source and drain of the thin-film FET. A second passivation layer 107 is located on the second metal layer 106 to isolate the second metal layer 106 from the filter layer 108. A filter layer 108 is located on the first passivating layer 107, and the filter layer 108 comprises a first color resist, a second color resist, and a third color resist. A second passivation layer 109 is arranged on the filter layer 108 to isolate the filter layer 108 from the pixel electrode layer 110. On the second passivating layer 109 is a layer of pixel electrodes 110.

In this embodiment of the present invention, the channels 111 are formed in the filter layer 108 at positions where the color resistors overlap. To perform light shielding, a metal line 113 is arranged on the second metal layer 106 in accordance with the channel in the X-axis direction. The positions in which the color resistors overlap are those in which adjacent color resistors overlap.

In this embodiment of the present invention, the channels 111 are formed at positions where the color resistes overlap in the X-axis direction. To perform light shielding, the metal line 113 is located on the second metal layer 106 in accordance with the channels in the X-axis direction. In this embodiment, the metal line 113 is an elongated portion of the drain. That is, to perform light shielding, the elongated portion of the drain is able to shield the channels in the direction of the scan line by lengthening the drain line to the positions of the channels. The width of the metal 113 is greater than or equal to the width of the channels.

In this embodiment of the present invention, the positions in which the color resistors overlap may be the positions in which the red resist and the blue resist overlap, the positions in which the red resist and the green resist overlap, or the positions in which the blue resist overlap colors and green resist. Taking as an example the overlapping red resist and the blue resist, the color resist embedded in the channel may be a blue resist, and also a red resist.

According to yet another embodiment of the present invention, an LCD panel is further provided. This LCD panel contains a filter matrix substrate and a liquid crystal layer. The filter matrix substrate comprises a glass substrate 101, a first metal layer 102, an insulating layer 103, an active layer 104, an ohmic contact layer 105, a second metal layer 106, a first passivation layer 107, a filter layer 108, a second passivation layer 109 and a pixel electrode layer 110. The first metal layer 102 is located on the glass substrate 101, and the first metal layer 102 contains a scanning line and a gate of a thin film FET. An insulating layer 103 is located on the first metal layer 102. An active layer 104 is located on the insulating layer 103 to conduct charges from the source of the thin-film FET to the drain

- 4,034,149 thin-film FETs when the first metal layer 102 is formed. At both ends of the active layer 104, an ohmic contact layer 105 is disposed which reduces the contact resistance between the second metal layer 106 and the active layer 104 and promotes conductivity. A second metal layer 106 is located on the ohmic contact layer 105, and the second metal layer 106 contains a data line, as well as the source and drain of the thin-film FET. A second passivation layer 107 is located on the second metal layer 106 to isolate the second metal layer 106 from the filter layer 108. A filter layer 108 is located on the first passivating layer 107, and the filter layer 108 comprises a first color resist, a second color resist, and a third color resist. A second passivation layer 109 is arranged on the filter layer 108 to isolate the filter layer 108 from the pixel electrode layer 110. On the second passivating layer 109 is a layer of pixel electrodes 110.

In this embodiment of the present invention, the channels 111 are formed in the filter layer 108 at positions where the color resistors overlap. More specifically, the channels 111 are formed in accordance with the positions in which the color resistes overlap in the direction of the Y axis, and the channels 111 are further formed in accordance with the positions in which the color resistes overlap in the direction of the X axis. The positions in which the color resistes overlap are the positions in which adjacent color resistors overlap.

In this embodiment of the present invention, to perform light shielding, the common electrode line 112 is located on the first metal layer 102 in accordance with the channels in the direction of the Y axis. That is, to perform light shielding, the width of the common electrode line corresponding to channels 111 is increased in the direction of the data line . Preferably, the line width of the common electrode corresponding to the channels is greater than or equal to the channel width.

In this embodiment of the present invention, to perform light shielding, a metal line 113 is arranged on the second metal layer 106 in accordance with the channels in the direction of the Y axis. In this embodiment, the metal line 113 is an elongated portion of the drain. That is, to perform light shielding, the elongated portion of the drain is able to shield the channels in the direction of the scan line by lengthening the drain line to the positions of the channels. The width of the metal 113 is greater than or equal to the width of the channels.

In this embodiment of the present invention, the positions in which the color resistors overlap may be the positions in which the red resist and the blue resist overlap, the positions in which the red resist and the green resist overlap, or the positions in which the blue resist overlap colors and green resist. Taking as an example the overlapping red resist and the blue resist, the color resist embedded in the channel may be a blue resist, and also a red resist.

In short, in the present invention, in order to improve the fluidity of PI and liquid crystal, the color resist stacking design is changed, which does not involve an increase in the size of the smoothing layer so as not to increase costs. Namely: the channels are formed in the filter layer in positions where the color resistes overlap, and the light shielding function does not work, since in the positions of the channels there is only one layer of color resistes. In this case, there is a risk of light leakage. Accordingly, the present invention provides matching the common electrode line on the first metal layer to the channels in the Y-axis direction and matching the metal line on the second metal layer to the channels in the X-axis direction. Embodiments of the present invention can not only effectively shield light leakage, but also improve PI fluidity and liquid crystal.

Although one or more embodiments of the present invention has been illustrated and described, those of ordinary skill in the art can easily assume equivalent changes and modifications in accordance with the disclosure and graphic materials of the present invention. All such modifications and changes are considered to be covered by the scope of the invention defined by the claims. In particular, with regard to the various functions performed by the components described above, terms have been used to describe these components, which are intended to perform a specific function that can be performed by any other components (functionally equivalent, unless otherwise indicated), even if other components are not are the same in design as shown in exemplary implementations of this description. In addition, although specific features are described herein that relate to several embodiments of the invention, these features may be combined to form other embodiments that are necessary and advantageous for a particular application. Moreover, the terms including, having, consisting and their variants are used in the detailed description and claims in a meaning similar to the meaning of the term containing.

Thus, although the present invention has been described using the aforementioned preferred embodiments, descriptions related to the aforementioned embodiment

- 5,034,149 there, the implementation should preferably be construed as exemplary, and not limiting, of the present invention. Those of ordinary skill in the art can make many modifications and changes without departing from the spirit and scope of the present invention as defined by the following claims.

Claims (11)

CLAIM 1. The substrate of the filter matrix containing a glass substrate; a first metal layer located on a glass substrate, the first metal layer comprising a scan line and a gate of a thin film field effect transistor (FET); an insulating layer located on the first metal layer; an active layer located on an insulating layer; an ohmic contact layer located at both ends of the active layer; a second metal layer located on the ohmic contact layer, the second metal layer containing a data line, as well as the source and drain of a thin-film FET; a first passivation layer located on the second metal layer to isolate the second metal layer from the filter layer; a filter layer located on the first passivating layer, wherein the filter layer contains sequentially ordered first color resist, second color resist and third color resist; a second passivating layer located on the filter layer to isolate the filter layer from the pixel electrode layer; and a pixel electrode layer located on the second passivating layer; wherein the channels are formed in the filter layer at positions where the color resistors overlap, the common electrode line is located on the first metal layer in accordance with the indicated channels to perform light shielding, and the positions at which the color resistes overlap are the positions at which adjacent color resistors overlap Resists 2. The substrate of the filter matrix according to claim 1, characterized in that the channels are formed in accordance with the provisions in which the color resistors overlap in the direction of the Y axis. 3. The substrate of the filter matrix according to claim 2, characterized in that the channels are additionally formed in accordance with the provisions in which the color resistors overlap in the direction of the X axis, and to perform light shielding, the metal line is located on the second metal layer in accordance with the channels. 4. The substrate of the filter matrix according to claim 3, characterized in that the metal line is an elongated part of the drain. 5. The substrate of the filter matrix according to claim 3, characterized in that the positions in which the color resistes overlap are the positions in which the red resist and the blue resist overlap, the positions in which the red resist and green resist overlap, or positions in which the blue resist and the green resist overlap. 6. The substrate of the filter matrix containing a glass substrate; a first metal layer located on a glass substrate, the first metal layer comprising a scan line and a gate of a thin film field effect transistor (FET); an insulating layer located on the first metal layer; an active layer located on an insulating layer; an ohmic contact layer located at both ends of the active layer; a second metal layer located on the ohmic contact layer, the second metal layer containing a data line, as well as the source and drain of a thin-film FET; a first passivation layer located on the second metal layer to isolate the second metal layer from the filter layer; a filter layer located on the first passivating layer, wherein the filter layer contains sequentially ordered first color resist, second color resist and third color resist; a second passivating layer located on the filter layer to isolate the filter layer from the pixel electrode layer; and a pixel electrode layer located on the second passivating layer; wherein the channels are formed in the filter layer at the positions where the color resistes overlap, the metal line is located on the second metal layer in accordance with the indicated channels to perform light shielding, and the positions at which the color resistes overlap are the positions at which adjacent color resistes overlap . 7. The substrate of the filter matrix according to claim 6, characterized in that the metal line is - 6 034149 is an elongated part of the runoff. 8. The substrate of the filter matrix according to claim 6, characterized in that the channel is formed in accordance with the provisions in which the color resistes overlap in the direction of the X axis. 9. The matrix substrate of the filter according to claim 6, characterized in that the width of the metal is greater than or equal to the width of the channel. 10. The substrate of the filter matrix according to claim 6, characterized in that the positions in which the color resistors overlap are the positions in which the red resist and the blue resist overlap, the positions in which the red resist and green resist overlap, or positions in which the blue resist and the green resist overlap. 11. A liquid crystal display panel containing a substrate of a matrix of color filters according to claim 1.