GB2515631A - Method of fabricating diodes - Google Patents

Method of fabricating diodes Download PDF

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Publication number
GB2515631A
GB2515631A GB1407633.5A GB201407633A GB2515631A GB 2515631 A GB2515631 A GB 2515631A GB 201407633 A GB201407633 A GB 201407633A GB 2515631 A GB2515631 A GB 2515631A
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wafer
diodes
back surface
layer
proton
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GB1407633.5A
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GB2515631B (en
GB201407633D0 (en
Inventor
Maolong Ke
Ian Francis Deviny
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Zhuzhou CRRC Times Electric Co Ltd
Dynex Semiconductor Ltd
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Zhuzhou CSR Times Electric Co Ltd
Dynex Semiconductor Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

A large diameter wafer is thinned by grinding a back surface and a laser annealed n+ phosphorous implant region is used to form a cathode contact. Multiple back side proton implants are used to fabricate a field stop layer. The proton implanted region is annealed by preheating in an oven combined with laser annealing. The cathode and field stop layer structure may also be used in an IGBT.

Description

METHOD OF FABRICATING DIODES
Field of the Invention
This invention relates to a method of fabricating diodes, for example power diodes, particularly of the fast recovery type.
Background to the Invention
Fast recovery power diodes typically consist of p-n-n-n doped regions, that is to say p-type anode layer, it voltage blocking layer, a gradually-increased n-type doped buffer region and a shallow, but heavily-doped, n backside cathode layer respectively. The thickness of the ft region is depend- ent upon the diode voltage rating for its applications and it represents a signifi-cant portion of the device total thickness. The doping profile of the n-type buffer region determines the smoothness of the diode recovery characteristics. The importance of the n-type buffer for the ruggedness of the diode recovery has been demonstrated before [See References 1-3]. Therefore, most of the power is diodes today consist of a long diffused n-type buffer, which can be incorporated at the substrate level through high temperature annealing. For medium to low voltage rated diodes (<1700V), the thickness of the it region is typically less than 150pm, and the total thickness, which includes all four regions (p-n-n-n), may only be around 200pm or even less.
Currently, the Si substrates used for diode fabrication typically start with pre-diffused n-type buffer on the backside, hence the thickness of the it region, or the device voltage rating, is pre-determined as well. Different Si substrates are, therefore, used for the fabrication of different voltage rated diodes. How-ever, as substrate thickness is necessarily increased with the wafer diameter for mechanic stability, the thickness of the pre-diffused n-type buffer region in-creases as well in order to keep the ii region (i.e. the device voltage rating) constant.
For example, for 6 inch (150mm) diameter wafer production line, the substrate thickness used for diode production is around 320pm, where the thickness of the n-type pre-diffused buffer is around l7Opm for 1700V rated di- odes and even thicker for 1200V or lower rated diodes. It is quite time consum-ing and costly to make a lengthy buffer through diffusion. The problem is made much worse for 8 inch (200mm) wafer production line, because the substrate thickness has to be increased significantly for mechanic strength during photo- lithographic processes. The typical substrate thickness for 8 inch (200mm) wa-fer is around 700pm, and the diffused n-type buffer would need to be thicker than 500pm for 1700v or lower rated diodes. It is very difficult and would be ex-tremely expensive to request such a thick pre-diffused n-type buffer substrates for 8 inch wafer production line. An object of the present invention is to provide an alternative method for thin wafer fast recovery diodes and IGBT fabrication.
References [4] and [5] disclose the implantation of protons. Protons are not very effective dopants because protons themselves are not dopants. They have to react with other species, such as oxygen in silicon, to form n-type do-pants.
Summary of the Invention
According to the invention, there is provided a method of fabricating di-odes in which a substrate wafer is processed to create a doped layer structure, the wafer being doped with n-impurities and having a front surface and a back surface, the method comprising: forming an anode on the front surface; grinding the back surface to reduce the thickness of the wafer; doping the back surface with n impurities to form a cathode layer; forming a buffer layer on the inside of the cathode layer using multiple n-type proton implants through the back sur- face and activating both the back n+ impurities and the proton implants by heat-ing the wafer to an elevated temperature below that required for annealing and maintaining the said elevated temperature while applying laser annealing to the heated wafer.
The substrate wafer will typically be of silicon, but other substrates such as silicon carbide may also be used.
Localised annealing at the desired position within the thickness of the wafer is achieved more efficiently using laser annealing. The elevated tempera- ture is suitably 100-450°C, with around 300-350°C being found to be an effec-tive practical range, although up to 400°C may be useful if the protons to be treated are especially deep inside the wafer (relative the back side). The pre-heating temperature chosen may vary depending on the location of the proton implant within the wafer. Pre-heating changes the temperature profile of the wafers during laser annealing, allowing deeper impurity activation.
The anode may be formed on the front surface using boron implants and thermal diffusion. Photolithographic processes may also, or alternatively, be carried out on the front surface prior to grinding. A thin Ti layer may be deposit-ed on the cathode layer and annealed by laser annealing.
Brief Description of the Drawings
Inthedrawings: Figure 1 is a schematic diagram showing the key processing steps in-volved in thin wafer diode fabrication in accordance with the invention; Figure 2 shows a typical doping profile for a 1700V fast recovery diode, using multiple proton implantations; Figure 3 is a graph of simulated forward I-V characteristics for three dif-ferent buffer structures; Figure 4 is a graph of simulated reverse blocking voltage for three differ-ent buffer structures; Figure 5 is a graph of transient reverse recovery waveform for cathode current and voltage under the initial current condition of 300A and di/dt=1 000AIps; Figure 6 is a graph of measured dynamic recovery waveforms for diodes with pre-diffused n-type buffer at three different conditions; Figure 7 is a graph of measured dynamic recovery waveforms for diodes with proton implanted buffer at three different conditions; and Figure 8 is a graph comparing recovery energy loss against operating current for diodes with conventional diffused buffers against diodes with proton-implanted buffers in accordance with the invention.
Detailed Description of the Illustrated Embodiment
Figure la illustrates a standard uniformly it doped Si wafer, which is used as the initial substrate. A p-type anode contact layer is formed in the front side of the wafer through Boron implant and thermal diffusion. All the photolith- ographic processing steps are also applied to the front side at this stage, requir-ing the water to have the necessary mechanical strength for some delicate steps, such as stepper for feature alignment, and thus at this stage the sub-strate has a thickness greater than that appropriate for the voltage rating of the end device. This stage is represented in Figure lb. The substrate is then subjected to grinding with standard wafer grinding equipment to reduce the thickness to that which is appropriate for the voltage rating of the diodes. This stage is represented by Figure 1 c.
An n-type cathode contact layer is then formed on the backside by high dose phosphorus implantation, typically to a depth within 0.5pm, the result be-ing illustrated by Figure id. Once the front-side is fully processed, the wafer temperature has to be limited to below 500°C to protect the processed patterns on the front side. Such a temperature restriction has adverse effects on both the n-type buffer formation and the impurity activation for the backside contact layer.
To further improve the contact resistance for the back cathode contact, a thin layer of Ti can be deposit onto the n contact layer and then using laser again to anneal and form a TiSi layer. This is because Ti is an inherently better metal for forming an ohmic contact onto n layer than aluminium. The reverse is true for the p-type doped anode contact where aluminium metal is used.
For the backside bufter formation, multiple n-type proton implants are used, as illustrated at Figure le. The reason for choosing the proton implants for n-type buffer here is at least twofold.
Firstly, protons are the only available species which can be implanted deep enough (a few tens of micrometres) for the buffer purpose. For example, according to simulation results from SRIM program, protons can penetrate about 3Opm deep inside silicon with ion energy of 1.5MeV, but carbon only about 2pm deep and phosphorous only 1.4pm. Multiple implantations are needed to achieve a doping profile which can lead to a smooth reverse recov-ery. Typically, the implantations are within 3-4Opm from the back surface of the wafer. However, relatively high doses are required in order to achieve neces-sary doping level for voltage blocking purpose. The conversion efficiency from protons to n-type dopants is very low, normally under one per cent. In other words, a proton dose of 1 el 3cnt2 will produce less than 1 eli cm2 n-type do-pants. The use of multiple implantations of protons to form a buffer or field stop zone in semiconductor devices has been described in US6482681 Bl and US7514750B2, for example. Secondly, its activation temperature is around 450°C, which is within the 500°C temperature limit discussed early.
Both impurity diffusion for buffer formation and activation for low contact resistance typically require the temperature to be above 1000°C, but the tradi-tional methods of high temperature annealing to achieve impurity diffusion for buffer formation and activation for low contact resistance at the cathode contact are not suitable here.
Instead, laser annealing is used for the backside impurity activation to achieve good ohmic contact, as well as for activation of the proton implants, these being achieved in a single scanning laser annealing step in conjunction with an elevated temperature in the wafer holder, as illustrated in Figure lf..
The key advantage of laser annealing is the fact that the annealing is highly lo- calized to within a very shallow depth from the back surface. Only the tempera- ture under the laser spot is very high (>1400°C) and it can melt the Si under-neath. But the temperature drops drastically away from the direct laser spot and also drops very quickly as well in vertical direction into the silicon. It can melt the back surface up to a few hundred nm thickness and therefore com-pletely activate the dopants within the melted region. The temperature then drops dramatically over a short distance to reach below 100°C above the base wafer temperature at 5Opm from the back surface. At the front surface it is ex-pected to remain at the pre-heating temperature during the annealing, keeping the temperature at the front half of the wafer to 350°C or below.
Figure 2 displays a typical doping profile for 1700V rated diodes, where the wafer was thinned from the backside to appropriate thickness after the front side processing was completed and the n-type buffer was then obtained through multiple proton implantations using a tandem accelerator and subse-quent annealing at 450°C. The proton implantation was repeated three times with three different energies and doses (for example 35OkeV and 8e1 3cm2; 700keV and 6e13cm2; and 1.2MeV and 4e13cm2) to achieve the displayed doping profile. Separate SRP measurements confirmed the simulated doping profile. The highest proton implantation energy used here was under 2MeV.
Figure 3 displays simulated forward current characteristics for three dif-ferent buffer structures, where the number of implantations varied from 2, 3 and 4 respectively. The forward voltage Vf was calculated to be 1.63, 1.58 and 1.56V respectively for 2, 3 and 4 proton implantations under 1 OOA current con-dition. The drop of Vf as the number of implantation increases can be explained by the beneficial effect of electron injection. The reverse blocking characteris-tics are displayed in Fig. 4 where 1 950V blocking capability was achieved for all three implantation conditions. Figure 5 shows the reverse recovery property under the di/dt condition of 1 000A/ps and the initial forward current of 300A. A smooth recovery was obtained for all three cases and the recovery curves were nearly identical for all three buffer structures.
Figures 6 and 7 compare the dynamic recovery characteristics from an assembled substrate consisted of two diodes. Figure 6 represents recovery waveforms obtained from wafers with pre-diffused n type buffer and Figure 7 represents the waveforms from wafers without pre-diffusion of the buffer, the buffer instead being achieved by proton implantation with three proton implanta-tions with different energies and doses as identified hereinbefore. Three test conditions were displayed, initially the voltage was 900V and current 600A (equivalent to 300A per diode); then the current reduced to 56A while keeping the voltage at 900V level; and finally the voltage increased to 1100V with the current reading of 66A. The latter two conditions represent around 10% of the nominal current condition (-30A per die). It is well known that the diodes are more prone to snappy recovery under low current conditions. However, the ob- served recovery waveforms were quite smooth under all these testing condi-tions for both types of diodes. A longer recovery current tail was observed for diodes made out of pre-diffused wafers (Figure 6) than that from the proton im-planted wafers (Figure 7).
Referring to Figure 8, which illustrates the measured recovery energy loss (Erec) against operating current, the energy losses during the recovery (Erec) were found to be higher for diodes with pre-diffused buffer than that from proton implanted. Typically over 1 00mJ was observed under 600A current con-dition for one case and around 4OmJ for others. The higher energy loss can be explained by the longer current tail mentioned before during the recovery.
However, the static losses (VF) under forward current condition for the proton implanted buffer diodes were found to be around 2.6V at the current of 600A (300A per diode), whereas the same VF loss was only around 1.82V for the other diodes. So clearly a trade-off between forward VF loss and reverse re-covery loss (Erec) existed here. A similar trade-off curve was reported widely before [Reference 7].
References [1] FelsI H. P., Heinze B. and Lutz J., "Effects of Different Buffer Struc-tures on the Avalanche Behaviour of High Voltage Diodes Under High Reverse Current Conditions" lEE Proc.-Circuits Devices Syst., vol. 153, No. 1, p. 11-15 (2006) [2] Heinzea B., Lutza J.,Felslb H. P., Schulze H. J., "Ruggedness Analy-sis of 3.3 kV High Voltage Diodes Considering Various Buffer Structures and Edge Terminations", Microelectronics Journal Vol. 39, p. 868-877 (2008) [3] Lutz J., Baburske R., Chen R. M., Heinze B., Domeij M., FelsI H. P., and Schulze H. J., "The nn+-Junction as the Key to Improved Ruggedness and Soft Recovery of Power Diodes", IEEE Transactions on Electron Devices, Vol. 56, No. 11, p. 2825-2832 (2009) [4] Mauder A., Schulze H. J., Hille F., Schulze H., Pfaffenlehner M., Schaffer C., Niedernostheide F. J., "Semiconductor Device and Fabrication Method Suitable Therefor" US Patent No: US 7514750 B2 (2009) [5] KIug J. N., Lutz J., Meijer J. B.," n-type doping of silicon by proton Im-plantation" Proceedings of the 14th European conference on Power Electronics and Applications (EPE2O1 1), p.1-7 (2011) [6] Rahimo M., Corvasce C., Vobecky J., Otani Y., Huet K., "Thin-wafer silicon IGBT with advanced laser annealing and sintering process" IEEE Elec-tron Device Letters, vol. 33, No. 11, p. 1601-1603 (2012) [7] Siemieniec R. and Lutz J. "Axial lifetime control by radiation induced centers in fast recovery diodes" Proc. ISPSD-2002, p. 83-90 (Prague 2002)

Claims (9)

  1. CLAIMS1. A method of fabricating diodes in which a substrate wafer is pro- cessed to create a doped layer structure, the wafer being doped with n-impuri-ties and having a front surface and a back surface, the method comprising: forming an anode on the front surface; grinding the back surface to reduce the thickness of the wafer; doping the back surface with n impurities to form a cathode layer; forming a buffer layer on the inside of the cathode layer using multiple n-type proton implants through the back surface and activating both the back n+ impurities and the proton implants by heating the wafer to an elevated temperature below that required for annealing and maintaining the said elevated temperature while applying laser annealing to the heated wafer.
  2. 2. A method according to Claim 1, wherein the substrate wafer is a silicon wafer.
  3. 3. A method according to Claim 1 or 2, wherein said elevated tem-perature is 100-450°C.
  4. 4. A method according to Claim 3, wherein said elevated tempera-ture is 300-350°C.
  5. 5. A method according to any preceding claim, comprising forming the anode on the front surface using boron implants and thermal diffusion.
  6. 6. A method according to any preceding claim, comprising implanting the back surface with arsenic or phosphorus to form the n impurities.
  7. 7. A method according to any preceding claim, comprising carrying out photolithographic processes on the front surface prior to grinding.
  8. 8. A method according to any preceding claim, comprising depositing a thin Ti layer on the cathode layer and laser annealing the Ti layer.
  9. 9. A method of fabricating diodes, substantially as described with reference to the drawings.
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Publication number Priority date Publication date Assignee Title
CN105321817A (en) * 2015-10-26 2016-02-10 株洲南车时代电气股份有限公司 Diode and cathode metallization method therefor
DE102016112139B3 (en) * 2016-07-01 2018-01-04 Infineon Technologies Ag A method of reducing an impurity concentration in a semiconductor body

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482681B1 (en) * 2000-05-05 2002-11-19 International Rectifier Corporation Hydrogen implant for buffer zone of punch-through non epi IGBT
US20070108558A1 (en) * 2005-11-10 2007-05-17 Fuji Electric Device Technology Co., Ltd Semiconductor device and method of manufacturing the same
US7514750B2 (en) * 2004-09-30 2009-04-07 Infineon Technologies Ag Semiconductor device and fabrication method suitable therefor
US20100015788A1 (en) * 2007-09-10 2010-01-21 Yuichiro Sasaki Method for manufacturing semiconductor device
WO2013073623A1 (en) * 2011-11-15 2013-05-23 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6482681B1 (en) * 2000-05-05 2002-11-19 International Rectifier Corporation Hydrogen implant for buffer zone of punch-through non epi IGBT
US7514750B2 (en) * 2004-09-30 2009-04-07 Infineon Technologies Ag Semiconductor device and fabrication method suitable therefor
US20070108558A1 (en) * 2005-11-10 2007-05-17 Fuji Electric Device Technology Co., Ltd Semiconductor device and method of manufacturing the same
US20100015788A1 (en) * 2007-09-10 2010-01-21 Yuichiro Sasaki Method for manufacturing semiconductor device
WO2013073623A1 (en) * 2011-11-15 2013-05-23 富士電機株式会社 Semiconductor device and method for manufacturing semiconductor device

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Ke et al. Process development and proton implanted n-type buffer optimization for 1700V rated thin wafer fast recovery diodes