GB2508788A

GB2508788A - Clock signal error detection system

Info

Publication number: GB2508788A
Application number: GB1208385.3A
Authority: GB
Inventors: Kenji Imamoto; Keiji Maekawa; Naoki Shibata; Yoichi Sugita; Takeshi Takehara; Hideo Sakuyama
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2009-12-04
Filing date: 2010-11-26
Publication date: 2014-06-18
Anticipated expiration: 2030-11-26
Also published as: GB2508788B; WO2011068080A1; GB201208385D0; JP5161196B2; JP2011120059A

Abstract

Disclosed is a clock signal error detection system, which prevents system faults that result from clock signal errors by using serial communications to detect same. A receiver (2) of the clock signal error detection system periodically reads signals received via serial (asynchronous) communications that are transmitted from a transmitter (1), and a clock signal error detection device (23) determines that a clock signal error has occurred, and outputs an alert, if the bit value that is read immediately after the delimiter of each respective bit differs from the bit value that is read immediately prior to the delimiter following thereafter.

Description

DESCRIPTION

Title of Invention: CLOCK SIGNAL ERROR DETECTION SYSTEM

Technical Field

[0001] The present invention relates to a clock signal error detection system that receives a serial communication from an external device, and detects an error of a clock signal based on the communication.

Background Art

[0002] A clcck signal is a periodical signal used to synchronize a plurality of electronic circuits when a computer or a digital circuit operates. Where there occurred an error in a clock signal oscillation, the electronic circuits will fail to synchronize with each other and might cause unexpected malfunction. Therefore, a signal error detection system is needed that diagnoses whether the clock signal oscillation is normal.

[0003] In conventional error detection systems for optical disk recording and reproduction devices, for example, a clock signal error is detected by comparing the frequency of a wobble signal used in an optical disk and the clock signal frequency. A wobble signal refers to a signal formed by intensity variation of reflected light from a fine groove formed on an optical disk and having a predetermined amplitude and period. The frequency of the wobble signal is used for a carrier wave for reading data from the optical disk.

[0004] In conventional techniques, a value obtained by counting, with clock signals, the number of cycles of a wobble signal detected from an optical disk is compared with a value obtained by counting the number of cycles of the wobble signal that would normally be obtained. If there is a difference between the two values, it is determined that there is an error in the wobble signal frequency or in the clock signal oscillation.

[0005] Further, for example, Patent Literature 1 discloses a technique in a serial input circuit, which includes determining that there is a clock signal error if a time at which a communication has been completed is deviated from a time at which the communication would be completed with a normal operation; and Patent Literature 2 discloses a technique that includes counting the number of cycles of a reception signal with clock signals, and if the counted value is deviated from the number of counts taken in a normal state, determining that there is a clock signal error, while not determining that there is a clock signal error if the number of counts is extremely small, regarding it as a result of a noise affecting the reception signal.

[0006] E'urther, Patent Literature 3 discloses a technique that includes obtaining a plurality of pieces of digital data converted by an AD converter by the time when one cycle of an external clock signal completes, and if there is any one piece of the obtained digital data that is different from others, determining that there is a failure in the AD converter (a failure of the AD converter caused by breakage of a clock signal line) Citation List Patent Literature [0007] Patent Literature 1: Japanese Patent Laid-Open Publication No. 2002-27016 Patent Literature 2: Japanese Patent Laid-Open Publication No. 2000-222829 Patent Literature 3: Japanese Patent Laid-Open Publication No. 2000-236388

Summary of Invention

Technical Problem [0008] The above-stated systems can employ a wobble signal since they are optical disk recording and reproduction devices. However, in usual environments, the problem is that it is not possible to obtain a signal that has a predetermined amplitude and period, such as a wobble signal.

[0009] Furthermore, although the above-stated systems can employ serial communication instead of a wobble signal, the transmitter needs to transmit a testing signal for diagnostic purpose since the amplitude and the period is predetermined. Moreover, according to the conventional techniques, if a communication noise is superimposed on a signal, the problem is that an erroneous count of the number of cycles for a reception signal is caused, leading to erroneous determination that there is an error in the clock signal oscillation.

[0010] In view of the foregoing problems, an object of the present invention is to provide a clock signal error detection system that detects a clock signal error by receiving a serial communication from an external device even in an environment in which a signal having an amplitude and a period that are predetermined cannot be obtained, and that determines the effect of a noise and the effect of a error in a clock signal oscillation even if a noise is superimposed on a communication.

[0011] A clock signal error refers to a state in which the clock signal oscillates at a higher rate or a lower rate than a predetermined clock rate under a normal state.

Solution to Problem [0012] To achieve the above-described object, the gist of a primary feature of the present invention is a clock signal error detection system comprising: a clock signal generation device, a serial communication receiving device, and a clock signal error detection device that detects a clock signal error by comparing the period of a received serial communication and the period of a clock signal.

[0013] Further, the above-described clock signal error detection device is featured by having a noise identification function that discriminates an effect of a communication noise from a clock signal error by analyzing the tendency of the occurrence of the detected error.

Advantageous Effect of Invention [0014] According to the present invention, it is possible to detect a clock signal error by receiving a serial communication from an external device, even in an environment in which a signal having a predetermined amplitude and period cannot be obtained. Moreover, it is possible to discriminate the effect of noise from the effect of an error in clock signal oscillation even if a noise is superimposed on the serial communication.

Brief Description of Drawings

[0015] {Figure 1] Figure 1 is a diagram showing one exemplary configuration of a clock signal error detection system according to a first embodiment of the present invention.

[Figure 2] Figure 2 is a diagram showing one exemplary configuration of a clock signal error detection system according to a second embodiment of the present invention (a configuration in which usage of a plurality of transmitters and an error clock signal identification device is added to the configuration described in Figure 1.) [Figure 3] Figure 3 is a flowchart showing a procedure until the output of an alert according to clock signal error detection by a receiver in the first and the seccnd embodiments of the present invention.

[Figure 4] Figure 4 is a flowchart showing a procedure until the output of an alert according to clock signal error detection by the receiver in the first and second embodiments of the present invention. In addition to the procedure of Figure 3, a process is performed that identifies the cause by which inconsistency has occurred (a clock signal error or a communication noise) based on the tendency of the positions where inconsistency in bit values has occurred.

[Figure 5] Figure 5 is a flowchart showing the procedure until the output of an alert according to clock signal error detection by the receiver in the first and the second embodiment of the present invention. In addition to the procedure of Figure 4, a process is performed that identifies a clock signal in which an error has occurred based on a failure rate of a transmitter and/or receiver that have performed a serial communication.

[Figure 6] Figure 6 is a diagram showing a timing to read a reception signal in the first and second embodiments of the present invention. Figure 6 also shows an operation in which a transmitter clock signal and a receiver clock signal synchronize with each other so that the reception signal is correctly read.

[Figure 7] Figure 7 is a diagram showing a timing to read a reception signal in the first and second embodiments of the present invention. Figure 7 shows inconsistency of bit values read before and after the delimiters of the bit values caused due to the faster speed of the oscillation of the clock signal of the receiver than that of the transmitter.

[Figure 8] Figure 8 is a diagram showing a timing to read a reception signal in the first and second embodiments of the present invention. Figure 8 shows inconsistency of bit values read before and after the delimiters of the bit values caused due to the slower speed of the oscillation of the clock signal of the receiver than that of the transmitter.

[Figure 9] Figure 9 is a diagram showing a timing to read a reception signal in the first and second embodiments of the present invention. Although the clock signal of the transmitter and the clock signal of the receiver oscillate at the sane speed, inconsistency of the bit values is caused before and after the delimiters of bit values, due to a communication noise.

[Figure 10] Figure 10 is a diagram showing a timing to read the reception signal of the first and second embodiments of the present invention. Figure 10 shows changing a range to be read in consideration of the allowable range of error of the clock signal oscillation.

Description of Embodiments

[0016] Hereafter, the embodiments of the present invention will be described with reference to the drawings.

However, it should be noted that the drawings are schematic ones.

First Embodiment [0017] Figure 1 shows a configuration of the present embodiment. The present embodiment uses a transmitter 1 that transmits a serial communication and a receiver 2 that receives a serial communication transmitted from the transmitter 1 via a network 3 to detect a clock signal error, The transmitter 1 comprises a clock signal generation device 11 and a serial communication transmission device 12. The receiver 2 comprises a clock signal generation device 21, a serial communication receiving device 22 for receiving a serial communication transmitted from the serial communication device 12, and a clock signal error detection device 23 that detects a clock signal error based on the data received through the serial communication.

[0018] Using Figure 6, a serial communication that uses an asynchronous scheme will be described. If there is no information conveyed on data transmission/receiving, the transmitter 1 transmits stop bits consecutively. A start bit comprising 1 bit is transmitted before information transmission, and 7 to 8 bits of data bits follow the start bit, and a parity bit comprising 1 bit follows the data bits and finally a stop bit or stop bits comprising 1 to 2 bit(s) follow(s) the parity bit in the transmission.

[0019] The prescribed start bit value is 0, and the prescribed stop bit value is 1. The transmitter 1 transmits each bit with a predetermined period. In this transmission, the transmission period is measured by using the clock signal generation device 11 of the transmitter 1. similarly, the receiver 2 uses the clock signal generation device 21, and reads the reception signal for each predetermined period to receive the signal as a bit string.

[0020] Hereafter, a clock signal error detection system performing a serial communication using an asynchronous scheme will be described. However, the system can be also implemented with a serial communication of a clock synchronization scheme. V'Jith such a serial communication of a clock synchronization scheme, a clock signal in which repetition of 0 and 1 takes place with a predetermined period is transmitted separately from a data signal. Accordingly, by using the clock signal as a reception signal, a clock signal error detection system equivalent to the below-described one can be configured.

10021] Next, using Figure 6, an operation for detection of an error of a clock signal will be described. A flowchart of the detection procedure is shown in Figure 3.

Hereafter, a period for each 1 bit of received data is referred to as a fundamental period. During the fundamental period, a reception signal is constant, and each period has delimiters of a bit value. Since the reception signal is created by the transmitter, the position of the delimiter is determined by the clock signal generation device 11 of the transmitter 1, and the timing to read a reception signal is determined by the clock signal generation device 21 of the receiver 2.

[0022] The serial communication receiving device 22 receives a serial communication transmitted from the serial communication transmission device 12 of the transmitter (S300) [0023] The receiver 2, upon detection of falling of the reception signal, regards the time of the detection as a time of onset of the start bit, and reads reception signals before and after the delimiters of each bit transmitted for each fundamental period, based on a clock signal generated by its own clock signal generation device 21, and records the bit value thereof (3301) [002 4] The serial communication receiving device 22, when having read a stop bit, stops reading and sends the read bit value to the clock signal error detection device 23.

If 0 is read as the stop bit, a framing error is occurring. Even in this case, the read bit values are sent to the clock signal error detection device 23. The clock signal error detection device 23 checks the bit value at a position immediately after a delimiter position (3302) [0025] If a bit value of the position immediately prior to the delimiter position after one fundamental period therefrom is consistent, the device determines no clock signal error has occurred and after elapse of a predetermined time period performs the diagnosis again.

If the bit value is inconsistent, the device determines that a clock signal error (3303) has occurred and outputs an alert.

[0026] A bit value, by nature, does not vary from a delimiter position to the next delimiter position.

Therefore, as long as the bit values before and after the delimiter positions are consistent, the determination that any error has occurred is not to be provided.

However, in the case where there is a variation in the bit values before and after the delimiter positions, it can be estimated that such state is caused by an offset that has occurred for a deliniter position calculated by the clock signal generation device 21 of the receiver side, with respect to the actual delimiter position of the reception signal, due to occurrence of offset between the clock signal oscillation of the transmitter side and that of the receiver side. Therefore, it is possible to detect a clock signal error by examining the consistency of the bit values.

[0027] The timing for reading a reception signal may be determined depending on the allowable range of a clock signal offset of a system that uses the clock signal.

The timing to read the reception signal in the case where it is determined according to a clock signal error allowable range of the system is shown in Figure 10.

[0028] In Figure 10, where the fundamental period is T second(s) and the allowable range of error of the clock signal is ±E percent, the shortest period to reach the allowable range of error is set S second(s), and the longest period is set L second(s). Here, S = T x (1 -E / 100), and L = T x (1 -I-E / 100).

[0029J Where the clock signal error detection process is performed, the device waits for S second(s) after the start bit is detected, and then reads a reception signal for L -S seconds. If a delimiter of bits is detected in the reception signal during the reading, the device waits for S second(s) from the time of the detection, and then reads the reception signal for L -S seconds and attempts to detect a delimiter.

[0030] For the delimiter of a bit value, the present embodiment employs a position where the bit value has varied for the first time after the start of reading the reception signal. If the same bit value consecutively appears and the delimiter of the bit is not detected, detection of the delimiter is attempted by starting reading of the reception signal S second(s) after the last time at which reading of reception signal is started, and continuing reading until L second(s) after the last time at which reading of the reception signal is terminated. After this, the same process is repeated until the stop bit is read.

[0031] The clock signal error detection device 23 may determine the clock signal error based on the tendency of occurrence of bit value inconsistency. The bit value inconsistency is seen not only where an error has occurred in the clock signal oscillation, but also where the communication noise has occurred.

[0032] However, the position where the bit value inconsistency occurs varies according to the cause thereof. If the inconsistency is caused by a communication noise, the bit value inconsistency appears only where the noise is generated. By contrast, if the inconsistency is caused by a clock signal error, the offsets of the delimiter positions accumulate. Therefore, bit value inconsistency occurs at a plurality of positions.

[0033] Therefore, an alert may be output in view of the discrimination between the communication noise and the clock signal error based on the tendency in the position(s) where the bit value inconsistency has occurred. A flowchart that additionally includes the process is shown in Figure 4.

[0034] The serial communication receiving device 22 receives a serial communication transmitted by the serial communication transmission device 12 of the transmitter (S400) . After the start bit included in the initial position of the received signal is read, a reception signals before and after the delimiters of each bit transmitted for each fundamental period are read and the bit value are recorded based on the clock signal generated by the own clock signal generation device 21 (S40l) [0035] The serial communication receiving device 22, when having read a stop bit, stops reading and sends the read bit value to the clock signal error detection device 23.

The clock signal error detection device 23 checks the bit values immediately after the delimiter positions and records the positions where the bit value is inconsistent with the bit value of the position immediately prior to the delimiter position after one fundamental period therefrom (S402) [3036] When all the bit values are consistent, the device determines that no clock signal error has occurred, and performs diagnosis again after elapse of a predetermined time period (S403) [0037] If any position that is inconsistent is detected, the cause of occurrence of the inconsistency is identified based on the conditions (bit error rate or the like) of the communication channel at the time of sending of the reception signal (S404) [0038] If it is estimated that there was a communication noise, it is determined that no clock signal error has occurred, and performs diagnosis again after elapse of a predetermined time period. In other cases, the device determines that a clock signal error has occurred and outputs an alert (S405) [0039] An exemplary case where inconsistency has occurred by occurrence of a clock signal error that caused an oscillation faster than the normal state is shown in Figure 7, such a case with lower speed than the normal state is shown in Figure 8, and a case where the inconsistency is caused by a communication noise is shown in Figure 9.

[00401 As compared to the case where a communication noise causes bit inconsistency, in those cases with a clock signal error, the probability that the position where the bit value is inconsistent appears a plurality of times becomes clearly high. Therefore, statistical methods, such as Bayesian estimation and data mining, can be used to identify the cause of the inconsistency occurrence with high accuracy.

[0041] The clock signal error detection device 23 may confirm if received data includes a communication error by checking the parity bit added to the received data cr a communications error detection method such as Error Correcting Code (ECC), Cyclic Redundancy Check (CRC), and so on, in order to discriminate a communication noise.

[0042] The clock signal errcr detection device 23 may use, for clock signal error detection, only received data that does not include a bit error, based on a result of the error correction.

[0043J Further, the bit error rate may be determined according to a plurality of transmitters or a communication environment, such as positions to perform communication, and a time zone for communicaticn, and the like, and it may be determined whether the error detection is necessary, or whether output of an alarm is necessary, according to the bit error rate. For example, in an environment where the bit error rate is high (there are many communication noises), it may be determined that the accuracy of the clock signal error detection is low, and received data at the time point may be segregated so as not to be used for error detection.

[0044] The clock signal error detection device 23 may, where communication errors are detected a predetermined number or more times in the process for confirming the above-described communication errors, determine that a clock signal error has occurred. In other words, although the above-described method has employed reading two or more positions before and after the delimiters of each bit, it is also possible to read one bit for each time at a predetermined timing to confirm whether a communication error is included in the reception signal, to determine the presence of the clock signal error.

[0045] Moreover, similar to the above-described method, the timing for reading the reception signal may be determined according to the allowable range of offset of the clock signal of the system that utilizes the clock signal. In this determination, information regarding the position of the bit where the communication error has occurred may be used to discriminate the cause of the communications error. [0046

There may be two causes of the occurrence of the communication errors: a communication noise and a clock signal error. If a communication noise is the cause, errors may occur equally for any bit of the received bit string.

[0047] On the other hand, if the clock signal error is the cause, synchronizing between the reception signal and the clock signal generation device 21 at the receiver side will be offset accumulatively. Therefore, errors are least likely to occur in the start bit that is initially received, and the more rearward position the bit resides in, the more likely the error is to occur. Therefore, it is possible to highly accurately identify the cause of occurrence of communication error by employing statistical methods based on the positions of the bits where the error has occurred.

Second Embodiment [0048] In a second embodiment, the cause of the bit inconsistency or the origin of the clock signal error may be identified by using majority decision, based on the reception signal of a serial communication from a plurality of transmitters. By receiving signals from a plurality of transmitters that utilize clock signal generation devices independent from one another and examining offsets therebetween, it is possible to identify an abnormal clock signal by majority decision.

The configuration of the device in this case is shown in Figure 2.

[0049] For example, a case will be discussed in which, as a result of receiving signals from a transmitter la and a transmitter lb and examining the clock signal offset by a receiver, no clock signal error is detected in the signal from the transmitter la while an error is detected in the signal from the transmitter lb. In this case, since it is determined that the speed of the clock signal of the transmitter la and the receiver is the same, and only the transmitter lb has a different speed, it can be determined by majority decision that the clock signal error has occurred in the transmitter lb. [0050J Moreover, it is possible to determine that the clock signal error is occurring in the receiver when clock signal errors are detected in both of signals of the transmitters la and lb. The receiver 2, when receiving serial communications from a plurality of transmitters la, lb. -, performs clock signal error detection by clock signal error detection device 23 using respective communications. Based on the result of the error clock signal detection, an error clock signal identifying device 24 identifies the clock signal in which an error has occurred by majority decision.

[0051] In the above-described system, although it is assumed that the failure rates of clock signal generation devices are the same, where the failure rates of the clock signals are different from each other, those clock signals in which the errors have occurred may be identified in accordance with the failure rate.

[0052] For example, it is assumed that the failure rate of the clock signal generation device 11 of the transmitter 1 is very low as compared to the receiver 2. In this case, when the receiver 2 uses the communications from the transmitter 1 to detect the clock signal errors, the receiver 2 can determine that it is highly possible that its own clock signal generation device 21 has failed.

[0053] Also, in the case where majority decision is performed by using a plurality of transmitters, evaluation may be weighted based on the failure rate to identify the clock signal in which an error has occurred.

A flowchart of a clock signal error detection where evaluation based on the failure rate is weighted is shown in Figure 5.

10054] The procedures until the clock signal error is detected (S500 to S505) are the same as those of the first embodiment.

When an error is detected, evaluation is weighted based on the failure rate of each clock signal (S506), and a clock signal in which an error has occurred is identified (S507) [0055] Where no clock signal is identified, serial communications sent from one or more of the transmitters are continuously received to perform clock signal error detection. When an error clock signal is identified, an alert is output. In this case, the alert may include information on the clock signal in which the error is occurring.

[0056] To calculate a failure rate used on identifying, by the error clock signal identifying device 24, clock signals in which an error is occurring, the number of times or the frequency of occurrence of the alert in the past by the clock signal error detection may be recorded as a history. The history may be recorded by each individual receiver, or all alerts output by the receivers may be controlled in a centralized manner. Or instead, a value ensured by a manufacturer of the device may be used as an index value of failure rate of the clock signal generation device.

Industrial Applicability

[0057] By detecting with high accuracy an error of a clock signal used in a control system in which security is important, such as a train control system, a motor vehicle control system, and an elevator control system, the device of the present invention can securely stop or recover the system, even when an error occurs.

Reference Signs List [0058] 1 transmitter 2 receiver 3 network 11 clock signal generation device 12 serial communication transmission device 21 clock signal generation device 22 serial communication receiving device 23 clock signal error detection device 24 error clock signal identifying device S300 serial communication receiving procedure S30l reception signal reading procedure S302 bit value consistency examination procedure S303 bit value inconsistency examination procedure S400 serial communication receiving procedure S40l reception signal reading procedure 5402 bit value consistency examination procedure S403 bit value inconsistency examination procedure S404 bit value inconsistency cause identifying procedure S405 clock signal error presence examination procedure S500 serial comunication receiving procedure S501 reception signal reading procedure S502 bit value consistency examination procedure S503 bit value inconsistency examination procedure S504 bit value inconsistency cause identifying procedure S505 clock signal error presence examination procedure S506 procedure for weighting evaluation based on a failure rate S507 procedure for examining capability of identifying an error in a clock signal