GB2490546A

GB2490546A - Semiconductor structure

Info

Publication number: GB2490546A
Application number: GB1107574.4A
Authority: GB
Inventors: Vishal Ajit Shah; Maksym Myronov
Original assignee: University of Warwick
Current assignee: University of Warwick
Priority date: 2011-05-06
Filing date: 2011-05-06
Publication date: 2012-11-07
Also published as: WO2012153112A2; GB201107574D0; WO2012153112A3

Abstract

A semiconductor structure 27 comprises a frame for example silicon 29 provided by a monocrystalline substrate (1, Figure 4a) comprising a first patterned semiconductor material 28 and having a window passing through the substrate between first and second opposite surfaces of the substrate; and a monocrystalline free-standing membrane 30 for example, germanium, Ge, is formed over the window provided by a layer 5 grown at a low temperature which is under compressive strain and supported directly on the surface of the substrate. Alternatively, ( Figure 4c) a free-standing germanium membrane (25, Figure 4c) is under tensile strain at high temperature and is supported by a silicon frame (24, Figure 4c).

Description

Semiconductor structure

Description

The present invention relates to a semiconductor structure, particularly, but not exclusively, to a semiconductor structure comprising a germanium membrane supported on an etched silicon substrate.

Silicon membranes can be fabricated by etching a (001) orientated silicon wafer using a wet anisotropic etchant, such as potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH) or e thylenediamine pvrocatechol (EDP), and using etch stop and masking layers comprising a dielectric, such as silicon dioxide (Si02) or silicon nitride (Si3N4), or doped silicon. Reference is made to "The Fabrication of Thin, Freestanding, Single-Crystal INiembranes", by K. C. Lee, and Journal of the Electrochemical Society, volume 137, number 8, pages 2556 to 2574 (1990) and to "Etch stop techniques for micromachining", by S.D. Collins, Journal of the Electrochemical Society, volume 144, number 6, pages 2242 to 2262 (1997).

"Germanium as a versatile material for low-temperature micromachining", B. Li et al., Journal of Microelectromechanical Systems, volume 8, number 4, pages 366 to 372 (1999) describes deposition of polycrystalline and amorphous germanium films using low-pressure chemical vapour deposition at temperatures of 325 °C and 300 °C respectively. The document describes the behaviour of stress in 500 nm thick polycrystalline and amorphous germanium films formed on (100) orientated silicon wafers having a 500 nm thick layer of silicon dioxide. The polycrystalline and amorphous germanium films exhibit compressive stress, although the stress can be relaxed by using a rapid thermal anneal at 600 °C. This document also shows a micrograph of a 500 nm thick germanium membrane.

The present invention seeks to provide a semiconductor structure having an improved membrane.

According to a first aspect of the present invention there is provided a frame provided by a monocrystalline substrate comprising a first semiconductor material and having a window passing through the substrate between first and second opposite surfaces of the substrate, and a monocrystalline membrane disposed over the window provided by a layer which is supported directly on the first surface of the substrate, the layer comprising a second, different semiconductor material which is under tensile strain.

This can allow membranes comprising, for example single-crystal germanium (Ge) and other, less commonly-used semiconductor materials, to be formed.

The first semiconductor material may be silicon, e.g. (001)-orientated silicon. The second semiconductor material may comprise germanium.

The first semiconductor material may have a relaxed lattice constant a1 and the second semiconductor material may have a relaxed lattice constant a2, and the second semiconductor material in the layer may have a strained lattice constant a2' in the plane of the layer such that a2' > a2. The value of (a1 -a2D/(a1 -a2) may be no more than 1.1 or no more than 1.05.

The layer may have a thickness of at least 2 nm, at least 5 nm, at least 10 nm or at least 20 nm. The layer may have a thickness no more than 1 pm, no more than 2 pm, no more than 5 pm or no more than tO pm.

The layer may be a first layer and the semiconductor structure may further comprise a second layer disposed on the second surface of the substrate, the second layer having a window passing through the second layer between first and second opposite faces of the second layer. Thus, the second layer may be used as a mask to etch the substrate and form the window through the substrate aligned to the window in the second layer.

The first and second layers may comprise the same material, such as germanium.

The second layer may be under compressive strain. The first and second layers may have different dopants and/or different dopant concentrations.

The semiconductor structure may further comprise at least one further layer disposed on the layer over the window. Thus, the layer may provide a substrate on which a layer structure can be formed and can provide a platform on which to fabricate devices.

One or more of the at least one further layer may comprise a polycrystalline or amorphous layer of semiconductor material, such as the second semiconductor material (i.e. the same material as the membrane). The further layer may be directly in contact with the layer.

The layer and/or the at least one further layer may be configured to provide at least one functional device. The at least one functional device may include at least one electronic device, at least one photonic device, at least one spintronic device and/or other form of device. The layer and/or the at least one further layer may be configured to provide an integrated circuit.

According to a second aspect of the present invention there is provided a frame provided by a monocrystalline substrate comprising a first semiconductor material and having a window passing through the substrate between first and second opposite surfaces of the substrate and an amorphous membrane disposed over the window provided by a layer which is supported directly on the first surface of the substrate, the layer comprising a second, different semiconductor material which is under tensile strain.

According to a third aspect of the present invention there is provided a method of forming a semiconductor structure comprising providing a monocrysr2lline substrate having first and second opposite surfaces and comprising a first semiconductor material, forming a monocrystalline layer directly on the first surface of the substrate, the layer comprising a second, different semiconductor material which is under tensile strain and forming a window passing through the substrate between first and second opposite faces of the substrate so as to provide a membrane over the window.

The first semiconductor material may be silicon, e.g. (001)-orientated silicon. The second semiconductor material may comprise germanium. The layer may be deposited, for example, using chemical vapour deposition, at a temperature of at least 500 °C, at least 550 °C, at least 600 °C or at least 650 °C. The layer may be deposited at a temperature no more than 700 °C. The temperature may be no more than the lower of the melting temperature of the first semiconductor and the melting temperature of the second semiconductor material or no more than 10 °C below the lower of the melting temperature of the first semiconductor and the melting temperature of the second semiconductor material.

The method may comprise depositing a first part of the layer at a first temperature and depositing the rest of the layer at a second, different temperature. The second temperature is preferably higher than the first temperature. Depositing part of the layer at a lower temperature can help to provide a smooth surface for subsequent deposition of the rest of the layer at a higher temperature and/or can help to reduce the number of dislocations. The first temperature may be no more than 400 °C, no more than 450 °C or no more than 500 °C. The second temperature may be at least 550 °C, at least 600 °C or at least 650 °C. The second temperatures may be no more than the lower of the melting temperature of the first semiconductor and the melting temperature of the second semiconductor material or no more than tO °C below the lower of the melting temperature of the first semiconductor and the melting temperature of the second semiconductor material. The method may further io comprise, after depositing the layer, annealing the layer at a temperature of at least 700 °C, at least 750 °C or at least 800 °C, and/or below 900 °C. The annealing temperatures may he no more than the lower of the melting temperature of the first semiconductor and the melting temperature of the second semiconductor material or no more than 10 °C below the lower of the melting temperature of the first semiconductor and the melting temperature of the second semiconductor material.

Forming the window may comprise etching the substrate. For example, etching the substrate may comprise wet etching the substrate using an etchant comprising, for instance, potassium hydroxide or tetramethylammonium hydroxide. The substrate may be etched by dry etching.

The method may comprise amorphising some or all of the layer so as to provide an amorphous membrane over the window.

Certain embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings in which: Figures Ia to lc illustrate steps during fabrication of a layer structure; Figure 2 is a schematic diagram of a chemical vapour deposition reactor; Figure 3 is a cross-sectional transmission electron micrograph of a layer structure; Figures 4a to 4c show steps during fabrication of a membrane in a first semiconductor structure; Figure 5 illustrate a second semiconductor structure; Figure 6 is an optical micrograph of the second semiconductor structure shown in Figure 5 using differential interference contrast; Figure 7 is an optical micrograph of the first semiconductor structure shown in Figure 4c without using differential interference contrast; Figure 8 is an optical micrograph of the first semiconductor structure shown in Figure 4c using differential interference contrast; Figure 9 is a scanning electron micrograph of the first semiconductor structure shown in Figures 8 and 9 after having been intentionally broken; Figure 10 is scanning electron micrograph of the first semiconductor structure having been intentionally broken; and Figure II is a schematic diagram of a device formed on the first semiconductor structure.

Referring to Figure Ia, a 4-inch diameter, low-resistivity (10-25 Qcm) double-sided polished wafer 1 having a thickness, t1, of 325 ±25 tm is shown. The wafer 1 has first and second opposite surfaces or "sides" 2, 3, herein referred to as CCtopside and "backside" respectively.

Referring also to Figures Ib, Ic and 2, a set of wafers 1 is provided for growing first Jo and second layers 4, 5 of germanium on the first and second sides 2, 3 respectively of each wafer 1 and form a layer structure 6. The wafers I are placed in an ASM Epsilon 2000 reactor 7 for reduced pressure chemical vapour disposition (RPCVD) of germanium using germane (GeH4) as a precursor gas. The layers 4, 5 are grown separately at different temperatures, in this example, at 670 °C and 400 °C. This results in the first and second germanium layers 4, 5 having different mechanical properties.

As shown in Figure 2, the reactor 7 includes a quartz tube 8 into which susceptors 9 (only one is shown) carrying the wafers I can be placed via a load lock (not shown).

The wafers 1 are heated from above by a first, upper lamp arrangement 10 and from below by a second, lower lamp arrangement 11. Temperatures of the wafers I and susceptors 9 are monitored using thermocouples (not shown). Precursor gas 12 is introduced through an injector flange (not shown) and flows through the tube 8, over the wafers I. The flow rate of precursor gas 12 is monitored using a mass fio\v meter (not shown). Growth product gases 13 flow out through an exhaust flange (not shown).

Prior to growth, the native oxide (not shown) on each \vafer I is desorbed by heating the wafers Ito 1100 °C for 90 seconds.

Referring in particular to Figure lc, the first germanium layer 4 (which is grown at relatively high temperature) is grown on the topside 2 of the wafer I before the second germanium layer 5 is grown on the backside 3 of the wafer at relatively low temperature.

The first layer 4 of germanium is grown in two steps. First, a layer 4A of germanium having a thickness, t2A, of 100 nm is grown at 400°C. Then, a layer 4B of germanium having a thickness, t2B, of 600 nm is grown at 670 °C, thus forming a layer 4 having a total thickness, t t + t, of 700 nm. The first layer 4 is annealed at 830 °C for minutes.

The resulting layer structure 6' is allowed to cool to room temperature. The layer structure 6' is then unloaded from the reactor 7, turned over and re-loaded into the reactor 7. This process is carried out in a dry nitrogen atmosphere in less than 15 minutes so that no native oxide is formed. This means that there is no need to desorb any native oxide prior to growing the second layer 5.

The second germanium layer S having a thickness, t3, of 700nm is grown at 400 °C.

Cross-sectional transmission electron microscopy (XTEM) is carried out on the resulting layer structure 6 in a (000) diffraction condition at 200 kV using a JEOL 2000FX TEM (not shown). This is used to confirm crystallinity of the germanium layers 4, 5, to view dislocation arrangement and also to confirm layer thicknesses.

Figure 3 is a composite cross-sectional transmission electron micrograph of the layer structure 6. Both germanium layers 4, 5 are fully monocrystalline.

Relaxation and composition of the germanium layers 4, S is determined by X-ray diffraction (XRD) using a Philips X'pert MRD Pro single crystal high resolution x-ray diffractometer (not shown). Reciprocal space mapping (RSM) is performed along the symmetrical (004) and asymmetrical (224) orientations, which allows in-and out-of-plane lattice parameters to be calculated.

The first germanium layer 4, i.e. the germanium layer grown at high temperature, is calculated to have a relaxation of 104.2±0.5 o,/ compared to the (001) sihcon substrate, i.e. to be under slight tensile strain. Without wishing to be bound by any particular theory, this can be attributed to a difference in thermal expansion between germanium and silicon. Silicon has a lattice constant a1 of about 5.43 A at 300 K and a hnear coefficient of thermal expansion x of about 2.6 x 106 IC.

Germanium has a lattice constant a2 of about 5.65 A at 300 K and a hnear coefficient of thermal expansion °b of about 5.8 x 106 IC1.

The second germanium layer 5, i.e. the germanium layer grown at low temperature, is calculated to have a relaxation of 97.1±0.5 % i.e. to be under slight compressive strain.

The layer structure 6 can he used to form first and second semiconductor structures 26 (Figure 4c), 27 (Figure 5), each comprising a free-standing portion of the germanium layer (herein referred to as a germanium cmembrane) supported by an etched silicon wafer.

In the first semiconductor structure 26 (Figure 4c), the germanium membrane is formed from germanium grown at high temperature and is under tensile strain. In the second semiconductor structure 27 (Figure 5), the free-standing germanium membrane is formed from germanium grown at low temperature and is under compressive strain.

The first and second semiconductor structures 26 (Figure 4c), 27 (Figure 5) are fabricated in a similar way using the same processes, namely by patterning one of the germanium layers 4, 5 to form an etch mask and using a highly-selective etchant to etch through the silicon wafer I to the other germanium layer 4, 5.

The fabrication processes will now be described using fabrication of the first semiconductor structure 26 (Figure 4c) as an example: Referring to Figure 4a, an etch mask in the form of a layer 15 of chemically-resistive Apie2on Wax W is applied to the surface 16 of the second germanium layer 5 leaving an area 17 of the surface 16 unmasked. The unmasked area 17 is square in plan view and has dimensions of about 1 mm by about 1 mm.

An unmasked region 18 of the second germanium layer S is removed using a selective etch (not shown) comprising a mixture of HF:I-T202:CH3COOH in a ratio 1:2:3 for 30 seconds at a temperature of 19±1 °C. Germanium is etched at a rate of 4 am min1 and silicon is etched at a rate of about I nm min'. Thus, the etchant reaches the surface 2 of the silicon substrate 1. The etched structure 19 is cleaned using de-ionised water.

io Figure 4b shows the resulting etched structure 19 comprising a patterned second germanium layer 20 which reveals an area 21 of underlying silicon 1.

-10 -The Apiezon Wax W is removed using toluene solvent and ultrasonic agitation. The surface of patterned germanium layer 20 and the exposed silicon substrate 21 is cleaned using another (clean) toluene dip, followed by an acetone rinse and dried using a jet of dry nitrogen gas.

An unmasked region of silicon 22 is removed by a deep, anisotropic, wet chemical etch (not shown) comprising a 30% solution of KOH for 100 minutes at 100±2 °C using a flow cell (not shown) arranged to keep mildi-turbulent, unreacted etchant flowing over the sample and so minimise surface roughness. The flow rate of etchant hes between about 0.4 to 4 ml min1. Silicon is etched at a rate of about 3.7 m min1 and crystalline germanium is etched at about 4 nm min. Thus, the etchant reaches the substrate side 23 of the first germanium layer 4. This results in a sihcon frame 24 which supports the germanium layer 4 leaving a free-standing region 25 (i.e. a membrane) of germanium which is under tensile strain. The etched structure 26 is cleaned using de-ionised water.

Referring also to Figure 5, the same processes are used to fabricate the second semiconductor structure 27. However, in this case, the first germanium layer 4 is patterned to form a patterned layer 28. Etching results in a silicon frame 29 which supports a free-standing region 30 (i.e. a membrane) of germanium which is under compressive strain.

The same fabrication processes yields different results in the first and second semiconductor structure 26, 27.

Figure 6 is an optical micrograph of the second semiconductor structure 27 (Figure 5) using differential interference contrast.

As shown in Figure 6, the germanium membrane 30 exhibits short-range ripples 31, io large-scale ripples 32 and cracks 33. The short-range ripples 31 appear to have an amplitude of the order of 10 nm to 100 nm since they are not visible when differential interference contrast is not used. The difference in focal distance between the surface of the short-range ripples 31 and the largest of the large-scale -11 -ripples 32 is of the order of about 20 pm. The cracks 33 indicate that the germanium membrane is not fully supported on all sides.

Figures 7 and 8 are optical micrographs of the first semiconductor structure 26 (Figure 4c) respectively with and without differential interference contrast.

In Figure 7, no short-range ripples and no cracks are seen. In Figure 8, no short-range ripple, long-range ripples or cracks are observed.

The first semiconductor structure 26 (Figure 4c) can be cleaved to allow it to be viewed in a scanning electron microscope (not shown).

When the semiconductor structure 26 (Figure 4c) is cleaved, the semiconductor layer 4 (Figure 4c) breaks away from the edges of the wafer support 24 (Figure 4c).

Nevertheless, fragments of the membrane 25 can be viewed to determine surface quality and residual thickness of the membrane 4 (Figure 4c).

Figure 9 is a scanning electron micrograph of fragments 34 of the membrane 25 when attached to an SEM stub (not shown) with etched side face up. An outline 35 of the membrane 25 is highlighted in chain Figure 10 is a micrograph at higher magnification showing the side profile of a membrane fragment 36. The membrane thickness appears to be about 600 to 700nm.

As shown in Figure 10, the etched surface 36 of the membrane fragment 34 is generally smooth. A few etch islands 37 having sub-micron lateral dimension can be seen. However, the height of these islands is much less than the thickness of the membrane.

Membranes under tensile strain can be used as a substrate for circuits, as will now be described in more detail.

-12 -Referring to Figure 11, a single-crystal membrane 37 provided by a layer 38 comprising a semiconductor material under tensile strain is shown. In this example, the semiconductor material is germanium. The membrane 37 is formed over a window 39 which passes through a single-crystal substrate 40 between top and bottom sides 41,42 of the substrate 40. In this example, the substrate 40 comprises silicon. The germanium layer 38 is supported directly on the top side 41. The window 39 is defined using a germanium etch mask 43 and can be fabricated using a similar process to that hereinbefore described.

A device, such as metal-oxide-semiconductor field-effect transistor (MOSFET) 44, can be formed in and on the membrane 37. Thus, in the case of a germanium membrane, a germanium MOSFET can be formed.

A thin (e.g. a few nanometres) gate dielectric layer 45 is disposed on the substrate 40. For a germanium MOSFET, the gate dielectric may comprise, for example, zirconium oxide (Zr02) which may be deposited by sputtering. However, other dielectric materials, such as silicon dioxide (SiC2) or hafnium oxide (Hf02), and other deposition processes, such as CVD or atomic layer deposition (ALD), may be used. The gate dielectric layer 45 separates the substrate 40 from a gate electrode 46. The gate electrode 46 may comprise a semiconductor material, a metal or other conductive material, such as tantalum nitride (TaN). As shown in Figure 11, a self-aligned diffusion process can be used to form doped well regions 47,48 which provide source and drain regions. A channel region 49 is formed under the gate dielectric 44 between the source and drain regions 47, 48.

It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

Materials other than germanium and silicon can be used. For example, first and second semiconductor materials can be used for the substrate and tensile strain layer respectively which have the same or similar crystal structure, such as diamond cubic, and having respective relaxed lattice constants, a1, a2 such that a1 <a2 or a1 > a2 (similar to the case for silicon and germanium) at room temperature, but as a result -13 -of the growing the layer on the substrate, the substrate changes the in-plane lattice parameter a2' for the grown layer such that a2' > a2 at room temperature.

An elemental semiconductor material for the layer under tensile strain (or for the layer under compressive strain) need not be used. Instead, a semiconductor alloy material may he used. For example, silicon germanium (Si1 Ge; where 0 < x < 1) can he used.

The wafer can have other diameters, e.g. smaller or larger, and thicknesses, e.g. small or larger. The wafer can have an orientation other than (001) can be used, such as (Ill). The wafer can he a composite wafer.

Other forms of chemical vapour deposition can he used, such as plasma-enhanced chemical vapour deposition (PECVD), atmospheric pressure chemical vapour deposition (APCVD) etc. A chemical vapour deposition process need not be used.

For example, molecular beam epitaxy (MBE) or atomic layer deposition (ALD) process may he used.

Other precursor gases, such as germanium tetrachloride (GeCl4), may be used.

Layers can he deposited which are doped, e.g. n-type or p-type, having a doping concentration in the range of between about I x 1016 cm3 and I x102° cm3 or more.

Doping need not he uniform. For example, the layers can be grown such that doping concentration varies \vith layer thickness.

Thicker or thinner layers can be grown. For example, the layer can have a thickness of a few monolayers or a few tens of monolayers. The layer can have a thickness of at least 5 nm, at least 10 nm, at least 20 nm, at least 50 nm, at least 100 nm, at least nm, at least 500 nm or at least I p.m or more.

Waxes need not be used to define the etch mask. Other materials, such as resists, and processes, such as lithography and dry etching, can be used to pattern, e.g. a germanium (mask) layer.

-14 -Other wet etching systems can be used, such as an etch bath.

Other wet etchants can he used. Dry etching, such as reactive ion etching or ion-beam milling, can be used. An etch need not be selective or have high selectivity.

Tn the case of etch which is not selectively or does not has high selectivity, a sufficiently calibrated etch can be used.

The substrate need not be a wafer, but can be a wafer die or chip.

Some or all of a monocrystalline layer providing a membrane may be amorphorised, for example by ion implantation, after the layer is deposited and, optionally, after the membrane is formed.

The membrane can provide a base or platform for devices. To fabricate such devices, one or more layers can be deposited on the membrane and suitably patterned.

A polycrystalline or amorphous layer may be deposited on some or all of a monocrystalline layer providing the membrane after it is formed. Thus, a mixed form of membrane comprising a monocrystalline base and a polycrystalline or amorphous top can be formed.

Other non-semiconductor material layers can be deposited (or formed) on some or all of the monocrystalline layer. For example, a layer may be a metallization layer or a dielectric layer.

One or more of the layers need not be an inorganic material. For example, an organic material, such as organic semiconductor material or organic dielectric Jo material may be used.

Other forms of electronic device can be formed in and/or on a membrane.

Integrated circuits comprising a plurality of devices can be formed in and/or on a -15 -membrane. Additionally or alternatively, other forms of device can be used. For example, optical devices (such as a laser, light emitting diode or modulator), photonic devices, spintronic devices and/or microelectromechanical (MEMS) or nanoelectromechanical (NEMS) devices may be formed.

The membrane need not cover the window. For example, the membrane may be patterned to form a strip (or strips) which cross the window from one side to the other. Other forms of bridging (or "spanning") structures, such as crosses, may be used. This can be used to thermally isolate structures formed on the bridging structures.

Claims

-16 -Claims 1. A semiconductor structure comprising: a frame provided by a monocrystalline substrate comprising a first semiconductor material and having a window passing through the substrate between first and second opposite surfaces of the substrate; and a monocrystalline membrane disposed over the window provided by a layer supported directly on the first surface of the substrate, the layer comprising a second, different semiconductor material which is under tensile strain.
2. A semiconductor structure according to claim t, wherein the second semiconductor material is germanium.
3. A semiconductor structure according to claim I or 2, wherein the first semiconductor material is silicon.
4. A semiconductor structure according to any preceding claim, wherein the first semiconductor material has a relaxed lattice constant a1 and the second semiconductor material has a relaxed lattice constant a2 and wherein the second semiconductor material in the layer has a strained lattice constant a2' in the plane of the layer such that a2' > a2.
5. A semiconductor structure according to claim 4, wherein (a1 -a2D/( a1 -a2) is no more than 1.1 and, optionally, no more than 1.05.
6. A semiconductor structure according to any preceding claim, wherein the layer has a thickness of at least 2 nm.
7. A semiconductor structure according to any preceding claim, wherein the layer has a thickness of at least 10 nm.
8. A semiconductor structure according to any preceding claim, wherein the layer has a thickness of at least 20 nm.

-17 -
9. A semiconductor structure according to any preceding claim, wherein the layer has a thickness no more than 10 Ism.
10. A semiconductor structure according to any preceding claim, wherein the layer is a first layer and the structure further comprises: a second layer disposed on the second surface of the substrate, the second layer optionally having a window passing through the second layer between first and second opposite faces of the second layer.
ii. A semiconductor structure according to claim tO, wherein the first and second layers comprise the same material.
12. A semiconductor structure according to claim 11, wherein the second layer is under compressive strain.
13. A semiconductor structure according to claim tI or 12, wherein the first and second layers have different dopants and/or different dopant concentrations.t4. A semiconductor structure according to any preceding claim, further comprising: at least one further layer disposed on the layer over the window.15. A semiconductor structure according to claim 14, wherein the layer and/or the at least one further layer configured to provide at least one functional device.16. A semiconductor structure according to claim t4 or 15, wherein one of the at least one further layer comprises a polycrystalline or amorphous layer of semiconductor material, optionally, the second semiconductor material.t7. A semiconductor structure according to claim t6, wherein the one further layer is directly in contact with the layer.-18 - 18. A semiconductor structure according to any one of claims ISto 17, wherein the at least one functional device includes at least one electronic device.19. A semiconductor structure according to any one of claims 15 to 18, wherein the at least one functional device includes at least one optical and/or photonic device.20. A semiconductor structure according to any one of claims 15 to 19, wherein the at least one functional device includes at least one spintronic device.21. A semiconductor structure according to any one of claims 15 to 20, wherein the at least one functional device includes at least one microelectromechanical system and/or nanoelectromechanical systems device.22. A method of forming a semiconductor structure comprising: providing a monocrystalhne substrate having first and second opposite surfaces and comprising a first semiconductor material; forming a monocrystalline layer directly on the first surface of the substrate, the layer comprising a second, different semiconductor material which is under tensile strain; and forming a window passing through the substrate between first and second opposite faces of the substrate such that the layer provides a membrane over the window.23. A method according to claim 22, wherein the second semiconductor material is germanium.24. A method according to claims 22 or 23, wherein the first semiconductor material is silicon.25. A method according to any one of claims 22 to 24, further comprising annealing the monocrys talline layer.-19 - 26. A method according to any one of claims 22 to 25, wherein forming the window comprises etching the substrate.27. A method according to claim 26, wherein etching the substrate comprises wet etching the substrate using an etchant.28. A method according to claim 27, wherein the etchant comprises potassium hydroxide.29. A method according to claim 27, wherein the etchant comprises tetramethylammonium hydroxide.30. A method according to any one of claims 22 to 29, wherein etching the substrate comprises dry etching the substrate.