GB2481687A - Diamond composite substrate for semiconductor devices - Google Patents

Abstract

A composite substrate or a method of manufacturing a composite substrate comprising polycrystalline diamond layer 12 bonded to single crystal silicon or silicon carbide cleaved layer 14 which is 15mm or less in thickness. Polycrystalline diamond layer 12 (50mm to 150mm thick) is grown by Chemical Vapour Deposition (CVD) at 700°C to 1200°C on single crystal silicon or silicon carbide wafer 10 0.3mm to 2.0mm thick. A strain field to enable cleavage is generated in wafer 10 by heating or cooling. Cleavage may be triggered by mechanical force (e.g. using a knife blade), thermal shock or wafer 10 may cleave automatically during heating/cooling due to mismatch in the thermal expansion coefficient between the silicon/silicon carbide and the polycrystalline diamond. Wafer 10 may be treated to promote cleavage by forming a buried oxide damage layer, implanting a weakened cleave plane or forming nanostructured surface pits. Wafer 10 may be reused to grow further diamond substrates. A semiconductor material 16 may be epitaxially grown on a buffer layer over a planarised surface of cleaved layer 14 to form a semiconductor device e.g. thin film transistor, diode or high power switching device.

Description

SUBSTRATES FOR SEMICONDUCTOR DEVICES

Field of Invention

The present invention relates to the manufacture of substrates for semiconductor devices.

Background of Invention

Optoelectronic, high power, and high frequency devices are increasingly being fabricated using wide band gap compound semiconductor materials such as gallium nitride, aluminium nitride, and silicon carbide. Such semiconductor materials are frequently grown heteroepitaxially in thin film form onto a suitable substrate which provides a lattice matched template for crystal growth. Typical substrates include sapphire, silicon carbide, and silicon. For semiconductor devices such as microwave amplifier circuits, the substrate should be electrically insulating for the device to function.

A well known problem in semiconductor devices is that of heat dissipation. High temperatures often limit the performance and/or lifetime of such devices. This is a particular problem in semiconductor devices which operate at high power and/or high frequency such as microwave amplifiers, power switches and optoelectronic devices.

II is therefore desirable to be able to spread any heat generated by component devices to reduce temperatures and thus improve device performance, increase lifetime, and/or increase power density. Accordingly, it is desirable to utilize a substrate material with a high thermal conductivity to spread the heat generated by a device, lowering the power density and facilitating dissipation via a heat sink thus improving device performance, increasing lifetime, and/or enabling an increase in power density.

Diamond has unique properties as a heat spreading material, combining the highest room temperature thermal conductivity of any material, with high electrical resistivity and low dielectric loss when in an intrinsic undoped form. Thus diamond is utilized as a heat spreading substrate for semiconductor components in a number of high power density applications. The advent of large area polycrystalline diamond produced by a chemical vapour deposition (CVD) technique has expanded the applications for diamond heat spreaders via an increase in area and a reduction in cost. The majority of favourable thermal, dielectric and insulating properties of diamond are not dependent on the single crystal structure of naturally occurring or synthetic single crystal diamond material. Accordingly, polycrystalline CVD diamond wafers have been developed and are commercially available in sizes that enable them to be directly integrated with the fabrication processes of wide band gap semiconductors as a substrate material.

In light of the above, it is evident that for thin film compound semiconductor materials, an ability to integrate diamond as a carrier substrate could greatly improve thermal performance. For high power devices, the challenge is to position an active region of a device in as close proximity as possible to the heat spreading diamond substrate, since any intermediate carrier substrate material such as sapphire, silicon, or silicon carbide acts as a thermal barrier.

Compound semiconductor materials can be grown directly on a polycrystalline diamond substrate using, for example, a metal organic vapour phase epitaxy (MOVPE) technique. However, semiconductor material grown in such a manner will itself be polycrystalline, the crystals being distributed over a range of crystallographic orientations relative to the plane of the substrate. Such a polycrystalline layer of semiconductor material will tend to have relatively low charge mobility and thus will not provide good device performance for many proposed applications, particularly those which require high charge (electron and/or hole) mobility characteristics such as a high electron mobility transistor (HEMT) used in microwave frequency amplifier circuits. As such, it is desirable to provide a method which allows the formation of a monocrystalline semiconductor layer.

US 7,595,507 and US 2010/000 1293 disclose methods of forming semiconductor device substrates which comprise growing diamond over a monocrystalline silicon carbide layer. US 2009/0272984 also discloses a method of forming a semiconductor device substrate comprising diamond and silicon carbide. Such composite diamond-silicon carbide substrates can be used to form semiconductor devices. When forming such devices, the mono-crystalline silicon carbide layer can be used to grow a monocrystalline semiconductor layer thereover.

US 2006/0113545 discloses substrate structures comprising silicon-diamond-silicon multilayer structures. While silicon is much cheaper than silicon carbide, one problem with using silicon is that it offers relatively poor thermal and resistivity properties compared to silicon carbide. As such, it is desirable to make the silicon layer very thin.

US 7,695,564 discloses a method for fabricating a thermal management substrate having a thin silicon layer on a polycrystalline diamond film. The method comprises ion-implantation of oxygen into a silicon wafer to form a wafer comprising a bulk silicon wafer layer of an unspecified thickness, a buried oxide layer having a thickness of approximately 100-200 nm, and a silicon overlay structure having a thickness of 50-500 nm. A polycrystalline diamond film of approximately 200 to 1500 micrometers is grown on the silicon overlayer. The bulk silicon wafer layer and the buried oxide layer are then removed to leave a composite structure comprising the polycrystalline diamond film and the silicon overlayer. The polycrystalline diamond film is also mechanically polished to improve wafer flamess.

A number of different methods are described for removing the silicon to form a diamond substrate with a thin silicon overlayer including: (1) selectively dissolving the buried oxide layer; (2) wet etching the bulk silicon layer; (3) lapping and polishing the bulk silicon layer followed by wet etching; (4) lapping and polishing the bulk silicon layer followed by dry etching; (5) wet etching of the buried oxide layer; (6) Chemical Mechanical Polishing (CMP). The finished silicon-on-diamond substrate consists of an approximately 50 to 200 nm thick monocrystalline silicon film which is epitaxially fused to an approximately 300 to 1500 micrometer thick polycrystalline diamond substrate.

One problem with the method described in US 7,695,564 is that the proposed silicon removal techniques can be time consuming and/or difficult to control in order to provide a very thin layer of monocrystalline silicon over the polycrystalline diamond substrate. The thin layer of monocrystalline silicon can be subject to polishing damage, cracking, and/or delamination such as via peeling.

WO 2006/100559 discloses another method of fabricating a thermal management substrate having a thin silicon layer on a polycrystalline diamond film. The method comprises providing a wafer of silicon including at least one surface suitable for use as a substrate for CVD diamond synthesis. A layer of CVD diamond of predetermined thickness is grown on the silicon wafer. The thickness of the silicon wafer is then reduced to a predetermined level, providing a surface that is suitable for synthesis of a semiconductor layer. It is taught that the CVD diamond layer is greater than 100 1tm, preferably greater than 300 1tm, more preferably greater than 400 1tm, more preferably greater than 500 jim, and most preferably greater than 550 tm thick. It is also taught that the thickness of the silicon wafer is reduced to less than 20 tm, less than 10 1tm, or less than 5 pm. No preference is taught for the starting thickness of the silicon wafer although a silicon wafer 2.0 mm thick is utilized in the example described in WO 2006/100559 in combination with a diamond layer having a thickness of 380 tm thick. It is taught that the reduction in the thickness of the silicon wafer may be accomplished by using lapidary techniques known in the art.

One problem with the method described in WO 2006/100559 is that known lapidary techniques for reducing the thickness of the silicon wafer can be time consuming and/or difficult to control in order to provide a very thin layer of monocrystalline silicon over the polycrystalline diamond substrate. Furthermore, the thin layer of monocrystalline silicon can be subject to polishing damage, cracking, and/or delamination such as via peeling.

It is an aim of certain embodiments of the present invention to provide a method of forming a composite silicon-polycrystalline CVD diamond substrate that has superior thermal conductivity, dielectric loss, and high resistivity properties to the alternative substrate materials. It is also an aim of certain embodiments of the present invention to at least partially avoid some of the problems discuss above in relation to prior art methods of forming composite silicon-polycrystalline CVD diamond substrates.

Summary of Invention

According to one aspect of the present invention there is provided a method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a wafer comprising single crystal silicon or silicon carbide, the wafer having a thickness in the range 0.3 mm to 2.0 mm; growing a polycrystalline diamond layer on the wafer using a chemical vapour deposition technique at a first temperature in the range 700°C to 1200°C to form a composite comprising the wafer bonded to the polycrystalline diamond layer, the polycrystalline diamond layer having a thickness in the range 50 im to 150 1im; heating or cooling the composite to a second temperature to generate a strain field in the wafer which is sufficient to enable cleavage of the wafer at a distance of tni or less from an interface with the polycrystalline diamond layer while being low enough to avoid the wafer fragmenting and/or the polycrystalline diamond layer cracking; and cleaving the wafer at a distance of 15 tm or less from an interface with the polyciystalline diamond layer to release strain energy and form a composite substrate comprising the polycrystalline diamond layer directly bonded to a cleaved layer comprising single crystal silicon or silicon carbide, the cleaved layer having a thickness of 15 tm or less.

Accordingly to a further aspect of the present invention there is provided a composite substrate for a semiconductor device, the composite substrate comprising: a layer of polycrystalline diamond; and a cleaved layer comprising single crystal silicon or silicon carbide, the cleaved layer being directly bonded to the layer of polycrystalline diamond at an interface between the cleaved layer and the layer of polycrystalline diamond, wherein the cleaved layer has a thickness of 15 1.tm or less.

Accordingly to a further embodiment of the present invention there is provided a method of manufacturing a semiconductor device comprising: providing the composite substrate as described above; and epitaxially growing a layer of semiconductor material over the cleaved layer.

Using the aforementioned method, the resultant semiconductor device structure compnses: the composite substrate as described above; and a layer of semiconductor material epitaxially grown over the cleaved layer.

The prior art discussed in the background section discloses various methods of forming a substrate structure comprising a layer of polycrystalline diamond with a thin layer of silicon or silicon carbide disposed thereon. However, it is difficult to form a very thin good quality layer of silicon or silicon carbide and prior art lapidary and etching methods can be time consuming and difficult to control in order to ensure a good quality thin film which is not subject to polishing damage, cracking, and/or delamination such as via peeling.

The present inventors have recognized that one reason why it is difficult to process the silicon or silicon carbide wafer to a thin film is that direct CVD diamond growth on a silicon or silicon carbide wafer results in the wafer being significantly strained.

This strain can make it difficult to use conventional processing techniques, such as conventional lapping or etching, to thin the wafer to form a layer having a thickness of 15 tm or less without cracking the layer and/or delaminating the layer from the underlying polycrystalline diamond. As it is desirable to provide a semiconductor device substrate in which a siliconlsilicon carbide interface layer has a thickness of 15 tm or less to allow heat to be efficiently transferred from an overlying semiconductor device to an underlying diamond substrate, this is problematic.

One possible solution to the aforementioned problem is to try and minimize the amount of strain in the wafer. However, the present inventors have developed a more ingenious solution which actually uses the strain generated during CVD polycrystalline diamond growth to achieve a thin film comprising single crystal silicon or silicon carbide on the polycrystalline diamond.

The present inventors have surprisingly found that the stress generated in the silicon or silicon carbide wafer by direct CVD polycrystalline diamond growth thereon can be used to promote cleavage of the wafer across a plane substantially parallel and close to an interface with the polycrystalline diamond layer to form a composite structure comprising the polycrystalline diamond layer directly bonded to a layer of siliconlsilicon carbide 15 1.tm or less thick. In this regard, it should be appreciated that a significant mismatch in the thermal expansion coefficient of two layers which are adhered to each other is usually considered to be problematic as it can lead to stress build up in each of the layers causing cracking in one or both of the layers and/or delamination of the layers. While efforts are usually focussed on reducing stresses caused by such thermal mismatches to avoid cracking and/or delamination, embodiments of the present invention actually use the thermal mismatch between diamond and silicon/silicon carbide in an advantageous manner to manufacture a composite substrate structure comprising a layer of polycrystalline diamond on which a thin layer of silicon or silicon carbide is disposed.

Cleavage occurs by way of crack propagation to release strain energy generated in the wafer during heating or cooling of the composite due to a mismatch in the thermal expansion coefficient of the polycrystalline diamond and the silicon/silicon carbide.

It has been found that it is possible to generate sufficient strain in the wafer near the interface with the polycrystalline diamond layer to enable cleavage close to the interface across a plane substantially parallel to the interface without causing any cracking in the polycrystalline diamond layer.

In theory, cleavage may occur by way of a single propagating crack front which extends across the entire area of the composite. Furthermore, in theory cleavage may occur across a single crystallographic plane oriented substantially parallel to an interface between the layer of polycrystalline diamond and the wafer. In practice however, cleavage tends to form a series of distinct steps propagating out from a point of cleavage origin. The steps occur when the propagating cleavage front jumps from one crystallographic plane to another crystallographic plane. This may occur, for example, due to the interface with the diamond layer not being perfectly matched with a major crystallographic orientation, due to defects or impurities in the crystal structure of the wafer, or variations in the thickness of the polycrystalline diamond layer and/or the wafer leading to slight variations in the strain field through the wafer.

Furthermore, as the cleavage front propagates across the wafer, strain energy will be released which can alter the depth at which it is energetically most favourable for cleavage to occur.

Cleavage may also occur by way of a plurality of cracks propagating across the wafer forming a series of cleaved areas. Preferably, these cleaved areas should be as large as possible and most preferably there may be only a single cleaved area corresponding to the entire area of the wafer. The cleaved areas may be equal to or greater than 0.001 cm2, 0.003 cm2, 0.01 cm2, 0.03 cm2, 1 cm2, 2 cm2, or 5 cm2.

The cleaved surface should preferably be oriented in a plane substantially parallel to the interface with the polycrystalline diamond layer. In practice, the cleaved surface may deviate slightly from being perfectly parallel to the interface. Preferably, the cleaved layer may have a surface which is within 100, 5°, 4°, 30, 2°, 1°, or 0.5° of a plane parallel to the interface with the polycrystalline diamond layer. The angle of the surface may be measured as an angle over an area of substrate from one point to another point which discounts the previously described cleavage steps which can have a larger angle over very short distances. For example, the angle can be measured between two points more than 100 jim apart, more preferable over 1 mm apart, more preferably still over 5mm apart.

The layer of silicon or silicon carbide should preferably have a thickness which is substantially uniform across the area of the composite substrate, or at least across the area on which semiconductor devices are to be disposed. In practice, there may be slight variations due to crystallographic steps and/or variations in the thickness of the polycrystalline diamond layer. Preferably, the thickness variation is equal to or less than 10 jim, 5 jim, 1 jim, 500 nm, 200 nm, 100 nm, 50 nm, or lOnm over an area greater than or equal to 1 mm2, 5 mm2, 10 mm2, 30 mm2, 100 mm2, 300 mm2, or 1000 mm2 and/or over an area greater than or equal to 50%, 60%, 70%, 80% or 90% of a total surface area of the cleaved layer. Preferably the variation in thickness is less than 20% of a mean measured thickness.

In light of the above, it will be clear that while a cleavage front wilt tend to propagate across a crystallographic plane, the cleavage front may propagate across a number of crystallographic planes. In practice, the cleave plane should be approximately parallel to the interface with the diamond layer. Tn a wafer of uniform strength, a strain field can be generated during cooling after CVD diamond growth such that cleavage is promoted at a particular distance from the diamond interface. Cleavage at this distance can be additionally promoted by inclusion of a weaker layer in the wafer.

The cleaved layer may have a surface which is preferably single crystal over a majority of a substrate area for providing a suitable surface to heteroepitaxially grow semiconductor layers thereon. For example, the cleaved layer may have a surface which is at least 80% single crystal, more preferably at least 90% single crystal, more preferably at least 95% single crystal, more preferably at least 98% single crystal, more preferably at least 99% single crystal, or most preferably 100% single crystal.

The exact location at which cleaving occurs can be controlled by selecting suitable conditions for creating a suitable cleaving force at a desired depth during deposition of the CVD diamond layer. It has been found that selecting, in combination, a wafer having a thickness in the range 0.5 mm to 2.0 mm, a polycrystalline diamond layer having a thickness in the range 50 im to 150 kim, and a temperature in the range 700°C to 1200°C during CVD growth of the polycrystalline diamond layer can create a suitable cleaving force at a depth of 15 jim or less when the composite is cooled. Tn particular, the present inventors have found that this particular combination of parameters is advantageous for generating a strain field in the wafer which is sufficient to enable cleavage at a distance of 15 jim or less from an interface with the polyciystalline diamond layer while being low enough to avoid the wafer fragmenting and/or the polycrystalline diamond layer cracking.

Embodiments of the present invention start with the provision of a wafer of material which will ultimately provide an interface between a diamond substrate layer and an overlying semiconductor device structure. That is, an interface material of silicon or silicon carbide is initially provided as a substrate on which the polycrystalline diamond is grown. The polycrystalline diamond is grown on a siliconlsilicon carbide wafer and the wafer is cleaved using stress generated during heating or cooling after polycrystalline diamond growth to form a composite structure comprising a very thin layer of single crystal silicon or silicon carbide. A semiconductive layer of material can then be heteroepitaxially grown over the single crystal silicon or silicon carbide such that the initial siliconlsilicon carbide substrate material becomes the interface layer between the diamond layer and the active semiconductor layer.

Such a method has advantages over alternative methods for manufacturing substrate and semiconductor structures. In embodiments of the present invention, the semiconductor is grown over the diamond. Accordingly, it is not required to separately grow a desired semiconductor layer on a different substrate and then transfer and adhere the semiconductor to a diamond substrate. Simultaneously, the need to form an interface layer over the polycrystalline diamond substrate and convert it by, for example, annealing into a crystallographically oriented layer, is avoided as the interface material is provided as a substantially single crystal material from the outset in the form of a single crystal substrate for diamond layer formation.

Furthermore, the interface material is automatically bonded to the diamond layer in the correct orientation during formation of the diamond layer. Additionally, a high adhesion strength between the interface material and the diamond layer can be achieved by directly growing the polycrystalline diamond on the wafer using a CVD process. Further still, rather than trying to reduce strain created during CVD diamond growth and/or provide very precisely controlled lapidary and/or etching to form a thin interface layer, embodiments of the present invention actually use the strain created during CVD diamond growth to form the thin interface layer via a cleaving mechanism. Such a technique provides a very efficient and cost effective way of manufacturing diamond substrates with a very thin layer of single crystal material thereon. In addition, using a cleaving mechanism to form the thin interface layer is advantageous as strain energy is released during cleaving such that there is little remaining strain energy in the interface layer to promote cracking. As a result, a more stable interface layer is achieved.

The wafer may be silicon or silicon carbide as recited above. While silicon is much cheaper than silicon carbide, one problem with using silicon is that it offers relatively poor thermal and resistivity properties compared to silicon carbide. As such, it is particularly desirable to make the layer very thin if silicon is used. Embodiments of the present invention are capable of forming very thin layers of silicon and thus silicon may be the preferred material for use in many embodiments of the present invention. That is, the present invention offsets the inferior thermal conductivity of silicon by allowing the formation of a very thin layer of material. Silicon is considered advantageous for use in embodiments of the present invention as it has the closest thermal expansion match to diamond, is low cost, and is compatible with CVD diamond growth. Indeed, while joining diamond to other materials is often difficult, diamond grown via CVD on silicon can exhibit high adhesion strength. As such, much of the following discussion will refer to silicon as the wafer material. However, it will be understood that the invention may also be applied to silicon carbide.

The wafer may have a thickness in the range 0.3 mm to 2.0 mm, 0.3 mm to 1.8 mm, O.3mmtol.5mm,0.3mmtol.3mm,O.3mrntol.Omm,orO.5mmtoO.8mm. The layer of polycrystalline diamond may have a thickness in the range 50 tm to 150 1tm, tm to 130 urn, 80 tm to 120 1tm, or 90 tm to 110 pm. If the diamond layer is made too thick relative to the wafer, then the wafer can break during CVD growth of the diamond layer on the silicon wafer. Conversely, if the wafer is made too thick relative to the diamond layer, then the diamond layer can break during CVD growth of the diamond layer on the wafer.

It may be advantageous to use wafers which are doped. For example, wafers can be supplied as p-type or n-type, typically with 10E13 -10E16 concentration of one of dopant. P-type dopants include boron, aluminium, and gallium. N-type dopants include phosphorous, arsenic, and antimony. The end application may prefer that the wafers are doped, or specifically undoped. Doped wafers may modify the behaviour of cleavage, in particular modify the pattern of cleavage steps to improve the subsequent semiconductor epitaxy.

The polycrystalline diamond layer may be grown using a chemical vapour deposition technique at a temperature in the range 700°C to 1200°C, 700°C to 1100°C, 700°C to 1000°C, or 700°C to 900°C. At higher temperatures, the difference in the average thermal expansion relative to room temperature between the silicon and diamond narrows. Accordingly, it can be advantageous to grow the diamond layer in a lower temperature range of, for example, 700°C to 900°C to create a larger strain field in the silicon-diamond composite when the temperature of the composite is changed by, for example, cooling to less than or equal to: 400°C; 200°C; 100°C; 50°C; or to room temperature or below.

The silicon wafer and the resultant diamond-silicon composite may be a number of different shapes. However, according to certain embodiments it is desirable to form a circular disk. The diamond-silicon composite may have a largest dimension, for example a diameter in the case of a circular disk, in the range 20 mm to 160 mm, 40 mmto l4Omm,6Ommto 120mm, 80mmto l2Ommor90mmto 110mm.

The layer of silicon remaining on the diamond after cleaving may have a thickness of tm or less, 5 jm or less, 3 tm or less, 1 m or less, 100 nm or less, or 50 nm or less. For many high power applications which generate a large amount of heat it may be desirable to form the silicon layer as thin as possible while still maintaining a substantially complete covering of crystallographically oriented silicon over the diamond surface. In order to ensure a complete covering, in practice the silicon film may be formed to have a minimum thickness of 1 nm or more, 5 nm or more, 10 nm or more, or 20 nm or more depending on processing conditions and the thickness desired for a particular end-use. Any combination of the aforementioned upper and lower limits is envisaged. For example, a silicon layer having a thickness in the range to 100 nm is considered suitable for certain high power applications and such a layer thickness can be achieved using the method of the present invention.

In relation to the above, it has been found to be advantageous to form the silicon layer to a thickness greater than 10 nm, as the first 10 nm of silicon at the diamond interface tends to be amorphous silicon carbide formed during CVD diamond growth. As such, if the wafer is cleaved at a depth less than 10 nm, the resultant film may be amorphous silicon carbide rather than single crystal silicon as desired. In this regard, it should be noted that when we refer to a silicon layer directly bonded to a CVD diamond layer, it will be understood that the interface between the silicon and the CVD diamond layer may comprise a very thin layer of amorphous silicon carbide formed during CVD diamond growth on the silicon.

As will now be understood, embodiments of the present invention provide a thin layer of single crystal silicon or silicon carbide adhered to a polycrystalline diamond substrate. The thin layer of single crystal siliconlsilicon carbide is formed by cleaving the siliconlsilicon carbide across a plane disposed substantially parallel and close to the interface with the diamond. Cleavage of the silicoiilsilicon carbide across a plane disposed close to the interface with the diamond is promoted by internal stresses which are generated during CVD diamond growth on the siliconlsilicon carbide. A thin layer of single crystal siliconlsilicon carbide remains on the diamond surface due to the strong adhesion which results from growing CVD diamond directly on the siliconlsilicon carbide.

In addition to selecting suitable layer thicknesses and controlling substrate temperature during deposition of the CVD diamond layer to create a suitable cleaving force at a desired depth, other methods may be used in combination to trigger cleaving and/or provide fine control of the exact location and orientation of the cleavage plane. Examples of such methods are discussed below.

Since the surface formed by cleaving is preferably substantially single crystal, it may be beneficial to select the cleavage plane. This is selected by the orientation of the major face of the wafer onto which the diamond is grown. This surface is preferably one of the major planes { 1 OO}, { 11 O}, { 111). in practice the orientation may differ slightly from this. Accordingly, the wafer may have a major surface oriented on the {100}, {1 1O}, or {1 1 1} plane to within 100, 50, 40, 30, 2°, 1°, or 0.5°.

For example, a silicon wafer preferentially cleaves across a { 111} crystal plane.

Accordingly, it may be advantageous to select a { 111} silicon wafer, that is one which has its { 111 crystal planes disposed in the major plane of the wafer, such that failure occurs preferentially across a { 111} plane parallel to an interface with a CVD diamond layer grown on the wafer. In practice, the major plane of the wafer may vary slightly from the { 111) crystallographic plane. Accordingly, a silicon wafer may be selected which has a major surface oriented within 100, 5° 40, 30, 2°, 1°, or 0.5° of a { 111} crystallographic plane.

Since the surface formed by the cleavage is substantially single crystal, it may also be beneficial to select the cleavage direction on the cleavage plane. The cleavage direction is preferably one of the following major crystallographic directions: <100>, <110>, <111>, <113>. The cleavage direction may in practice differ slightly from one of these orientations, by less than 100, 5°, 4°, 3°, 2°, 1°, or 0.5° . In silicon, when using the { 111} plane as the major face, the preferred cleavage direction may be the <110>. The preferred cleavage direction can be selected by choosing the point of initiation of cleavage.

Cleavage can be triggered by applying a mechanical force at a desired location for cleavage to start. For example, a force may be applied to the silicon layer in a direction parallel to the diamond-silicon interface after completion of diamond layer growth to promote cleavage at a desired depth. This acts as a trigger to initiate cleavage due to internal stresses created during CVD diamond growth.

Alternatively, a thermal shock may be applied to the composite in order to trigger cleavage. For example after cooling the composite to room temperature to generate a suitable strain field, the composite may be rapidly cooled to sub-zero centigrade temperatures to trigger cleavage using, for example, liquid nitrogen. One possibility is to apply a drop of liquid nitrogen to an edge of the composite to trigger cleavage.

Cleavage may then propagate from the point at which the drop of liquid nitrogen is applied.

Another method for controlling the exact location and orientation of the cleavage plane is to treat the siliconlsilicon carbide material which is to be located near the diamond-silicon interface to promote cleavage parallel to the diamond surface at a desired depth. For example, a top surface of the siliconlsilicon carbide wafer may be treated prior to diamond growth. The silicon/silicon carbide may be treated in a variety of different ways to promote cleave at a particular depth. The treatment may involve a mechanical, chemical, or radiation treatment of the silicon to a desired depth below the surface. For example, cleave planes can be formed via buried oxides, implantation damage, or nano-structuring of the silicon surface. Such features can be formed in the silicon prior to diamond growth.

Providing a weakened layer as a cleave plane can be utilized in conjunction with the application of a mechanical force or thermal shock to trigger cleavage in a reproducible manner to yield a very thin layer of silicon adhered to the diamond.

Alternatively, in certain embodiments cleavage occurs automatically due to strain created during CVD diamond growth during cooling after CVD diamond growth.

These in-situ cleaving embodiments can be advantageous as post processing steps are reduced saving time and cost. Furthermore, automatic in-situ lift-off of a CVD diamond plate with a thin film of the substrate wafer material adhered thereto can allow the substrate wafer to be reused to grow further diamond composites. As such, certain embodiments allow the re-use of a substrate wafer to manufacture a plurality of diamond plates having a thin silicon/silicon carbide coating. For example, the substrate wafer may be re-treated to form a further weakened cleavage plane prior to growing a new layer of CVD diamond thereon. Alternatively, the substrate wafer may be provided with a plurality of weakened cleavage planes defining a plurality of layers from the outset. The strain is optimized to peak near the interface with the CVD diamond material during growth such that only a top layer cleaves off during each CVD diamond growth run.

One or more of the aforementioned methods for triggering and controlling cleavage may be utilized.

The aforementioned methods and structures can be utilized to manufacture electronic device structures such as thin film transistors and diodes. The methods and structures of the present invention are particularly preferred for high power devices which require good thermal management, for example high power switching devices. It is a surprising result that a semiconductor device can be epitaxially grown on a cleaved surface of silicon or silicon carbide as a substrate surface would normally be carefully chemically/mechanically polished to be planarized prior to epitaxial growth. That said, embodiments of the present invention can include a processing step for planarizing the cleaved layer prior to epitaxial growth of a semiconductor device structure thereover if desired. Such a processing step may, for example, involve plasma etching to reduce step density/cleavage features. Such processing steps can more readily be performed on a thin cleaved layer without damaging the layer as strain energy is released during cleaving such that there is little remaining strain energy in the cleaved layer to promote cracking. As a result, a more stable layer is achieved.

Brief Description of the Drawings

For a better understanding of the present invention and to show how the same may be carried into effect, embodiments of the present invention will now be described by way of example only with reference to the accompanying drawings, in which: Figure 1 illustrates the basic steps involved in performing the method according to embodiments of the present invention; Figure 2 illustrates the steps occurring in a more specific exemplary method of the present invention; Figures 3(A) illustrates a schematic cross-sectional view though a composite substrate comprising a layer of polycrystalline diamond and a thin layer of silicon or silicon carbide with a series of distinctive crystallographic plane steps propagating out from a point of cleavage origin; Figure 3(B) illustrates a top-view of the composite substrate shown in Figure 3(A) showing the series of distinctive crystallographic steps propagating out from a point of cleavage origin.

Figure 4 shows a cross section of a portion of a diamond-silicon-gallium nitride composite wafer manufactured using a method as described herein; Figure 5 illustrates an experimental set-up for modelling stress profiles of silicon-diamond composite substrates according embodiments of the present invention where measurements are taken at Regions 1 and 2 corresponding to a region midway between the centre and the edge of the composite and a region at the edge of the composite respectively; Figure 6 shows a stress profile parallel to the interface at Region 1; Figure 7 shows the stress profile parallel to the interface at Region 2; Figure 8 shows the stress profile perpendicular to the interface at Region 2; Figure 9 shows the shear stress at Region 2; and Figure 10 illustrates a spalling mechanism for cleavage of the silicon.

Detailed Description of Certain Embodiments

Figure 1 illustrates the steps involved in performing the method according to one embodiment of the present invention.

Initially a silicon wafer 10 is selected for use as a substrate for CVD diamond growth.

The silicon wafer 10 is selected to have a desired crystallographic orientation. The desired crystallographic orientation will depend on two considerations: (i) the mechanism of cleavage used for cleaving the silicon after diamond layer growth to form a thin layer of silicon on the diamond; and (ii) the crystallographic orientation required for hetero-epitaxial growth of a semiconductor layer on the silicon layer after cleavage. The present inventors have found that a single crystal { 111} silicon wafer is preferable in many cases as the silicon wafer tends to cleave most readily across the { 111} crystal planes. Furthermore, a { 111} silicon layer provides a good surface for hetero-epitaxial growth of useful semiconductor materials such as c-plane gallium nitride.

Other considerations for selection of a suitable silicon wafer include the size, shape and thickness of the wafer as these features will effect how stress is distributed over the diamond-silicon composite during and after diamond growth as discussed below.

In Step (A) illustrated in Figure 1, a layer of polycrystalline diamond 12 is grown on the silicon wafer 10 using a chemical vapour deposition technique. The present inventors used a microwave plasma-activated chemical vapour deposition technique, alternative techniques such as hot filament activated and plasma arc jet CVD can also be used. Such techniques are known in the art and the details will not be repeated here.

Growing a polycrystalline diamond layer on a silicon wafer creates stress in the silicon wafer and the polycrystalline diamond layer on cooling due to the thermal mismatch between the polycrystalline diamond layer and the silicon wafer. Three failure modes are possible due to this stress: cracking of the polycrystalline diamond layer; cracking of the silicon wafer; and/or delamination of the silicon wafer from the polyciystalline diamond layer at the interface.

The amount and distribution of stress within a diamond-silicon composite generated during cooling after diamond growth can be controlled by controlling the temperature of the composite. Accordingly, selecting a suitable temperature can alleviate failure due to cracking and/or delamination. Furthermore, a change in temperature can be utilized to initiate or assist cleavage. Advantageously, during growth of the polycrystalline diamond layer the temperature of the composite is controlled to be in the range 700 to 1200°C.

Varying the thickness of the silicon and diamond layers alters the stress distributed in the silicon and diamond layers. Accordingly, selecting a suitable thickness for each of the layers can alleviate failure due to cracking and/or delamination. Furthermore, a suitable thickness for each of the layers can be selected to promote cleavage.

Advantageously, the silicon substrate layer has a thickness in the range 0.3 mm to 2.00 mm prior to diamond layer formation. The diamond layer is advantageously grown to a thickness 50 to 150 pm.

According to one arrangement an approximately 100 tm thick layer of polycrystalline diamond 12 is grown on a (111) silicon substrate 10 having a thickness of 525tm.

The silicon-diamond composite forms a disk having a diameter of approximately 100 mm. The temperature of the composite is maintained at approximately 800°C during growth of the polycrystalline diamond.

In Step (B) illustrated in Figure 1, the silicon-diamond composite is cooled to room temperature. As the composite cools after diamond growth, stress is generated in the silicon substrate 10 due to the difference in thermal expansion coefficient between the silicon substrate 10 and the diamond layer 12. This forces the composite wafer into a dome shape with a peak height h in the range 0.5 to 2mm, preferably approximately 1 mm. A strain field is generated in the silicon wafer 10 which is sufficient to enable cleavage at a distance of 15 im or less from an interface with the polycrystalline diamond layer 12 while being low enough to avoid the wafer fragmenting and/or the p0 lycrystalline diamond layer cracking In Step (C) illustrated in Figure 1, the wafer 12 cleaves parallel and close to an interface with the polycrystalline diamond layer 10 to release strain energy and form a composite substrate comprising the polycrystalline diamond layer 10 directly bonded to a thin layer of single crystal silicon 14. Since the adhesion of CVD diamond and silicon is relatively strong, a thin layer of silicon 14 remains adherent to the diamond layer 12. The silicon layer 14 may have a thickness of approximately 100 nm. Such a thin layer applies very little strain to the diamond layer 12 and the composite wafer flatness is essentially that of the free-standing as grown diamond layer.

Although not shown in Figure 1, the polycrystalline diamond layer 12 may be optionally polished.

Finally, in Step (D) illustrated in Figure 1, a semiconductor layer 16 is grown in a heteroepitaxial manner on the thin silicon layer 14. One or more buffer layers (not shown) may be grown on the silicon layer in a heteroepitaxial manner prior to growth of an active semiconductor device layer 16. For example, one or more buffer layers may be desirable to alleviate thermal expansion mismatches between adjacent layers.

Figure 2 illustrates the steps occurring in another exemplary method of the present invention. Steps (A) and (B) are analogous to Steps (A) and (B) illustrated in Figure 1. In Step (A), a layer of polycrystalline diamond 22 is grown on a silicon wafer 20 using a chemical vapour deposition technique. In Step (B), the silicon-diamond composite is cooled generating a strain field in the silicon wafer and forcing the composite into a dome shape.

The arrangement of Figure 2 differs from that illustrated in Figure 1 in that the silicon wafer 20 doesn't automatically cleave on cooling. Accordingly, as the composite reaches room temperature in Step (C) the silicon wafer 20 remains in its strained state.

This may be because a thinner layer of diamond 22 is formed which has insufficient strength to trigger cleavage of the silicon wafer 20 during cooling.

In Step (D) illustrated in Figure 2, cleavage of the wafer 20 is triggered to form the desired thin layer of single crystal silicon 24. Cleavage may be triggered by applying a mechanical force at a desired location for cleavage. In its simplest form, this may be done by applying a point or edge tool, such as a knife blade, to a side of the silicon wafer near the diamond layer interface to form a notch which acts as an initiation point for cleavage propagation to release strain energy. Alternatively, a thermal shock may be applied to the composite in order to trigger cleavage as previously described.

Finally, in Step (E) a semiconductor layer 26 is grown in a hetero-epitaxial manner on the thin silicon layer 24. In this example c-plane GaN was grown on the (111) silicon layer to form a diamond-silicon-GaN composite wafer.

Figures 3(A) and 3(B) show a composite substrate formed according to a method such as that illustrated in Figures 1 or 2. Figures 3(A) illustrates a schematic cross-sectional view though a composite substrate comprising a layer of polycrystalline diamond 30 and a thin layer of silicon or silicon carbide 32 with a series of distinctive crystallographic plane steps 36 propagating out from a point of cleavage origin 34.

Figure 3(B) illustrates a top-view of the composite substrate shown in Figure 3(A) showing the series of distinctive crystallographic steps 36 propagating out from the point of cleavage origin 34. As can be seen, a cleaved surface has a distinctive pattern of crystallographic plane steps which forms as the cleavage front propagates across the composite substrate. The shape and distribution of crystallographic plane steps is a superposition of the direction of cleave front propagation and the crystallographic structure of the wafer which has been cleaved. The periphery of the cleave radiates out from the origin of the cleave in all directions within the composite wafer, the cleavage steps form along this periphery, typically following major crystallographic directions, at least in short segments. Multiple such short segments may be connected together to form a macroscopic cleavage step which is not obviously, on the macroscopic scale, aligned to a major crystallographic axis. The pattern of such cleavage steps is generally of a form however that the path of the cleavage periphery and the origin of the cleave can be determined, and make the cleaved surface distinct from any other form of surface.

Figure 4 shows a cross section of a portion of a diamond-silicon-gallium nitride composite wafer manufactured using a method according to an embodiment of the present invention. The silicon (11 1) interface layer is less than 100 nm thick. The GaN is c plane (200) with an X-ray rocking curve FWHM of 0.95°. As such, it has been demonstrated that a silicon wafer can be utilized as a substrate to grow a layer of polycrystalline diamond and the thermal mismatch between the silicon and the diamond material can be optimized to cleave the silicon near the silicon-diamond interface to leave a thin layer of single crystal silicon on which semiconductor layers can be epitaxially grown.

The present invention has been exemplified as illustrated in Figure 4 using gallium nitride as the semiconductor material. Gallium nitride is useful in forming gallium nitride high electron mobility transistor (GaN HEMT) structures. However, it will be understood that the concepts of the present invention may be utilized to form other semiconductor devices and structures using a variety of different semiconductor materials.

In order to model the stress profile of silicon-diamond composite substrates according embodiments of the present invention, an experimental set up as illustrated in Figure 5 was provided. The composite comprises a polycrystalline diamond layer 44 and a silicon layer 46. Reference numeral 40 indicates the composite centre and point of axial symmetry. The silicon-diamond composite had a radius of 25 mm, a silicon thickness of 625 jim, and a polycrystalline diamond layer thickness of 100 jim. The composite was clamped along planes 42 by applying constraints at top and bottom sides of the composite in a direction perpendicular to the interface 48 between the silicon and diamond layers. The composite was cooled from 800°C to 25°C. Stress measurements were taken in two regions: Region 1 at a midpoint between the centre and the edge of the composite; and Region 2 at an outer edge of the composite.

Figure 6 shows the stress profile parallel to the interface at Region 1. Figure 7 shows the stress profile parallel to the interface at Region 2. Figure 8 shows the stress profile perpendicular to the interface at Region 2. Figure 9 shows the shear stress at Region 2. The shear stress exceeds 100 MPa at approximately 15 tm from the interface.

The measurements indicate a large shear stress build up around the interface with the silicon layer in tension and the polycrystalline diamond layer in compression. This can lead to interfacial cracking. At a certain stress in the silicon and diamond composite, it is energetically favourable for the wafer to spall from an interfacial crack as illustrated in Figure 10. Figure 10 shows a composite comprising a polycrystalline diamond layer 90, a silicon layer 92, and an interface 94. A spalling crack 96 extends parallel to the interface 94.

The idealized criterion for spalling may be expressed by the following formula: F1 h -\1v -0.3430.2 where h is the critical thickness of the diamond layer, F is the fracture resistance of silicon, E is the biaxial elasticity of polycrystalline diamond, v is Poison's ratio, and 0.

is the stress in the silicon parallel to the interface.

Spalling is one possile failure mechanism in accordance with certain embodiments of the present invention as it leaves a thin residual layer of silicon on the polycrystalline diamond.

In addition to selecting suitable layer thicknesses and controlling substrate temperature during deposition of the CVD diamond layer to create a peak cleaving force at a desired depth, other methods may be used in combination to trigger cleaving and/or provide fine control of the exact location and orientation of the cleavage plane. The cleaving can be controlled in a number of different ways including one or more of the following: (a) Forming shallow processing pits, e.g. 20 nm to 100 nm, in the silicon substrates prior to diamond growth. A nano-structured surface may be formed on the silicon by nano-imprinting the silicon prior to diamond growth.

(b) Creating a damage layer in the silicon. This may be done by irradiating the silicon prior to diamond growth. For example, implanting Argon or Helium can generate a damage layer. A damage layer may alternatively be formed in-situ via high temperature hydrogen annealing prior to growth. Hydrogen diffuses into silicon at temperatures above 500°C. Prior to growth a damage layer can be created by a controlled duration exposure and an Ostwald ripening annealing step to define the depth of the damage plane.

(c) Deliberate inclusion of cleave planes in the silicon substrate prior to growth.

It is proposed that these can be created via buried oxides. Alternatively, a titanium layer can be implanted and an Ostwald ripening annealing step used to form a silicide layer.

(d) Triggering the cleavage at the end of the growth process by changing the process conditions (temperature) or post growth by the application of a force parallel to the cleave plane at one or more positions, for example using a sharp edge. A thermal shock such as rapid cooling below room temperature may also be used to trigger cleavage. For example, liquid nitrogen may be applied to initiate cleavage.

All these approaches are designed to incorporate a weaker layer at the desired depth for silicon cleavage or to otherwise provide a sufficiently high strain in the silicon near the silicon-diamond interface to enable cleavage. The methods may be used alone or in combination.

While this invention has been particularly shown and described with reference to preferred embodiments, it will be understood to those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as defined by the appendant claims.

Claims (43)

1. Claims 1. A method of manufacturing a composite substrate for a semiconductor device, the method comprising: selecting a wafer comprising single crystal silicon or silicon carbide, the wafer having a thickness in a range 0.3 mm to 2.0 mm; growing a polycrystalline diamond layer on the wafer using a chemical vapour deposition technique at a first temperature in a range 700°C to 1200°C to form a composite comprising the wafer bonded to the polycrystalline diamond layer, the polycrystalline diamond layer having a thickness in a range 50 im to 150 kim; heating or cooling the composite to a second temperature to generate a strain field in the wafer which is sufficient to enable cleavage of the wafer at a distance of trn or less from an interface with the polycrystalline diamond layer while being low enough to avoid the wafer fragmenting and/or the polycrystalline diamond layer cracking; and cleaving the wafer at a distance of 15 tm or less from an interface with the polyciystalline diamond layer to release strain energy and form a composite substrate comprising the polycrystalline diamond layer directly bonded to a cleaved layer comprising single crystal silicon or silicon carbide, the cleaved layer having a thickness of 15 tm or less.
2. 2. A method according to claim 1, wherein the selecting comprises selecting the wafer to have athickness in the range: 0.3 mmto 1.8 mm; 0.3 mmto 1.5 mm; 0.3 mm to 1.3 mm; 0.3 mm to 1.0 mm; or 0.5 mm to 0.8 mm.
3. 3. A method according to claim 1 or claim 2, wherein the selecting comprises selecting the wafer to have a diameter in the range: 20 mm to 160 mm; 40 mm to 140 mm; 60 mmto l2Ornm;80mmto 120 mm;or90mmto 110mm.
4. 4. A method according to any preceding claim, wherein the polycrystalline diamond layer is grown to a thickness in the range: 70 im to 130 tm; 80 tm to 120 jm,or9Ojimto 110 pm.
5. 5. A method according to any preceding claim, wherein the polycrystalline diamond layer is grown to a diameter in the range: 20 mm to 160 mm; 40 mm to 140 mm; 60 mm to 120 mm; 80 mm to 120 mm; or 90 mm to 110 mm.
6. 6. A method according to any preceding claim, wherein the first temperature is in the range: 700°C to 1100°C; 700°C to 1000°C; or 700°C to 900°C.
7. 7. A method according to any preceding claim, wherein the second temperature is equal to or less than: 400°C; 200°C; 100°C; or 50°C.
8. 8. A method according to any preceding claim, wherein the cleaved layer has a thickness of: 10 jim or less; 5tm or less; 3jim or less; him or less; lOOnm or less; or SOnm or less.
9. 9. A method according to any preceding claim, wherein the cleaved layer has a thickness of: lOnm or more; or 2Onm or more.
10. 10. A method according to any preceding claim, wherein the cleaving occurs during or after heating or cooling the composite to the second temperature.
11. 11. A method according to any preceding claim, wherein the cleaved layer has a surface which is oriented within 5°, 4°, 30, 2°, 1°, or 0.5° of a plane parallel to the interface with the polycrystalline diamond layer.
12. 12. A method according to any preceding claim, wherein the cleaved layer has a surface comprising a series of steps between crystallographic planes, the series of steps propagating out from a point of cleavage origin.
13. 13. A method according to any preceding claim, wherein the cleaved layer has a thickness which varies less than or equal to 10 tm, 5 tm, 1 tim, 500 nm, 200 nm, 100 nm, 50 nm, or lOnm over an area greater than or equal to 1 mm2, 5 n2 10 ff2 30 mm2, 100 mm2, 300 mm2 or 1000 iTim2
14. 14. A method according to any preceding claim, wherein the cleaved layer has a thickness which varies less than or equal to 10 jim, 5 jim, 1 jim, 500 nm, 200 nm, 100 nm, 50 nm, or lOnm over an area greater than or equal to 50%, 60%, 70%, 80% or 90% of a total surface area of the cleaved layer.
15. 15. A method according to any preceding claim, wherein the cleaved layer has a surface which is at least 80%, at least 90%, at least 95%, at least 98%, at least 99%, or 100% single crystal.
16. 16. A method according to any preceding claim, further comprising: treating the wafer to promote cleavage at a desired depth.
17. 17. A method according to claim 16, wherein treating the wafer comprises one or more of: forming a damage layer in the wafer to the desired depth; implanting a weakened cleave plane at the desired depth; and forming pits in a surface of the wafer which extend to the desired depth.
18. 18. A method according to any preceding claim, wherein the wafer cleaves automatically due to stress generated in the wafer due to a difference in thermal expansion coefficient between the wafer and the polycrystalline diamond layer during heating or cooling to the second temperature.
19. 19. A method according to any one of claims ito 17, further comprising: applying an external force to the composite to trigger cleavage of the wafer.
20. 20. A method according to any one of claims 1 to 17, further comprising: applying a thermal shock to the composite to trigger cleavage of the wafer.
21. 21. A method according to any preceding claim, wherein the selecting comprises selecting a wafer which has a major surface oriented within 100, 5°, 4°, 3°, 2°, 1°, or 0.5° of a {100}, { 110), or {1 11} crystallographic plane.
22. 22. A method according to any preceding claim, wherein the cleaving is directed within 10°, 5°, 4°, 3°, 2°, 1°, or 0.5° of a <100>, <110>, <111>, or <113> crystallographic direction.
23. 23. A method according to any preceding claim, wherein the selecting comprises selecting a silicon wafer which has a major surface oriented within 100, 5, 4°, 3°, 2°, 10, or 0.50 ofa {111} crystallographic plane.
24. 24. A method according to claim 23, wherein the cleaving is directed within 10°, 5°, 4°, 3°, 2°, 10, or 0.5° of a <110> crystallographic direction.
25. 25. A method according to any preceding claim, further comprising: processing the cleaved layer after cleaving to form a planarized surface.
26. 26. A composite substrate for a semiconductor device, the composite substrate comprising: a layer of polycrystalline diamond; and a cleaved layer comprising single crystal silicon or silicon carbide, the cleaved layer being directly bonded to the layer of polycrystalline diamond at an interface between the cleaved layer and the layer of polycrystalline diamond, wherein the cleaved layer has a thickness of 15 1.tm or less.
27. 27. A composite substrate according to claim 26, wherein the polycrystalline diamond layer has a thickness in the range: 50 tm to 150 1im; 70 im to 130 1im; 80 tmto 120 tm, or9O jimto 110 pm.
28. 28. A composite substrate according to claim 26 or claim 27, wherein the polyciystalline diamond layer has a diameter in the range: 20 mm to 160 mm; 40 mm to 140 mm;60mmto 120 mm; 8Ommto l2Omm;or9Ommto 110 mm.
29. 29. A composite substrate according to any one of claims 26 to 28, wherein the cleaved layer has a thickness of: 10 tm or less; 5iim or less; 3iim or less; him or less; lOOnm or less; or 5Onm or less.
30. 30. A composite substrate according to any one of claims 26 to 29, wherein the cleaved layer has a thickness of: lOnm or more; or 2Onm or more.
31. 31. A composite substrate according to any one of claims 26 to 30, wherein the cleaved layer has a surface which is oriented within 50, 40, 30, 2°, 1°, or 0.5° of a plane parallel to the interface with the polycrystalline diamond layer.
32. 32. A composite substrate according to any one of claims 26 to 31, wherein the cleaved layer has a surface comprising a series of steps between crystallographic planes, the series of steps propagating out from a point of cleavage origin.
33. 33. A composite substrate according to any one of claims 26 to 31, wherein the cleaved layer comprises a planarized surface.
34. 34. A composite substrate according to any one of claims 26 to 33, wherein the cleaved layer has a thickness which varies less than or equal to: 10 jim; 5 lim; 1 lim; 500 nm; 200 nm; 100 nm; 50 nm; or lOnm over an area greater than or equal to 1 mm2, 5 mm2, 10 mm2, 30 mm2, 100 mm2, 300 mm2, or 1000 mm2.
35. 35. A composite substrate according to any one of claims 26 to 34, wherein the cleaved layer has a thickness which varies less than or equal to: 10 kim; 5 lim; 1 lim; 500 nm; 200 nm; 100 nm; 50 nm; or lOnm over an area greater than or equal to 50%, 60%, 70%, 80% or 90% of a total surface area of the cleaved layer.
36. 36. A composite substrate according to any one of claims 26 to 35, wherein the cleaved layer has a surface which is at least 80%, at least 90%, at least 95%, at least 98%, at least 99%, or 100% single crystal.
37. 37. A composite substrate according to any one of claims 26 to 36, wherein the cleaved layer has a surface which is oriented within 10°, 5°, 4°, 30, 2°, 1°, or 0.5° of a {100}, {1 10}, or {1 11} crystallographic plane.
38. 38. A composite substrate according to any one of claims 26 to 37, wherein the cleaved layer is a layer of silicon which has a surface which is oriented within 5°, 4°, 3°, 2°, 1°, or 0.5° of a {1 1 1} crystallographic plane.
39. 39. A method of manufacturing a semiconductor device comprising: providing the composite substrate as claimed in any one of claims 26 to 38; and epitaxially growing a layer of semiconductor material over the cleaved layer, whereby the cleaved layer forms an interface layer between the polycrystalline diamond layer and the layer of semiconductor material.
40. 40. A method according to claim 39, further comprising: processing the cleaved layer to form a planarized surface prior to epitaxially growing the layer of semiconductor material over the cleaved layer.
41. 41. A method according to claim 39 or 40, further comprising: depositing a buffer layer on the cleaved layer prior to epitaxially growing the layer of semiconductor material over the cleaved layer.
42. 42. A semiconductor device comprising: the composite substrate as claimed in any one of claims 26 to 38; and a layer of semiconductor material epitaxially grown over the cleaved layer.
43. 43. A semiconductor device according to claim 42, further comprising: a buffer layer disposed between the cleaved layer and the layer of semiconductor material.*::r: INTELLECTUAL . ... PROPERTY OFFICE Application No: GB 1110557.4 Examiner: Dr Paul Baxter Claims searched: 1-43 Date of search: 29 June 2011 Patents Act 1977: Search Report under Section 17 Documents considered to be relevant: Category Relevant Identity of document and passage or figure of particular relevance to claims X 26-43 US2002/096 106 Al (KUB) Abstract, figure 1, paragraphs 28-32, 47 and 57 Y 1-43 EP1706895 A2 (CREE) Abstract, figure 1, paragraphs 27-33, 39 and 58 Y 1-43 EP1861865A1 (ELEMENT SIX) Abstract, figure 1, page 4 lines 18-22, page 5 lines 23-27, page 7 line 12 -page 8 line 28 Y 1-43 EP0442304A2 (GEN ELECTRIC) Abstract, column 2 line 64 -column 3 line 3, column 3 line 23 -column 5 line 15 Y 1-43 US7695564B1 (MICOVIC) Abstract, figures 1-4, column 2 lines 6-8, column 4 line 53 -column 6 line 10 Y 16, 17 and U5629 1326 Bi 19 (HENLEY) Column 1 line 51 -column 2 line 28, column 3 lines 33-37 A -W02005/122284A2 (SUNG CHIEN-MIN) Abstract, figure 3C, page 16 lines 1-13 A -EP1631984A1 (SOITEC) See English family member US2004248380 Al (AULNETTE) Abstract, figures 3A, 3B and 3C, paragraphs 16 and 42-A -EP1459361 A2 (ELEMENT SIX) Abstract, figures la, lb and lc, page 2 lines 5 and 6, page 5 lines 12 and 13, page 6 line 27 -page 8 line 19 Categories: X Document indicating lack of novelty or inventive A Document indicating technological background and/or state step of the art.Y Document indicating lack of inventive step if P Document published on or after the declared priority date but combined with one or more other documents of before the filing date of this invention.same category.& Member of the same patent family E Patent document published on or after, hut with priority date Intellectual Property Office is an operating name of the Patent Office www.ipo.gov.uk *::r: INTELLECTUAL . ... PROPERTY OFFICE earlier than, the filing date of this application.Field of Search:Search of GB, EP. WO & US patent documents classified in the following areas of the UKCX Worldwide search of patent documents classified in the following areas of the IPC C23C; C3OB; HUlL The following online and other databases have been used in the preparation of this search report ONLINE: WPI, EPODOC, INSPEC, XPESP, XPI3E, XPIEE, XPIOP and XPAIP I International Classification: Subclass Subgroup Valid From HO1L 0021/205 01/01/2006 C23C 00 16/24 01/01/2006 C3OB 0029/04 01/01/2006 HO1L 0021/20 01/01/2006 HO1L 0021/48 01/01/2006 HO1L 0023/373 01/01/2006 Intellectual Property Office is an operating name of the Patent Office www.ipo.gov.uk