TW202205357A - Process for manufacturing a composite structure comprising a thin layer of monocrystalline sic on a carrier substrate made of sic - Google Patents

Abstract

The invention relates to a process for manufacturing a composite structure comprising a thin layer of monocrystalline silicon carbide arranged on a carrier substrate made of silicon carbide, the process comprising: (a) a step of providing an initial substrate made of monocrystalline silicon carbide, (b) a step of epitaxial growth of a monocrystalline silicon carbide donor layer on the initial substrate, to form a donor substrate 111, (c) a step of ion implantation of light species into the donor layer, to form a buried brittle plane delimiting the thin layer between said buried brittle plane and a free surface of said donor layer, (d) a step of direct liquid injection-chemical vapour deposition, at a temperature below 1000 DEG C, to form a carrier layer directly on the free surface of the donor layer, said carrier layer being formed by an at least partially amorphous SiC matrix, (e) a step of separating along the buried brittle plane to form, on the one hand, an intermediate composite structure comprising the thin layer on the carrier layer and, on the other hand, the rest of the donor substrate, (f) a step of heat treatment at a temperature of between 1000 DEG C and 1800 DEG C, applied to the intermediate composite structure, to crystallize the carrier layer and to form the polycrystalline carrier substrate, (g) a step of mechanical and/or chemical treatment(s) of the composite structure.

Description

A method for making a composite structure comprising a thin layer of single crystal SiC on a SiC carrier substrate

The present invention relates to the field of semiconductor materials for microelectronic components. In particular, the present invention relates to a method for fabricating a composite structure comprising a thin layer of monocrystalline silicon carbide disposed on a carrier substrate made of silicon carbide.

Interest in silicon carbide (SiC) has grown substantially over the past few years because of the semiconductor material's ability to increase processing power. SiC is increasingly being used to make innovative power components to meet the needs of emerging electronics fields such as electric vehicles.

Monocrystalline silicon carbide-based power components and integrated supply systems are able to manage much higher power densities relative to traditional silicon homologues, and do so with smaller active region sizes . To further limit the size of power components on SiC, it is advantageous to make vertical components instead of horizontal components. To this end, it is necessary to allow vertical conduction between the electrodes arranged on the front side and the electrodes on the back side of the SiC structure.

However, single crystal SiC substrates for the microelectronics industry are currently still quite expensive and difficult to provide in large sizes. Therefore, it is advantageous to utilize the thin layer transfer method to fabricate composite structures, which typically include a thin layer of single crystal SiC disposed on a relatively inexpensive carrier substrate. A well-known thin layer transfer method is the Smart Cut ^(TM) method, which is based on light ion implantation and direct bonding. The method allows the fabrication of composite structures comprising thin layers of monocrystalline SIC (hereafter referred to as c-SiC), which are taken from a c-SiC donor substrate, and a carrier substrate of polycrystalline SiC (hereafter referred to as p-SiC) direct contact and allow vertical conduction. However, it is still difficult to achieve high-quality direct bonding through molecular adhesion between c-SiC and p-SiC bisubstrates, because managing the surface state and roughness of these substrates is rather complicated.

There are also various processing approaches derived from the method in the prior art. For example, F. Mu et al. (ECS Transactions, 86 (5) 3-21, 2018) performed direct bonding (SAB is an abbreviation for "surface-activated bonding") after activating the surfaces to be bonded by argon bombardment: this This pre-bonding treatment produces a very high density of side bonds that promote the formation of covalent bonds at the bonding interface, resulting in high bonding energies. However, the disadvantage of this method is the creation of an amorphous layer on the surface of the single crystal SiC donor substrate, which negatively affects the vertical conduction between the c-SiC thin layer and the p-SiC carrier substrate.

Solutions to this problem have been proposed, in particular document EP3168862, which employs implantation of dopant species into the amorphous layer to restore its electrical properties. The biggest disadvantage of this method is that it is complicated and expensive.

The document US8436363 discloses a method for producing a composite structure comprising a thin layer of c-SiC disposed on a metal carrier substrate, the thermal expansion coefficient of the carrier substrate being matched to that of the thin layer. This production method includes the following steps: - forming a buried brittle plane in the c-SiC donor substrate, thereby defining a thin layer between the buried brittle plane and the front surface of the donor substrate; - deposit a layer of metal, such as tungsten or molybdenum, on the front surface of the donor substrate to form a carrier substrate of sufficient thickness to function as a stiffener; - Separation along the buried brittle plane to form the composite structure comprising the metal carrier substrate and the c-SiC thin layer on the one hand, and the remainder of the c-SiC donor substrate on the other hand.

However, this fabrication method is incompatible when the material forming the carrier substrate is p-SiC, since p-SiC needs to be deposited at temperatures above 1200°C (the temperature typically used to make p-SiC). ). Specifically, at such high temperatures, the growth kinetics of the cavities existing in the embedded brittle planes are faster than those of the p-SiC layer and cannot be strong before blistering begins to appear. The thickness required for the effect, blistering is related to the deformation of the layer perpendicular to the cavity.

Regardless of the method used to transfer the layers, another issue arises with respect to providing a composite structure comprising ultra-high quality c-SiC thin layers, and more specifically no extensive defects (or with very low densities of extensive defects) , the defect easily affects the performance quality and reliability of the power device to be formed on the thin layer.

The present invention relates to an alternative solution to the prior art in order to overcome all or some of the aforementioned disadvantages. In particular, the present invention relates to a method for fabricating a composite structure comprising a thin layer of high quality c-SiC disposed on a crystalline SiC carrier substrate.

The present invention relates to a method for fabricating a composite structure comprising a thin layer of monocrystalline silicon carbide disposed on a carrier substrate made of silicon carbide. The method contains: a) the step of providing an initial substrate of single crystal silicon carbide, b) the step of epitaxially growing a donor layer of monocrystalline silicon carbide on the initial substrate to form a donor substrate, the donor layer having a crystal defect density lower than that of the initial substrate, c) the step of implanting light species ions into the donor layer to form a buried brittle plane to define the thin layer between the buried brittle plane and the free face of the donor layer, d) the step of carrying out direct injection liquid chemical vapor deposition at a temperature below 1100°C to form a support layer directly on the free surface of the donor layer, the support layer consisting of an at least partially amorphous SiC matrix (partially amorphous SiC matrix) is formed, e) a step of separating along the buried brittle plane, thereby forming an intermediate composite structure comprising the thin layer on the carrier layer on the one hand and the remainder of the donor substrate on the other hand, f) a step of applying a thermal treatment to the intermediate composite structure at a temperature between 1000°C and 1800°C to crystallize the carrier layer and form the polycrystalline carrier substrate, g) the step of subjecting the composite structure to a mechanical and/or chemical treatment applied to the free side of the carrier substrate (ie the back side of the composite structure) and/or the free side of the thin layer (ie the composite structure) front of the structure).

According to other advantageous and non-limiting features of the invention, which can be implemented individually or in any technically feasible combination: ∙ said deposition step d) is carried out at a temperature between 100°C and 700°C, or even preferably at a temperature between 200°C and 600°C; ∙ the deposition step d) is carried out at a pressure between 1 Torr and 500 Torr; ∙ the precursor used during the deposition step d) is selected from polysilylethylene and disilabutane; ∙ at the end of said deposition step d), the carrier layer has a thickness greater than or equal to 10 μm, even greater than or equal to 50 μm, or even greater than or equal to 100 μm, or even greater than or equal to 200 μm; ∙ chemical etching, mechanical grinding and/or chemical mechanical polishing, applied to the free face of the carrier layer between steps d) and e); ∙ Step a) includes forming a single crystal conversion layer on the initial substrate to convert basal plane dislocation defects of the initial substrate into threading edge dislocation defects; ∙ The epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably at a temperature between 1500°C and 1650°C; ∙ the separation step e) is carried out at a temperature higher than the deposition temperature of step d); ∙ said separation step e) takes place during said deposition step d), preferably at the end of step d); ∙ said separation step e) and said crystallization step f) take place during the same heat treatment; ∙ Step g) comprises the simultaneous chemical mechanical polishing of the front and back sides of the composite structure; ∙ The method further includes the step of trimming the remainder of the donor substrate for the purpose of reusing it as an initial substrate or a donor substrate.

In the following description, the same numerals in the drawings represent elements of the same type. For ease of illustration, the drawings are schematic representations that are not drawn to scale. In particular, the thicknesses of the layers along the z-axis are not to scale relative to the lateral dimensions along the x- and y-axes; furthermore, the relative thickness relationships between the layers are not necessarily presented in the drawings as they are.

The present invention relates to a method for producing a composite structure 1 comprising a thin layer 10 of monocrystalline silicon carbide disposed on a carrier substrate 20 made of silicon carbide (FIG. 1). The carrier substrate 20 is advantageously polycrystalline (polycrystalline SiC will be referred to as "p-SiC" hereinafter).

The method first comprises the step a) of providing an initial substrate 11 of single crystal silicon carbide (FIG. 2a). In the following description, single crystal silicon carbide will be referred to as "c-SiC".

The initial substrate 11 is preferably a wafer with a diameter of 100 mm, 150 mm, 200 mm, or even 300 mm, or even 450 mm, with a thickness typically between 300 and 800 microns. The initial substrate 11 has a front surface 11a and a back surface 11b. The surface roughness of the front side 11a may advantageously be selected to be below 1 nm Ra (average roughness), as measured with an atomic force microscope (AFM) scan of 20 microns x 20 microns.

The method then includes step b) of epitaxially growing a donor layer 110 of monocrystalline silicon carbide on the initial substrate 11 to form a donor substrate 111 (FIG. 2b). The epitaxial growth step operates so that the crystal defect density of the donor layer 10 is lower than the crystal defect density of the initial substrate 11 .

The initial substrate 11 made of c-SiC is usually a 4H or 6H polytype, which exhibits an offcut of less than 4.0°±0.5° with respect to the <11-20> crystallographic axis, and Micropipe density below or equal to 5/cm ² or even below 1/cm ² . For example, when the initial substrate 11 is N-type (nitrogen) doped, its resistivity is preferably between 0.015 ohm.cm and 0.030 ohm.cm. The selected initial substrate 11 may have a low basal plane dislocation (BPD) defect density, typically less than or equal to 3000/cm ² . c-SiC substrates with a BPD density of about 1500/ ^cm2 are reasonably available and are therefore easy to supply.

At the end of the method of the present invention, the c-Si thin layer 10 of the composite structure 1 will be formed from the donor layer 110. In order to meet the required specifications of the vertical components to be fabricated on the thin layer 10, it is expected that the crystal quality of the donor layer 110 is high. on the initial substrate 11. Different types of extensive defects exist in the layer or substrate of c-SiC. These extensive defects may affect device performance and reliability. In particular, BPD defects are fatal for bipolar assemblies: Shockley stacking faults (SFFs) will propagate from dislocations when the recombination energy of electron-hole pairs is present. SFF expansion inside the active region of a device will cause the device's passing state resistance to increase.

Therefore, the c-SiC donor layer 110 is fabricated in such a way that the BPD defect density is lower than or equal to 1/cm ² .

For this purpose, the epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably at a temperature between 1500°C and 1650°C. The precursors are silane (SiH4), propane (C3H8) or ethylene (C2H4); the carrier gas can be hydrogen with or without argon.

A low BPD defect rate in the donor layer 110 can be achieved by promoting the conversion of BPD defects present in the original substrate 11 into through edge dislocations (TED).

According to a particular embodiment, step a) comprises forming a single crystal conversion layer 13, preferably of c-SiC, to maximize the conversion of BPD defects in the initial substrate 11 into TED defects (FIG. 3a). For this purpose, c-SiC starting substrates 11 with a low off-angle close to 4°, increased in-situ etching prior to epitaxial growth, targeting high growth rates (typically greater than 5 µm/h), and single The growth conditions of the crystal conversion layer 13 are favorable for the C/Si ratio in the precursor stream to be close to 1.

Step b) then consists of epitaxially growing a donor layer 110 on the conversion layer 13 (FIG. 3b). According to this particular embodiment, it is also possible to obtain a c-SiC donor layer 110 with a BPD defect density lower than or equal to 1/cm ² , or even lower than 0.1/cm ² . Furthermore, the probability of bipolar degradation (probability of holes reaching below the BPD/TED transition point) at the end of the method of the present invention is extremely small (< 0.1%), since the single crystal transition layer 13 does not Move to Composite 1. A conventional technique aimed at reducing bipolar degradation involves introducing a recombination layer (doped with nitrogen in excess of 1 ^E 18 at/cm ³ ) between the conversion layer and the active layer. At the expense of a thickness of 10 µm and a concentration higher than 5 ^E 18/cm ³ , the recombination layer reduces the probability of holes to 0.1% compared to the basic structure without this recombination layer. In the present invention, since the single crystal conversion layer 13 is not transferred, the probability of holes reaching the bipolar degeneration nucleation point (BPD-TED conversion point or any BPD point) is at least less than 0.1% or even close to 0%.

It should be noted that prior to the epitaxial growth in step b), conventional cleaning or etching procedures of the initial substrate 11 may be performed to remove part or all of the particulate contamination, metal contamination or organic contamination, or there may be Native oxide layer on the front side 11a.

The fabrication method according to the present invention further comprises the step c) of implanting light ion species into the donor layer 110 to a predetermined depth, the predetermined depth representing the desired thickness of the thin layer 10, and the implantation in any case does not touch the initial Substrate 11 (and/or conversion layer 13, if any). The implantation forms a buried brittle plane 12 in the donor layer 110, which defines a thin layer 10 between the buried brittle plane 12 and the free face 11a of the donor layer 110 (FIG. 2c).

The implanted light species is preferably hydrogen, helium, or a co-implantation of hydrogen and helium. As known with reference to the Smart Cut ^(TM) method, the light species will form microcavities around a given depth, distributed in a thin layer parallel to the free face 11a of the donor layer 110, ie parallel to the plane in the diagram ( x, y). For brevity, this thin layer is referred to as the buried brittle plane 12 .

The implantation energy of the light species is selected to reach a predetermined depth in the donor layer 110 .

Hydrogen ions are typically implanted at energies between 10 keV and 250 keV and doses between 5 ^E 16/cm ² and 1 ^E 17/cm ² to define a thin layer 10 about 100 nm to 1500 nm thick .

It should be noted that a protective layer may be deposited on the free surface of the donor layer 110 prior to the ion implantation step. The protective layer may be composed of materials such as silicon oxide or silicon nitride.

The method of the present invention then comprises performing direct injection liquid chemical vapor deposition (DLI-CVD) directly on the free surface of the donor layer 110 at a temperature below 1000°C, preferably below 900°C Step d) of forming the carrier layer 20' (FIG. 2d). Said deposition step d) can be carried out at a temperature between 100°C and 800°C, at a temperature between 100°C and 700°C, or even advantageously between 200°C and 600°C. temperature in between. The pressure in the deposition chamber is preferably limited between 1 Torr and 500 Torr.

The DLI-CVD deposition technique can provide good yields between the materials provided (precursors) and the deposition thickness achieved without the use of chlorinated precursors, thereby limiting cost and environmental constraints .

DLI-CVD deposition is preferably performed using neat or diluted disilanebutane or polysilylethylene precursors. Other precursors can also be used as needed, such as methyltrichlorosilane, ethylenetrichlorosilane, dichloromethylvinylsilane, tetraethylsilane, tetramethylsilane Silane (tetramethylsilane), methyl diethoxysilane (diethylmethylsilane), bistrimethylsilylmethane (bistrimethylsilylmethane) or hexamethyldisilazane (hexamethyldisilane).

The technique is described in a paper by Guilhaume Boisselier (2013, “Dépôt chimique en phase vapeur de carbures de chrome, de silicium et d'hafnium assisté par injection liquide pulsée [Pulsed liquid injection-chemical vapour deposition of chromium, silicon and hafnium carbides] ”), used to deposit ceramic coatings on parts, such as metal parts made of steel or alloys, to protect these parts during very high temperature processing.

On the basis of DLI-CVD, the applicant of the present application proposes a deposition step d) which can be used for a completely different application, namely the formation of a carrier layer 20' on the c-SiC donor layer 110, in order to obtain at the end of the production method a deposition step d) for use in the field of microelectronics Composite structure 1.

The deposited carrier layer 20' forms a SiC matrix comprising amorphous SiC and reaction by-products derived from precursors used in the deposition process and formed from carbon chains. In addition, the SiC matrix may optionally contain crystalline SiC grains.

The DLI-CVD technique can provide deposition rates greater than or equal to 10 microns/hour, or even greater than 50 microns/hour, or even greater than 100 microns/hour. At a given average deposition temperature, the deposition rate does not need to be very high (except for obvious economic reasons), since in this temperature range a slow rate is maintained due to thermally activated growth of the cavities embedded in the brittle plane 12, Therefore, the thickness of the carrier layer 20 ′ can be easily made to ensure a strong effect with respect to the buried brittle plane 12 .

At the end of step d), the carrier layer 20' may have a thickness greater than or equal to 10 micrometers, greater than or equal to 50 micrometers, 100 micrometers, or even greater than or equal to 200 micrometers. The stack 211 produced by step d) comprises the carrier layer 20 ′ disposed on the donor layer 110 , and the donor layer 110 disposed on the initial substrate 11 .

The method of the invention then comprises a step e) of separation along the buried brittle plane 12 to form the intermediate composite structure 1' on the one hand and the remainder 111' of the donor substrate on the other hand (Fig. 2e).

According to an advantageous embodiment, the separation step e) is to apply a thermal treatment to the stack 211 at a separation temperature higher than the deposition temperature of step d). In detail, the micro-cavities existing in the embedded brittle plane 12 obey the growth kinetics until a fracture wave is initiated, which will propagate in the entire extent of the embedded brittle plane 12 and cause the intermediate composite structure 1' to be separated from the initial bottom. The remaining portion 111' of the material is separated. In operation, the temperature may be between 950°C and 1200°C, preferably between 1000°C and 1200°C, depending on the implantation conditions of step c).

According to an alternative embodiment, the separation step e) is carried out by applying mechanical pressure to the stack 211 , followed by a heat treatment to embrittle the embedded brittle planes 12 , if desired. This pressure can be applied, for example, by inserting a tool (eg, a knife edge) near the embedded brittle plane 12 . For example, the separation pressure may be on the order of several GPa, preferably greater than 2 GPa.

According to yet another embodiment, the separation step e) along the buried brittle plane 12 takes place during or just after the DLI-CVD deposition step d), more specifically when the deposition temperature reaches 900°C to 1000° Occurs when the scope of C.

The manufacturing method of the present invention then comprises the step f) of applying a heat treatment to the intermediate composite structure 1 ′ at a temperature between 1000° C. and 1800° C. to crystallize the carrier layer 20 ′ and form a polycrystalline carrier substrate 20 .

The tempering atmosphere may in particular contain gases such as argon, nitrogen, hydrogen, helium or mixtures of these.

The tempering has the effect of removing hydrogen from the carrier layer 20' and crystallizing the SiC matrix in the form of polycrystalline SiC.

The crystallization heat treatment can be performed using conventional furnaces that process multiple structures simultaneously (batch tempering). The usual duration of the crystallization heat treatment is between a few minutes and a few hours.

The crystallization heat treatment can optionally be performed in situ in the DLI deposition chamber, with a typical duration of about a few minutes.

Advantageously, the ramp of the temperature rise and fall is limited, eg less than 20°/min, less than 5°/min or even less than 1°/min, to limit the occurrence of cracks or structural defects in the crystalline layer.

After step f) a composite structure 1 can be obtained which comprises a thin layer 10 of monocrystalline silicon carbide disposed on a carrier substrate 20 made of polycrystalline silicon carbide.

Deposition parameters (step d) and crystallisation tempering parameters (step f) are determined so that the carrier substrate 20 has: - good electrical conductivity, ie less than or equal to 0.03 ohm.cm, or even less than or equal to 0.01 ohm.cm, - high thermal conductivity, i.e. greater than or equal to 150 Wm ^-1 .K ^-1 , or even greater than or equal to 200 Wm ^-1 .K ^-1 , - and a thermal expansion coefficient similar to that of the thin layer 10 , i.e. Between 3.8 ^E -6/K and 4.2 ^E -6/K at room temperature.

To achieve these properties, the carrier substrate 20 preferably has structural features such as: polycrystalline structure, 3C SiC grains, [111] orientation, average dimensions in the substrate principal plane of 1 to 50 μm, and N-type Doping so that the final resistivity is less than or equal to 0.03 ohm.cm, or even less than or equal to 0.01 ohm.cm.

Additionally, a non-insulating interface is preferably defined between the donor layer 110 and the carrier substrate 20 . The resistivity of the non-insulating interface is generally expected to be less than 1 mohm.cm ² . In order to ensure the electrical conductivity of the interface, the native oxides present on the free face of the donor layer 110 can be removed by deoxidation with HF (hydrofluoric acid) by wet or dry methods before the deposition step d). As an alternative, the first few nanometers deposited on the carrier layer 20' can be overdoped by introducing doping species during the DLI-CVD deposition step d). It should be noted that, in general, during deposition step d), the dopant species can be introduced at different doses depending on the degree of doping and the target conductivity of the carrier substrate 20, which conductivity will crystallize during step f) Effective at the end of tempering.

It is also advantageous to the present invention that a cleaning procedure may be applied to the donor substrate 111 prior to the formation of the deoxidizing and/or carrier layer 20' to remove some or all of the particulate contamination that may be present on the free side of the substrate substances, metal contaminants or organic contaminants.

It is known that at the completion of the separation step e), the surface roughness of the free surface 10a of the thin layer 10 of the composite structure 1 is between 5 and 100 nm RMS (which is scanned with an atomic force microscope (AFM) of 20 μm x 20 μm). measured in microns).

The step g) of mechanically and/or chemically treating the composite structure 1 is then performed to smooth the free surface 10a of the thin layer 10 and to correct the thickness uniformity of the composite structure 1 (FIG. 2f).

Step g) may comprise chemical mechanical polishing (MCP) of the free surface 10a of the thin layer 10, which typically removes about 50 to 1000 nm of material to obtain a RMS of less than 0.5 nm (scanning 20 x 20 µm with AFM) or even Final roughness less than 0.3 nm. Step g) may also comprise chemical or plasma treatments (cleaning or etching), such as SC1/SC2 cleaning (standard cleaning 1, standard cleaning 2) and/or HF (hydrofluoric acid) cleaning, and/or N2, Ar, CF4 plasma is used to further improve the quality of the free surface 10 a of the thin layer 10 .

It should be noted that the crystallization of the carrier layer 20' often causes cracks or structural defects in the crystalline layer (of which the carrier substrate 20 is formed), thereby affecting its mechanical and electrical quality.

Therefore, step g) may comprise chemical mechanical polishing (MCP) and/or chemical treatment (etching or cleaning) and/or mechanical treatment (trimming) of the backside 20b of the carrier substrate 20 to remove all or part of the aforementioned cracks and structures defects, thereby improving the thickness uniformity of the carrier substrate 20 and the roughness of the back surface 20b thereof. The thickness removed from the backside can be between about 100 microns and several microns.

The ideal roughness is below 0.5 nm RMS (measured with Atomic Force Microscopy (AFM) scanning a 20 micron x 20 micron area) in order to make vertical assemblies where there will be at least one metal electrode on the backside 20b of the composite substrate 1 .

During step g), the edges of the composite structure 1 may also be ground or trimmed so that the shape of its circular profile and cutting edge waste are compatible with the requirements of the microelectronics process.

It should be noted that the treatment applied to the back side 20b of the carrier substrate 20 can optionally be applied to the free side of the carrier layer 20' before the separation step e), ie before the front side 10a of the composite structure 1 is exposed, in order to limit the The degree of its contamination, especially during contaminating or restrictive treatments such as chemical etching or mechanical grinding (dressing).

According to an advantageous embodiment, the chemical mechanical treatment step g) comprises simultaneous grinding (MCP) of the front side 10a and the back side 20b of the composite structure 1 in order to smooth and improve the thickness uniformity of the composite structure 1 . The grinding parameters for the front and back sides can be different because the smoothing of c-SiC and p-SiC surfaces usually requires the use of different consumables. When the carrier substrate 20 is made of p-SiC, the emphasis is particularly placed on the mechanically ground portion of the back surface 20b to limit the preferential attack of the grain boundary by the chemically ground portion. For example, grinding parameters can be adjusted, such as rotational speed (of the grinding head and grinding disc), pressure, concentration of the abrasive and physical properties (ie, the diameter of the diamond nanoparticles is between about 10 nm and 1 µm), etc., To strengthen the mechanical grinding part.

After step g), a heat treatment step g') is optionally carried out at a temperature between 1000°C and 1800°C for about one hour up to several hours. The purpose of this step is to stabilize the composite structure 1 by ensuring that structural or organizational defects remain within and/or over the thin layer 10 and, where appropriate, by allowing the crystalline structure of the carrier substrate 20 to develop significantly, so that the The composite structure 1 is compatible with the high temperature heat treatment required for subsequent fabrication of components on the thin layers 10 .

The method of the invention may comprise a second step h) of epitaxially growing an additional layer 10' of monocrystalline silicon carbide on the thin layer 10 of the composite structure 1 (FIG. 2g). Such steps may be performed when a relatively thick (typically about 5 to 50 microns) useful layer 100 is required for fabrication of the component.

The temperature applied in step h) can be selected to limit the stress induced in the useful layer 100 (which corresponds to the combination of the thin layer 10 and the additional layer 10') due to the composite structure 1 .

Finally, the manufacturing method may include a step of trimming the remainder 111' of the donor substrate for the purpose of reusing it as the initial substrate 1 or as the donor substrate 111. Such conditioning steps are based on one or more treatments of surface 110'a (FIG. 2e), such as surface or edge chemical mechanical polishing, and/or mechanical conditioning, and/or dry or wet chemical etching.

The thickness of the donor layer 110 formed in step b) is preferably defined so that the remaining portion 111 ′ of the donor substrate 111 can be reused as the donor substrate 111 at least twice.

When the conversion layer 13 is present, care is taken to keep this layer intact, in other words always have a portion of the donor layer 110 remaining on the remainder 111' of the donor substrate. In this way, when the portion of the donor layer 110 is insufficient for fabricating the composite structure 1, only the step of epitaxially growing the donor layer 110 is required, and the previous step of growing the conversion layer 13 is not required.

Example: According to a non-limiting and exemplary embodiment, the initial substrate 11 provided in step a) of the manufacturing method is a wafer made of 4H polytype c-SiC, which is relative to the <11-20> axis The orientation is 4.0˚±0.5˚, the diameter is 150 mm, and the thickness is 350 µm.

Before step b) of epitaxially growing the c-SiC donor layer 110, a conventional RCA cleaning procedure (standard cleaning 1 + standard cleaning 2) may be performed on the initial substrate 11, followed by peroxysulfuric acid (a mixture of sulfuric acid and hydrogen peroxide) mixture), followed by HF (hydrofluoric acid).

The epitaxial growth is carried out in an epitaxial chamber at a temperature of 1650°C, and its precursor can be, for example, silane (SiH4), propane (C3H8) or ethylene (C2H4), and the grown c - SiC donor layer 110 has a thickness of 30 microns (growth rate: 10 microns/hour). The donor layer has a BPD defect density of about 1/cm ² .

Hydrogen ions were implanted through the free surface of the donor layer 110 with an energy of 150 keV and a dose of 6 ^E 16 H+/cm ² . Thereby a buried brittle plane 12 is formed in the initial substrate 11 at a depth of about 800 nm.

An RCA cleaning procedure + peroxysulfuric acid is performed on the donor body substrate 111 to remove potential contaminants from the free side of the donor body layer 110.

DLI-CVD deposition on the donor layer 110 at a temperature of 800°C with a disilabutane (DSB) precursor at a pressure of 50 Torr for 60 minutes to achieve a thickness of the carrier layer 20' of at least 150 microns . Under these conditions, the carrier layer 20' is deposited in the form of an amorphous SiC matrix and contains reaction by-products from the deposition precursors.

The stack 211 is then subjected to a tempering at a temperature of 1000° C. for 50 minutes, during which the separation occurs at the buried brittle plane. Upon completion of this separation step e), the intermediate composite structure 1' formed by the thin layer 10 and the carrier layer 20' is separated from the remainder of the donor substrate 111'.

The intermediate composite structure 1 ′ is then subjected to a crystallization heat treatment at a temperature of 1200° C. under an argon atmosphere for 1 hour to form the p-SiC carrier substrate 20 of the composite structure 1 .

As an alternative, the separation step and the crystallization step can be carried out during the same heat treatment, for example at a temperature of 1200°C in a neutral atmosphere.

Mechanical trimming of the backside of the carrier substrate 20 to remove about 15 to 30 microns can remove cracks and structural defects caused by crystallization of the SiC matrix.

One or more chemical mechanical polishing operations are then performed to restore the surface roughness of the thin layer 10 and the surface roughness of the backside of the carrier substrate 20, followed by conventional cleaning procedures.

Of course, the present invention is not limited to the described embodiments and examples, and various changes made to the examples all fall within the scope defined by the scope of the patent application of the present application.

1: Composite structure 1': Intermediate composite structure 10: Thin layer 10': extra layer 10a: Free surface 11: Initial substrate 11': rest of initial substrate 11a: Front 11b: Back 12: Embedded brittle plane 13: Single crystal conversion layer 20: Carrier substrate 20': carrier layer 20b: Back 21: middle layer 22: Extra Layers 100: useful layer 110: Donor layer 110'a: Surface 111: Donor Substrate 111’: Remainder 211: Stacked

Further features and advantages of the present invention will be more clearly explained in the following section on embodiments of the invention, embodiments are provided with reference to the accompanying drawings, wherein: FIG. 1 illustrates a composite structure fabricated according to the fabrication method of the present invention; 2a to 2g illustrate the steps of a manufacturing method according to the present invention; 3a and 3b illustrate the steps of a manufacturing method according to the present invention.

Claims (13)

A method for producing a composite structure (1) comprising a thin layer (10) of monocrystalline silicon carbide disposed on a carrier substrate (20) of silicon carbide, the method comprising: a) the step of providing an initial substrate (11) of monocrystalline silicon carbide, b) the step of epitaxially growing a donor layer (110) of monocrystalline silicon carbide on the initial substrate (11) to form a donor substrate (111), the donor layer (110) having a crystal defect density lower than the The crystal defect density of the initial substrate (11), c) the step of implanting light species ions into the donor layer (110) to form a buried brittle plane (12) defining the thin layer (10), d) the step of carrying out direct injection liquid chemical vapor deposition at a temperature below 1100°C to form a carrier layer (20') directly on the free surface of the donor layer (110), the carrier layer (20') formed from an at least partially amorphous SiC matrix, e) a step of separating along the buried brittle plane (12), thereby forming an intermediate composite structure (1') comprising the thin layer (10) on the carrier layer (20') on the one hand, and an intermediate composite structure (1') comprising the thin layer (10) on the other hand forming the remainder (111') of the donor substrate, f) a step of applying a heat treatment to the intermediate composite structure (1') at a temperature between 1000°C and 1800°C to crystallize the carrier layer (20') and form the polycrystalline carrier substrate (20) ), g) the step of mechanically and/or chemically treating the composite structure (1), said treatment being applied to the free side of the carrier substrate (20), ie the backside of the composite structure (1), and/or the The free face of the thin layer (10), ie the front face of the composite structure (1). A method as claimed in claim 1, wherein said deposition step d) is carried out at a temperature between 100°C and 700°C, or even preferably at a temperature between 200°C and 600°C. A method as claimed in claim 1 or 2, wherein said deposition step d) is carried out at a pressure between 1 Torr and 500 Torr. The method of any one of claims 1 to 3, wherein the precursor used during said deposition step d) is selected from polysilylethylene and disilabutane. The method of any one of claims 1 to 4, wherein, at the end of said deposition step d), the carrier layer (20') has a thickness greater than or equal to 10 microns, even greater than or equal to 50 microns, or even Greater than or equal to 100 microns, or even greater than or equal to 200 microns. A method as claimed in any one of claims 1 to 5, wherein chemical etching, mechanical grinding and/or chemical mechanical polishing are applied to the free face of the carrier layer (20') between steps d) and e). The method of any one of claims 1 to 6, wherein step a) comprises forming a single crystal conversion layer (13) on the initial substrate (11) to displace the bottom surface of the initial substrate (11) (basal plane dislocation) defects are converted into threading edge dislocation defects. The method of any one of claims 1 to 7, wherein the epitaxial growth step b) is carried out at a temperature higher than 1200°C, preferably at a temperature between 1500°C and 1650°C . The method of any one of claims 1 to 8, wherein the separating step e) is carried out at a temperature higher than the deposition temperature of step d). A method as claimed in any one of claims 1 to 8, wherein said separating step e) occurs during said deposition step d), preferably at the end of step d). The method of any one of claims 1 to 9, wherein said separation step e) and said crystallization step f) are performed during the same thermal treatment. A method as claimed in any one of claims 1 to 11, wherein step g) comprises simultaneous chemical mechanical polishing of the front and back surfaces of the composite structure (1). The method of any one of claims 1 to 12, further comprising the step of trimming the remainder (111') of the donor substrate for the purpose of reusing it as an initial substrate or a donor substrate.

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