GB2462014A - Landing pad structure to reduce impedance mismatch - Google Patents

Landing pad structure to reduce impedance mismatch Download PDF

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Publication number
GB2462014A
GB2462014A GB0915781A GB0915781A GB2462014A GB 2462014 A GB2462014 A GB 2462014A GB 0915781 A GB0915781 A GB 0915781A GB 0915781 A GB0915781 A GB 0915781A GB 2462014 A GB2462014 A GB 2462014A
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GB
United Kingdom
Prior art keywords
vias
package substrate
layers
stack
pcb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0915781A
Other versions
GB0915781D0 (en
GB2462014B (en
Inventor
Amarjit Singh Bhandal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0709792A external-priority patent/GB0709792D0/en
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Publication of GB0915781D0 publication Critical patent/GB0915781D0/en
Publication of GB2462014A publication Critical patent/GB2462014A/en
Application granted granted Critical
Publication of GB2462014B publication Critical patent/GB2462014B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1905—Shape
    • H01L2924/19051—Impedance matching structure [e.g. balun]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Abstract

A PCB or package substrate structure comprises a plurality of interleaved metal and dielectric layers (figure 1, not shown) forming a stack and a plurality of micro vias connecting adjacent pairs of metal layers. A landing pad provides a conductive path between the vias, the landing pad being formed with rectangular slots lying along part of the length of a chord across the pad. The slots are parallel to each other and lie in a horizontal plane parallel to the layers of the stack, defining a generally s-shaped conductive path between the vias. This pad structure reduces excess capacitance in the vicinity of the vias and allows better impedance matching to the standard 50 Ohm impedance of the traces. The PCB or package substrate may be used in a high frequency serial-deserializer.

Description

OPTIMIZATION OF ORGANIC PACKAGING INTERCONNECT FOR GIGABIT
SIGNALLING
FIELD OF THE INVENTION
The present invention relates to multi-layered substrates and, more particularly, to an electronic signal interconnect path in said structure and a method of reducing impedance mismatch therein.
BACKGROUND OF THE INVENTION
Printed circuit boards (PCBs) and package substrates used to imp]ement the interconnect between e]ectronic devices generally consist of layers of conducting sheets sandwiched between layers of non-conducting (dielectric) sheets. Signals are transferred between devices by means of conducting strips of metal (traces) etched into the conducting sheets and vertical cylindrically shaped (in general) conducting components (vias, balls, bumps) placed through the dielectric layers to connect the traces. At the connection points between the vertical components (henceforth to be referred to as vias) and the traces, landing pads are etched into the conducting sheets to ensure the connection points between the traces and vias can cope with manufacturing tolerances.
By convention most high speed electronic signal interconnects are required to have a characteristic impedance of 50 Ohms.
Layered PCB and package substrate materials and their stack-ups are chosen to make it easy to implement 50 Ohm traces. However, the same is not true for the vias, which tend to have an excess capacitance due to coupling between their pads and the conducting layers above or below. This results in their characteristic impedance being below 50 Ohms. The effect of the change in impedance on a propagating signal is to cause the signal to reflect back towards its source rather than continue on towards its destination. The larger the difference in impedance between the traces and the vias, the greater the level of reflected signal (and corresponding reduction in transmitted signal)
SUMMARY OF THE INVENTION
The present invention provides a PCB or package substrate structure that reduces the level of excess capacitance in the vicinity of the vias, and so causes their characteristic impedance to be closer to the 50 Ohm value implemented for the traces. Accordingly, there is provided a PCB or package structure comprising: a number of metal layers interleaved between a further number of dielectric layers to form a stack; a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers; and a landing pad having cut-out regions for providing an s-shaped conduction path between the vias, each said region formed substantially in the shape of a rectangular slot lying along part of the length of an associated chord across said landing pad, said rectangular slot shaped cut-out regions lying parallel to each other along their length in a horizontal plane lying parallel to the layers of the stack.
Advantageously, the present invention reduces the amount of impedance mismatch between the traces and vias in the POE or package structure, thereby reducing the level of reflected signal and increasing signal transmission, without compromising mechanical reliability.
Advantageously, the present invention provides an improvement of one to two orders of magnitude in bit error rate (BER) when utilized in a high frequency Serial-Deserializer (SERDES) Specific embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a schematic diagram of a cross-section through a organic build-up layered package substrate in accordance with a preferred embodiment of the invention; Figures 2a to 2e are schematic diagrams of cross-sections through layers lOm to the BOT layer of the layered package substrate shown in Figure 1 in accordance with a preferred embodiment of the invention; Figure 3a a graphical diagram showing a comparison of the die-end reflection coefficient for a short net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figure 3b is a graphical diagram showing a comparison of the die-end reflection coefficient for a medium net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figure 3c is a graphical diagram showing a comparison of the die-end reflection coefficient for a long net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figures 4a is a graphical diagram showing a comparison of the transmission coefficient for a short net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figures 4b is a graphical diagram showing a comparison of the transmission coefficient for a medium net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; Figures 4c is a graphical diagram showing a comparison of the transmission coefficient for a long net, for an organic build-up layered package substrate formed according to conventional techniques and two preferred embodiments of the present invention; and Figure 5 is a diagram showing an alternate geometry for a patterned landing pad according to a preferred embodiment of the invention.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION
The present invention concerns a technique and structure for reducing the level of excess capacitance in PCB and layered package substrates due to coupling between landings pads and the conducting layers above or below them.
With reference to Figure 1, which shows a simplified cross-section through a layered package substrate structure, a number of conducting sheets (metal layers) are interleaved between a number of non-conducting sheets (dielectric layers) to form a first stack. A second stack is formed from a further number of metal layers interleaved between a further number of dielectric layers. Sandwiched in between the first and second stacks is an organic build-up core layer with a plated through hole (PTH) via connecting the lower most metal layer of the first stack with the upper most metal layer of the second stack. Pairs of adjacent metal layers in the second stack are connected to each other by micro-vias. The micro-vias are positioned in a staggered arrangement in relation to each other, so that vertically adjacent micro-vias in the stack do not coincide in their alignment.
Figures 2b and 2d show how vertically adjacent micro-vias may be coupled to form an interconnect path through the layered package substrate in accordance with alternate embodiments of invention.
As seen from Figure 1 and Figure 2a-e, the cut-out pads in the dielectric layers have the same, or a substantially similar, cross-section as that of the landing pad of the structure in layer 1OM.
Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the scope of the invention as defined by the appended claims.

Claims (3)

  1. WHAT IS CLAIMED IS: 1. A PCB or package substrate comprising: a number of metal layers interleaved between a further number of dielectric layers to form a stack; a plurality of micro-vias, each micro-via connecting a pair of adjacent metal layers; and a landing pad having cut-out regions for providing an s-shaped conduction path between the vias, each said region formed substantially in the shape of a rectangular slot lying along part of the length of an associated chord across said landing pad, said rectangu]ar s]ot shaped cut-out regions]ying paralle] to each other along their length in a horizontal plane lying parallel to the layers of the stack.
  2. 2. A PCB or package substrate substantially as hereinbefore described with reference to Figures 2a to 2e of the drawings.
  3. 3. A PCB or package substrate substantially as hereinbefore described with reference to Figure 5 of the drawings.
GB0915781A 2007-05-22 2009-09-09 Optimization of organic packaging interconnect for gigabit signalling Active GB2462014B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0709792A GB0709792D0 (en) 2007-05-22 2007-05-22 Optimization of organic packaging interconnect for gigabit signalling
GB0716790A GB2449508B (en) 2007-05-22 2007-08-31 Optimization of organic packaging interconnect for gigabit signalling

Publications (3)

Publication Number Publication Date
GB0915781D0 GB0915781D0 (en) 2009-10-07
GB2462014A true GB2462014A (en) 2010-01-27
GB2462014B GB2462014B (en) 2010-06-09

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Family Applications (1)

Application Number Title Priority Date Filing Date
GB0915781A Active GB2462014B (en) 2007-05-22 2009-09-09 Optimization of organic packaging interconnect for gigabit signalling

Country Status (1)

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GB (1) GB2462014B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060207790A1 (en) * 2005-03-15 2006-09-21 Jayoung Choi Bonding pads having slotted metal pad and meshed via pattern

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060207790A1 (en) * 2005-03-15 2006-09-21 Jayoung Choi Bonding pads having slotted metal pad and meshed via pattern

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate

Also Published As

Publication number Publication date
GB0915781D0 (en) 2009-10-07
GB2462014B (en) 2010-06-09

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