CN220545190U - PCB structure for optimizing high-speed signal buried hole impedance - Google Patents
PCB structure for optimizing high-speed signal buried hole impedance Download PDFInfo
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- CN220545190U CN220545190U CN202321988010.1U CN202321988010U CN220545190U CN 220545190 U CN220545190 U CN 220545190U CN 202321988010 U CN202321988010 U CN 202321988010U CN 220545190 U CN220545190 U CN 220545190U
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 104
- 239000011889 copper foil Substances 0.000 claims abstract description 104
- 238000005553 drilling Methods 0.000 claims description 4
- 230000001808 coupling effect Effects 0.000 abstract description 7
- 150000003071 polychlorinated biphenyls Chemical group 0.000 description 21
- 238000000034 method Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000035772 mutation Effects 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- -1 layers of PCBs Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The utility model discloses a PCB structure for optimizing high-speed signal buried hole impedance, which comprises a multi-layer PCB, wherein the multi-layer PCB comprises a plurality of copper foil layers which are sequentially laminated, laser holes are arranged between the copper foil layers positioned on the outer layer, buried holes are arranged between the copper foil layers positioned on the inner layer, hollowed-out areas are arranged on the copper foil layers adjacent to hole plates of the buried holes, and the hollowed-out areas are opposite to the hole plates of the buried holes. According to the utility model, the hollowed-out area is arranged on the copper foil layer adjacent to the hole disc of the buried hole, and the hollowed-out area is opposite to the hole disc of the buried hole, so that the coupling effect between the hole disc of the buried hole and the adjacent copper foil layer can be reduced, the impedance of the buried hole is improved, and the influence on the quality of high-speed signals is reduced.
Description
Technical Field
The utility model relates to the technical field of PCBs, in particular to a PCB structure for optimizing high-speed signal buried hole impedance.
Background
Printed circuit boards (PrintedCircuitBoard, PCB boards), also known as printed circuit boards, printed wiring boards, are an important component of the physical support and signal transmission of electronic products. With the continuous development of electronic technology, the design and manufacturing technology of PCB boards are advancing, wherein the application of HDI process design is becoming wider and wider.
The HDI process is a High Density Interconnect (HDI) process that achieves high density wiring and connection in a small space of a PCB board by employing a laser hole and buried hole structure. The laser holes are connecting holes formed between the plate layers by laser drilling, and the buried holes are connecting holes formed inside the plate layers by electroplating or the like. The combination of the two structures enables the HDI technology to realize finer wiring and connection on the high-density PCB, thereby improving the signal transmission performance and stability of the PCB.
However, when the substrate density of the PCB board is high, the use of HDI process design may face some challenges. Among them, the coupling effect between the hole plate of the buried hole and the adjacent copper foil layer is an important problem. Because the hole disc of the buried hole penetrates into the plate layer, a coupling phenomenon can be generated between the hole disc of the buried hole and the adjacent copper foil layer, and therefore a capacitor is formed. This capacitive effect pulls down the impedance of the buried via, resulting in an increase in the abrupt impedance change in the signal path, thereby adversely affecting the quality of the high-speed signal. When the high-speed signal is transmitted through the buried hole, the problems of delay, distortion or signal loss and the like of the high-speed signal can be caused due to the fact that the impedance mutation is large. The performance and use effect of the electronic products are affected by the occurrence of these problems, so that corresponding measures need to be taken for optimization and solution.
Disclosure of Invention
In order to solve the problem that the impedance mutation is large when a high-speed signal is buried in the prior art, the utility model provides a PCB structure for optimizing the buried impedance of the high-speed signal.
The technical scheme of the utility model is as follows:
the utility model provides an optimize PCB board structure of high-speed signal buried hole impedance, includes the multilayer PCB board, the multilayer PCB board includes the multilayer copper foil layer that stacks gradually, is located the skin be provided with the laser hole between the copper foil layer, be located the inlayer be provided with between the copper foil layer and bury the hole, with be provided with on the copper foil layer adjacent of the hole dish of burying the hole digs the empty region, dig the region just to the hole dish of burying the hole.
According to the PCB structure for optimizing the high-speed signal buried hole impedance, the diameter of the hollowed-out area is not smaller than the diameter of the buried hole.
According to the PCB structure for optimizing the high-speed signal buried hole impedance, the diameter of the hollowed-out area is 0.2mm larger than the diameter of the buried hole.
According to the PCB structure for optimizing high-speed signal buried hole impedance, the multi-layer PCB is an eight-layer PCB and comprises eight copper foil layers which are sequentially laminated.
According to the PCB structure for optimizing high-speed signal buried hole impedance, the laser holes are formed between the first copper foil layer and the second copper foil layer, and between the second copper foil layer and the third copper foil layer.
According to the PCB structure for optimizing high-speed signal buried hole impedance, the laser holes are formed between the sixth copper foil layer and the seventh copper foil layer, and between the seventh copper foil layer and the eighth copper foil layer.
According to the PCB structure for optimizing high-speed signal buried hole impedance, the buried holes are formed between the third copper foil layer and the sixth copper foil layer, and the hollowed-out areas opposite to the hole plates buried holes are formed on the second copper foil layer and the seventh copper foil layer.
According to the PCB structure for optimizing high-speed signal buried hole impedance, the upper hole plate of the buried hole is connected with the third layer of copper foil layer, the lower hole plate of the buried hole is connected with the sixth layer of copper foil layer, and the buried hole is not connected with the fourth layer of copper foil layer and the fifth layer of copper foil layer.
According to the PCB structure for optimizing high-speed signal buried hole impedance, through holes are formed between the first copper foil layer and the second copper foil layer, and between the seventh copper foil layer and the eighth copper foil layer.
According to the PCB structure for optimizing the high-speed signal buried hole impedance, the buried holes are formed through mechanical drilling.
Compared with the prior art, the utility model has the beneficial effects that:
according to the PCB structure for optimizing the high-speed signal buried hole impedance, the hollowed-out area is arranged on the copper foil layer adjacent to the hole disc of the buried hole and is opposite to the hole disc of the buried hole, so that the coupling effect between the hole disc of the buried hole and the adjacent copper foil layer can be reduced, the buried hole impedance is improved, and the influence on the high-speed signal quality is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic structural diagram of a PCB structure for optimizing high-speed signal buried via impedance according to the present utility model;
fig. 2 is a schematic structural diagram of a PCB structure with eight layers of high-speed signal buried vias in the prior art.
In the drawing of the figure,
1. a copper foil layer; 2. a laser hole; 3. burying holes; 4. digging out the area; 5. and a through hole.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the utility model is further described in detail below with reference to the accompanying drawings and embodiments. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, it is stated that the embodiments described below are only for explaining the present utility model and are not intended to limit the present utility model.
It should be noted that, the terms "disposed," "connected," and the like should be understood in a broad sense, and for example, may be fixedly connected, detachably connected, or integrated; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The direction orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship which is commonly put when the product of the application is used, or the orientation or positional relationship which is commonly understood by those skilled in the art, or the orientation or positional relationship which is commonly put when the product of the application is used, only for convenience of description of the application and simplification of description, and is not intended to indicate or imply that the device or element to be referred must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the application. The terms "first," "second," "third," "fourth," "fifth," "sixth," "seventh," "eighth" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features. "multilayer" means two or more layers unless specifically defined otherwise.
Referring to fig. 1, the embodiment provides a PCB structure for optimizing high-speed signal buried hole impedance, which comprises a multi-layer PCB board, wherein the multi-layer PCB board comprises a plurality of copper foil layers 1 laminated in sequence, laser holes 2 are arranged between the copper foil layers 1 positioned on the outer layer, buried holes 3 are arranged between the copper foil layers 1 positioned on the inner layer, the buried holes 3 are formed by mechanical drilling, a hollowed-out area 4 is arranged on the copper foil layer 1 adjacent to a hole disc of the buried holes 3, the hollowed-out area 4 is opposite to the hole disc of the buried holes 3, and the diameter of the hollowed-out area 4 is not smaller than the diameter of the hole disc of the buried holes 3. According to the utility model, the hollowed-out area 4 is arranged on the copper foil layer 1 adjacent to the hole disc of the buried hole 3, and the hollowed-out area 4 is opposite to the hole disc of the buried hole 3, so that the coupling effect between the hole disc of the buried hole 3 and the adjacent copper foil layer 1 can be reduced, the impedance of the buried hole 3 is improved, and the influence on the quality of high-speed signals is reduced.
Referring to fig. 1, the following describes in detail a PCB structure for optimizing high-speed signal buried hole impedance by taking the most common eight-layer PCB as an example:
when the multilayer PCB board is an eight-layer PCB board, including eight copper foil layers 1 laminated in proper order, between first layer copper foil layer 1 and second layer copper foil layer 1, between second layer copper foil layer 1 and third layer copper foil layer 1, between sixth layer copper foil layer 1 and seventh layer copper foil layer 1, between seventh layer copper foil layer 1 and eighth layer copper foil layer 1 all be provided with laser hole 2, between first layer copper foil layer 1 and second layer copper foil layer 1, between seventh layer copper foil layer 1 and eighth layer copper foil layer 1 all be provided with through-hole 5, be provided with between third layer copper foil layer 1 and sixth layer copper foil layer 1 and bury hole 3, the last hole dish of burying hole 3 is connected with third layer copper foil layer 1, the lower hole dish of burying hole 3 is connected with sixth layer copper foil layer 1, and bury hole 3 and be not connected with fourth layer copper foil layer 1 and fifth layer copper foil layer 1. Wherein, the laser holes 2 between the first copper foil layer 1 and the second copper foil layer 1 and the laser holes 2 between the seventh copper foil layer 1 and the eighth copper foil layer 1 are symmetrically arranged with the center of the buried hole 3; the laser holes 2 between the second copper foil layer 1 and the third copper foil layer 1 and the laser holes 2 between the sixth copper foil layer 1 and the seventh copper foil layer 1 are symmetrically arranged with the center of the buried hole 3; the through holes 5 between the first copper foil layer 1 and the second copper foil layer 1 and the through holes 5 between the seventh copper foil layer 1 and the eighth copper foil layer 1 are symmetrically arranged with the center of the buried hole 3. In addition, the second copper foil layer 1 and the seventh copper foil layer 1 are provided with the hollowed-out area 4 which is opposite to the hole disc of the buried hole 3, and the diameter of the hollowed-out area 4 is 0.2mm larger than the diameter of the hole disc of the buried hole 3 in consideration of the layer deviation influence, so that the coupling effect between the hole disc of the buried hole 3 and the adjacent copper foil layer 1 can be reduced to the greatest extent, and the layer deviation influence can be avoided.
Fig. 2 shows a conventional eight-layer high-speed signal buried hole PCB structure, in which the buried hole 3 disposed between the third copper foil layer 1 and the sixth copper foil layer 1 is a mechanical drill, so that the hole disc of the unavoidable buried hole 3 is relatively large, so that the hole disc of the buried hole 3 and the adjacent copper foil layers 1 (i.e., the second copper foil layer 1 and the seventh copper foil layer 1) may have a coupling effect, and the impedance of the buried hole 3 is lowered, thereby affecting the quality of the high-speed signal. In the utility model, the hollowed-out area 4 is arranged on the copper foil layer 1 (namely the second copper foil layer 1 and the seventh copper foil layer 1) adjacent to the hole disc of the buried hole 3, and the hollowed-out area 4 is opposite to the hole disc of the buried hole 3, so that the coupling effect between the hole disc of the buried hole 3 and the adjacent copper foil layer 1 can be reduced, the impedance of the buried hole 3 is improved, and the influence on the quality of high-speed signals is reduced.
It should be understood that the present utility model is applicable to eight-layer PCBs, as well as other layers of PCBs, and the present utility model is not limited thereto.
It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.
While the utility model has been described above with reference to the accompanying drawings, it will be apparent that the implementation of the utility model is not limited by the above manner, and it is within the scope of the utility model to apply the inventive concept and technical solution to other situations as long as various improvements made by the inventive concept and technical solution are adopted, or without any improvement.
Claims (10)
1. The utility model provides an optimize PCB board structure of high-speed signal buried hole impedance, includes the multilayer PCB board, the multilayer PCB board includes the multilayer copper foil layer that stacks gradually, is located the skin be provided with the laser hole between the copper foil layer, be located the inlayer be provided with between the copper foil layer and bury the hole, its characterized in that with it is adjacent to bury the hole dish of hole be provided with the region of digging on the copper foil layer, the region of digging just to bury the hole dish of hole.
2. The PCB structure of claim 1, wherein the hollowed-out area has a diameter not less than the diameter of the hole disc of the buried hole.
3. The PCB structure of claim 1, wherein the hollowed-out area has a diameter that is 0.2mm greater than the diameter of the hole-disc of the buried hole.
4. The PCB structure of claim 1, wherein the multi-layer PCB is an eight-layer PCB comprising eight copper foil layers laminated in sequence.
5. The PCB structure of claim 4, wherein the laser holes are disposed between the first and second copper foil layers and between the second and third copper foil layers.
6. The PCB structure of claim 4, wherein the laser holes are disposed between the sixth layer of copper foil and the seventh layer of copper foil, and between the seventh layer of copper foil and the eighth layer of copper foil.
7. The PCB structure of claim 4, wherein the buried vias are disposed between the third and sixth copper foil layers, and the second and seventh copper foil layers are provided with the hollowed-out regions directly opposite to the pads of the buried vias.
8. The PCB structure of claim 7, wherein the upper pad of the buried via is connected to the third layer of the copper foil layer, the lower pad of the buried via is connected to the sixth layer of the copper foil layer, and the buried via is not connected to the fourth layer of the copper foil layer and the fifth layer of the copper foil layer.
9. The PCB structure of claim 4, wherein a through hole is formed between the first and second copper foil layers and between the seventh and eighth copper foil layers.
10. The PCB structure of claim 1 wherein the buried vias are formed by mechanical drilling.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321988010.1U CN220545190U (en) | 2023-07-26 | 2023-07-26 | PCB structure for optimizing high-speed signal buried hole impedance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321988010.1U CN220545190U (en) | 2023-07-26 | 2023-07-26 | PCB structure for optimizing high-speed signal buried hole impedance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220545190U true CN220545190U (en) | 2024-02-27 |
Family
ID=89966798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202321988010.1U Active CN220545190U (en) | 2023-07-26 | 2023-07-26 | PCB structure for optimizing high-speed signal buried hole impedance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN220545190U (en) |
-
2023
- 2023-07-26 CN CN202321988010.1U patent/CN220545190U/en active Active
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