GB2449508B - Optimization of organic packaging interconnect for gigabit signalling - Google Patents

Optimization of organic packaging interconnect for gigabit signalling

Info

Publication number
GB2449508B
GB2449508B GB0716790A GB0716790A GB2449508B GB 2449508 B GB2449508 B GB 2449508B GB 0716790 A GB0716790 A GB 0716790A GB 0716790 A GB0716790 A GB 0716790A GB 2449508 B GB2449508 B GB 2449508B
Authority
GB
United Kingdom
Prior art keywords
gigabit
signalling
optimization
organic packaging
packaging interconnect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
GB0716790A
Other versions
GB0716790D0 (en
GB2449508A (en
Inventor
Amarjit Singh Bhandal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Ltd
Original Assignee
Texas Instruments Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Ltd filed Critical Texas Instruments Ltd
Publication of GB0716790D0 publication Critical patent/GB0716790D0/en
Publication of GB2449508A publication Critical patent/GB2449508A/en
Priority to GB0915781A priority Critical patent/GB2462014B/en
Application granted granted Critical
Publication of GB2449508B publication Critical patent/GB2449508B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/113—Via provided in pad; Pad over filled via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
GB0716790A 2007-05-22 2007-08-31 Optimization of organic packaging interconnect for gigabit signalling Active GB2449508B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
GB0915781A GB2462014B (en) 2007-05-22 2009-09-09 Optimization of organic packaging interconnect for gigabit signalling

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB0709792A GB0709792D0 (en) 2007-05-22 2007-05-22 Optimization of organic packaging interconnect for gigabit signalling

Publications (3)

Publication Number Publication Date
GB0716790D0 GB0716790D0 (en) 2007-10-10
GB2449508A GB2449508A (en) 2008-11-26
GB2449508B true GB2449508B (en) 2009-12-23

Family

ID=38234865

Family Applications (2)

Application Number Title Priority Date Filing Date
GB0709792A Ceased GB0709792D0 (en) 2007-05-22 2007-05-22 Optimization of organic packaging interconnect for gigabit signalling
GB0716790A Active GB2449508B (en) 2007-05-22 2007-08-31 Optimization of organic packaging interconnect for gigabit signalling

Family Applications Before (1)

Application Number Title Priority Date Filing Date
GB0709792A Ceased GB0709792D0 (en) 2007-05-22 2007-05-22 Optimization of organic packaging interconnect for gigabit signalling

Country Status (1)

Country Link
GB (2) GB0709792D0 (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232564B1 (en) * 1998-10-09 2001-05-15 International Business Machines Corporation Printed wiring board wireability enhancement
US6889367B1 (en) * 2003-02-13 2005-05-03 Hewlett-Packard Development Company, L.P. Differential via pair impedance verification tool
US20060108143A1 (en) * 2004-11-24 2006-05-25 Jimmy Hsu Signal transmission structure and circuit substrate thereof
WO2006056473A2 (en) * 2004-11-29 2006-06-01 Fci Improved matched-impedance surface-mount technology footprints
US20060158280A1 (en) * 2005-01-14 2006-07-20 Uei-Ming Jow High frequency and wide band impedance matching via
US20060197625A1 (en) * 2005-03-03 2006-09-07 Nec Corporation Transmission line and wiring forming method
US20060207790A1 (en) * 2005-03-15 2006-09-21 Jayoung Choi Bonding pads having slotted metal pad and meshed via pattern

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6232564B1 (en) * 1998-10-09 2001-05-15 International Business Machines Corporation Printed wiring board wireability enhancement
US6889367B1 (en) * 2003-02-13 2005-05-03 Hewlett-Packard Development Company, L.P. Differential via pair impedance verification tool
US20060108143A1 (en) * 2004-11-24 2006-05-25 Jimmy Hsu Signal transmission structure and circuit substrate thereof
WO2006056473A2 (en) * 2004-11-29 2006-06-01 Fci Improved matched-impedance surface-mount technology footprints
US20060158280A1 (en) * 2005-01-14 2006-07-20 Uei-Ming Jow High frequency and wide band impedance matching via
US20060197625A1 (en) * 2005-03-03 2006-09-07 Nec Corporation Transmission line and wiring forming method
US20060207790A1 (en) * 2005-03-15 2006-09-21 Jayoung Choi Bonding pads having slotted metal pad and meshed via pattern

Also Published As

Publication number Publication date
GB0716790D0 (en) 2007-10-10
GB0709792D0 (en) 2007-06-27
GB2449508A (en) 2008-11-26

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