GB2457683A - A CMOS operational amplifier with chopper stabilization and a switched output - Google Patents
A CMOS operational amplifier with chopper stabilization and a switched output Download PDFInfo
- Publication number
- GB2457683A GB2457683A GB0803135A GB0803135A GB2457683A GB 2457683 A GB2457683 A GB 2457683A GB 0803135 A GB0803135 A GB 0803135A GB 0803135 A GB0803135 A GB 0803135A GB 2457683 A GB2457683 A GB 2457683A
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- output
- operational amplifier
- stage
- chopper
- input
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C1/00—Amplitude modulation
- H03C1/36—Amplitude modulation by means of semiconductor device having at least three electrodes
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/005—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/38—Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers
- H03F3/387—Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only
- H03F3/393—Dc amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers with semiconductor devices only with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
- H03F3/45183—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H19/00—Networks using time-varying elements, e.g. N-path filters
- H03H19/004—Switched capacitor networks
Abstract
The input stage of a CMOS operational amplifier for use in a switched capacitor circuit is chopper stabilized by switches N13-N16 and N9-N12 so as to reduce the effect of flicker noise. Flicker noise (I/f noise) is normally reduced by using large area transistors which consume valuable IC area and which lower the amplifier bandwidth for a fixed supply current due to their parasitic capacitance. The dominant pole capacitances C1, C2 of the output stages act as low pass output filters for the chopper stabilized input stage. The switches N5,N7,N3,N8 allow the output stages to be switched into a high-impedance mode. This allows the elimination of a floating input switch (S1, figure 1) in switched capacitor circuits coupled to the amplifier output. It is difficult to drive floating switches effectively in circuits with low supply voltages.
Description
SWITCHED-MODE OPERATIONAL AMPLIFIER
The present invention relates to a switched mode operationai amplifier suitable for use in switched capacitance circuits.
It is well known that a number of switches in combination with a capacitor can be used to emulate a resistance. Circuits built using such simulated resistances are known as switched capacitor (SC) circuits. SC circuits are commonly used for signal processing applications such as filtering and analog-to-digital converters (ADCs) since strict matching requirements and calibration are not required. SC circuits provide accurate frequency responses as well as good linearity and dynamic range. Once the coefficients of an SC circuit are determined, its overall frequency response remains a function of the clocking or sampling frequency which is usually constant. SC circuits are easily implemented using CMOS tecimology. In addition to switches and capacitance, a basic building block of SC circuits is the operational amplifier or opamp. A simple integrator constructed as an SC circuit is illustrated in Figure 1.
In order to reduce power consumption of CMOS circuits, the power supply voltage (Vdd) has been reduced. However, as Vdd is reduced, a point is reached where the switches in the circuit cannot be turned fully on and off. With reference for example to Figure 1, switch Si is effectively a "floating" switch as neither the source nor drain are held at Vdd or Vss. As the source and/or drain voltage approaches Vdd (or ground), there is not enough of a voltage differential with the gate voltage to properly switch Si on and off. Under these conditions, SC circuits can fail to operate as required. Two methods to mitigate this problem are 1) the use of voltage multipliers to increase the Vdd that generates the clocking signals to the switches and 2) special processes that provide low VT devices for the switches.
However, a possibly more attractive option is the use of switched-opamps (or switched-mode opamps) which eliminate the floating switches altogether. The switched opamp principle is described in "Switched-Opamp: An Approach to Realize Full CMOS Switched-Capacitor Circuits at Very Low Power Supply Voltages", Jan Crols and Michel Steyaert, IEEE Journal of Solid-State Circuits, Vol. 29, No 8, August 1994.
The input yin to switch Si of the circuit of Figure 1 will be provided by the output of another opamp. The output of that opamp appears to be floating when the switch Si is off. By moving switch Si into the output stage of the opalnp, the switch can be connected to a fixed voltage, i.e., Vss, allowing it to be turned fully on an off. Such an arrangement is illustrated in Figure 2. A first gain stage of the amplifier comprises a conventional long tail pair (P2, P5, P6, Ni, N2). The output stage comprises current gain transistors N4 and N6 with effective high impedance transistors P3 and P4.
Transistor P1 provides current mirroring for P2 to P4, with a constant current lb. Capacitors Cl and C2 provide domin2nt pole compensation to enhance stability.
Transistor pairs N5, N7 and N3, N8 are switched by a clock signal CK (the clock signal applied to Sl in the circuit of Figure 1) such that the output of the opamp that is supplied to one side of the capacitance (CA in the circuit of Figure 1) satisfies the requirements of the SC circuit; i.e., preserves the proper functionality.
Considering further the output stage of the circuit of Figure 2, it is noted that the sources of switched transistors N3 and N5 are connected to ground. The sources of switched transistors N7 and N8 are close to ground under normal operation. As such, the switched transistors can be turned fully on and fully off. An advantageous "side effect" of the switched opamp is that the output stages consume only half the power of the output stage of a continuous opamp, as current is drawn through the output transistors for only 50% of the time.
In SC filters and analogue to digital converters (ADCs) the signal to noise ratio (SNR) and dynamic range is limited by various noise sources including white noise and flicker (1/f) noise in the MOSFETs and integrated resistors. In the case of low frequency signals, e.g. signals in the region of 1-100Hz, flicker noise can be the dominant noise component. Considering a simple two-stage CMOS opamp such as the switched opainp of Figure 2, the input referred noise of the opainp is dominated by the flicker noise of the first stage: when the flicker noise present in the output stage is referred back to the input of the opamp, it must be divided by the gain of the first stage and is thus a small proportion of the total input referred noise. Whilst flicker noise can be reduced by increasing MOSFET device channel length and gate area, this can lead to a larger parasitic capacitance within the first stage of the opamp and a reduced operating bandwidth. To re-establish the original bandwidth, more current is required by the first stage to charge and discharge the parasitic capacitance more quickly and hence the overall power consumption increases. In any case, it is not desirable to increase device area It is known that 1/f noise can be reduced in opamps using chopper stabilization techniques. This approach is described in "A CMOS Chopper Amplifier", Christian C. Enz et al, IEEE Journal of Solid-State Circuits, Vol 22, No 3, June 1987. Chopper stabilisation involves placing a switch set at the input to an opamp, and operating the set so as to alternate the input signals applied to the differential inputs of the opamp at a relatively high frequency. The switch set or "chopper" effectively modulates the chopping signal with the input signal, upconverting the input signal to a first (and further) sideband at the chopping frequency. Flicker noise is added to the signal within the amplifier. An identical chopper is coupled to the differential outputs of the opainp.
This again modulates the signal at the chopping frequency, shifting the noise to the first sideband whilst shifling the wanted component back to its original low frequency. The output from the second chopper is low pass filtered to eliminate the (now high frequency) ificker noise. The ratio between the chopper frequency and the bandwidth of the LPF determine the amount of 1/f noise reduction. Figure 3 illustrates chopper stabilization applied to an opamp.
It is desirable to be able to integrate the chopping stabilisation and switched opamp techniques to provide an opamp suitable for use in SC circuits which presents only low levels of flicker noise.
According to a first aspect of the present invention there is provided an operational amplifier suitable for use in a switched capacitance circuit and comprising an input stage implementing chopper stabilisation, and an output stage implementing a switched mode.
Embodiments of the present invention provide ibr significant flicker noise reduction in a switched mode operational amplifier. Moreover, the low pass filtering required to achieve chopper stabilisation may be provided inherently by the switched output stage.
Said input stage may comprise a first chopper for chopping an input signal to the input stage at a chopping frequency, and a second chopper for chopping an output signal of the input stage at said first chopping signal. The second chopper is coupled between a gain device and an output device of the or each end of said input stage.
Said output stage may comprise for the or each end a miller capacitance performing stabilisation and low pass filtering of the output signal of the input stage.
Said output stage may comprise, for the or each end, a gain device and a switch connected at one end to said gain device and at the other end to a fixed potential, the switch being clocked in use at a switching frequency. The device may comprise, for the or each end, a switch coupled between an output of the input stage and an output of the second stage, the switch being switched in use at said switching frequency.
In a preferred embodiment of the invention, said input stage comprises a differential amplifier, each leg of the differential amplifier comprising a gain device in series with a load device. Said first chopper is coupled between differential signal inputs of the operational amplifier and differential inputs of the differential amplifier, and is configured in use to switch the differential input signals between said differential inputs at a chopping frequency, whilst said second chopper is coupled between said gain devices and said load devices and is configured in use to switch the outputs of the load devices between the inputs of the gain devices at said chopping frequency. The output stage comprises, for each leg, a gain device and a miller capacitance coupled between the output of the input stage and an output of the output stage, the miller capacitance being configured to perform low pass filtering of the output signal from the input stage. -5
For each end of the device, a switch is connected between said gain device and a fixed potential, e.g. ground, said switch being switched in use at a switching frequency. For each end of the device, a further switch is connected between the output of the input stage and said miller capacitance, said further switch being switched in use at said switching frequency.
Typically, chopper stabilisation is performed at a frequency lower than that at which said output stage is switched.
According to a second aspect of the present invention there is provided an operational amplifier suitable for use in a switched capacitance circuit. The amplifier comprises differential signal inputs, a first chopper coupled to said inputs, and a differential amplifier coupled to said first chopper. A second chopper is coupled to said differential amplifier. A switched mode output stage is coupled to said differential amplifier and comprises low pass filters for ifitering outputs of the differential amplifier, and a switching arrangement for switching outputs of the output stage.
According to a third aspect of the present invention there is provided n method of operating an operational amplifier comprising an input stage and an output stage, the method comprising chopping an input signal to the input stage, chopping the output of the output stage, filtering the output of the input stage in the output stage, and switching the output in the output stage.
For a better understanding of the present invention and in order to show how the same may be carried into effect reference will now be made, by way of example, to the accompanying drawings in which: Figure 1 illustrates an integrator implementing using a switched capacitance circuit, Figure 2 illustrates a known switched-mode operational amplifier design (excluding the common mode feedback circuit); Figure 3 illustrates a technique known as chopper stabilization applied to an operational amplifier; Figure 4 illustrates the component stages of a differential switched opamp topology with chopper stabilization in accordance with an embodiment of the present invention; Figure 5 shows again the circuit of Figure 4, identi1ing individual components; and Figure 6 is a flow diagram illustrating a method of operating a chopper stabilised switched-mode operational amplifier.
The techniques of chopper stabilization to reduce the effects of flicker noise and of switching the output stage of an opamp to eliminate floating switches from SC circuits have been described above with reference to Figures 1 to 3. It is desirable to combine these techniques together. One might anticipate that this would be relatively straightforward at low Vdd. For example, one might contemplate placing a first chopper at the opainp inputs and a second chopper at the outputs, followed by a low pass filter. In practice however such an arrangement has proved difficult to implement.
An alternative and in fact more optimal configuration will now be described.
Referring again to Figure 4, an opamp topology comprises an input stage 2, 6 and an output stage 4, 8. A common, current mirror device P1 is indicated by reference numeral 10. The components comprising each of the input and output stages will now be described with reference to Figure 5.
The input stage has two differential inputs in, mx. The input is received by a first chopper 2 which comprises four NMOS switch devices N13 to N16. Switches N14 and N15 are clocked by a common clock signal CKC at the chopping frequency (in this example 8kHz), and when in the on state connect mx and in to the input devices of a differential amplifier 6. Switches NI 3 and N16 are clocked by a clock signal CKX which is complimentazy to CK. When switches N13 and N14 are on, switches N14 and N15 are off, and the input devices of the differential amplifier to which mx and in are connected are reversed. The effect of the first chopper 2 is to modulate the amplitude of the high frequency chopping signal with the input signal.
A differential amplifier 6 is provided by two PMOS gain devices PS and P6 which are supplied with a constant current by PMOS device P2. Current mirror device P1 provides current mirroring for P2. The amplified differential output voltages of the input stage are developed across NMOS active load devices Ni and N2 which have their sources connected to ground. The gates of the devices Ni, N2 are connected to a common mode feedback signal VCM generated by a common mode feedback (CMFB) circuit which is not shown in the Figures. The CMFB circuit is required to establish the common mode (average) output voltage. The chopped input signals are provided to gates of the respective gain devices P5 and P6.
A second choppers is integrated into the differential amplifier 6 and comprises NMOS devices N9 to N12. Devices Nil and N12 are clocked by (XC, whilst devices N9 and Nl0 are clocked by the complimentary signal CKCX. When Nil and N12 are on, N9 and Ni 0 are off and vice versa. The second chopper 5 performs modulation of the chopping frequency with the modulated and amplified input signal.
As will be appreciated from the above discussion of the chopper stabilization technique, whilst the first chopper 2 shifts the input signals to the first (and higher order) modulation frequency sideband, the second chopper 5 shifts it back to the baseband.
The flicker noise on the other hand is not subject to the first modulation process, and is only added to the amplified input signal within devices P5, P6 and Ni and N2 (these are the main contributors of thermal noise). The action of the second chopper 5 is therefore to shift the thermal noise from the baseband to the first and higher order sidebands, i.e. the amplified input signal and the flicker noise are transposed in the frequency domain by the second chopper.
Turning now to the output stage 4, 8, current gain is provide at each end by common source NMOS devices N4 and N6. These devices are provided with constant currents by constant current PMOS devices P4 and P3, assisted by the current mirror device P1.
Differential outputs of the opamp are taken from the drains of N4 and N6.
Compensation is required to ensure that the opamp is stable when placed in a closed loop configuration as in SC filters and ADCs. Miller capacitors Cl, C2 are therefore positioned between the outputs of the first stage (drain node of Ni and N2) and the outputs of the second stage (out and outx). This type of compensation introduces a dominant pole in the frequency response to ensure stability.
The output stage further comprises, at each end, a pair of switching transistors N3, N8 and N5, N7. These devices act as sampling switches and are connected to a sampling clock signal CK having a frequency of 32kHz in this example. During one half of the period of CK, the switching transistors are in the off' state (CK=Vss) and the output stage does not consume any current. During the other half of the clock period, current is provided to the outputs out and outx to charge up the capacitance(s) of the SC circuit (seeFigurel).
It will be appreciated that, following modulation by the second chopper 5, low pass filtering of the amplified signal is required in order to remove the now upconverted flicker noise. This is achieved by the capacitors Cl, C2 of the output stage.
The method of operating the amplifier is further illustrated in the flow diagram of Figure 6.
Embodiments of the present invention recognise that the input stage does not need to operate in switch mode since floating switches are only connected to the outputs of opanips in conventional SC circuits. This allows the input stage to be operated in chopper mode. As the output stage contributes little to the overall level of flicker noise in the opanç, an optimal solution is achieved.
The opamp topology shown in Figures 4 and 5 may form part of larger signal processing circuitry involving, for example, an input signal to be processed, transducer means for converting the signal to an electrical signal suitable for processing, and a chain of opalnp topologies forming an ADC, the final one feeding into a comparator.
One possible application of the design described here is in the SensiumTt TZ1O3O chip, manufactured by Toumaz Technology Ltd. The SensiumlM chip is an ultra low power wireless sensor interface plafform than may be used in medical applications such as ECG monitoring, temperature monitoring, and the monitoring of blood glucose and oxygen levels etc. Sensors wearable on a patient's body generate signals that are transmitted to the chip for processing/monitoring. The signals to be monitored are low frequency, up to 100Hz. At such low frequencies, flicker noise dominates and can reduce the SNR achieved by the sensor interface measurement section.
It will be appreciated by the person of sidil in the art that various modifications may be made to the above described embodiments without departing from the scope of the present invention. For example, it is to be noted that although Figures 4 and 5 show a fully differential opamp topology (i.e. differential inputs and differential outputs), the principles may also be applied to opamps with single ended outputs.
Claims (17)
- CLAIMS1. An operational amplifier suitable for use in a switched capacitance circuit and comprising an input stage implementing chopper stabilisation, and an output stage implementing a switched mode.
- 2. An operational amplifier according to claim 1, wherein said input stage comprises a first chopper for chopping an input signal to the input stage at a chopping frequency, and a second chopper for chopping an output signal of the input stage at said first chopping signal.
- 3. An operational amplifier according to claim 2, wherein said second chopper is coupled between a gain device and an output device of the or each end of said input stage.
- 4. An operational amplifier according to any one of the preceding claims, wherein said output stage comprises for the or each end, a miller capacitance performing stabilisation and low pass filtering of the output signal of the input stage.
- 5. An operational amplifier according toy one of the preceding claims, wherein said output stage comprises, for the or each end, a gain device and a switch connected at one end to said gain device and at the other end to a fixed potential, the switch being clocked in use at a switching frequency.
- 6. An operational amplifier according to claim 5 and comprising, for the or each end, a switch coupled between an output of the input stage and an output of the second stage, the switch being switched in use at said switching frequency.
- 7. An operational amplifier according to claim 1, wherein said input stage comprises a differential amplifier, each leg of the differential amplifier comprising a gain device in series with a load device.
- 8. An operational amplifier according to claim 7, wherein said first chopper is coupled between differential signal inputs of the operational amplifier and differential inputs of the differential amplifier, and is configured in use to switch the differential input signals between said differential inputs at a chopping frequency.
- 9. An operational amplifier according to claim 8, wherein said second chopper is coupled between said gain devices and said load devices and is configured in use to switch the outputs of the load devices between the inputs of the gain devices at said chopping frequency.
- 10. An operational amplifier according to claim 9, wherein said output stage comprises, for each leg, a gain device and a miller capacitance coupled between the output of the input stage and an output of the output stage, the miller capacitance being configured to perform low pass filtering of the output signal from the input stage.
- 11. An operational according to claim 10 and comprising, for each end of the device, a switch connected between said gain device and a fixed potential, said switch being switched in use at a switching frequency.
- 12. An operational amplifier according to claim 11, wherein said fixed potential is ground.
- 13. An operational amplifier according to claim 11 or 12 and comprising, for each end, a further switch connected between the output of the input stage and said miller capacitance, said further switch being switched in use at said switching frequency.
- 14. An operational amplifier according to any one of the preceding claims, said chopper stabilisation being performed at a frequency lower than that at which said output stage is switched.
- 15. An operational amplifier according to any one of the preceding claims, said input and output stages being implemented using CMOS logic.
- 16. An operational amplifier suitable for use in a switched capacitance circuit and comprising: differential signal inputs; a first chopper coupled to said inputs; a differential amplifier coupled to said first chopper; a second chopper coupled to said differential amplifier; and a switched mode output stage coupled to said differential amplifier and compnsing low pass filters for filtering outputs of the differential amplifier, and a switching arrangement for switching outputs of the output stage.
- 17. A method of operating an operational amplifier comprising an input stage and an output stage, the method comprising chopping an input signal to the input stage, chopping the output of the output stage, filtering the output of the input stage in the output stage, and switching the output in the output stage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0803135A GB2457683A (en) | 2008-02-21 | 2008-02-21 | A CMOS operational amplifier with chopper stabilization and a switched output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0803135A GB2457683A (en) | 2008-02-21 | 2008-02-21 | A CMOS operational amplifier with chopper stabilization and a switched output |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB0803135D0 GB0803135D0 (en) | 2008-03-26 |
| GB2457683A true GB2457683A (en) | 2009-08-26 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0803135A Withdrawn GB2457683A (en) | 2008-02-21 | 2008-02-21 | A CMOS operational amplifier with chopper stabilization and a switched output |
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| Country | Link |
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| GB (1) | GB2457683A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9924904B2 (en) | 2014-09-02 | 2018-03-27 | Medtronic, Inc. | Power-efficient chopper amplifier |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939516A (en) * | 1988-06-13 | 1990-07-03 | Crystal Semiconductor | Chopper stabilized delta-sigma analog-to-digital converter |
| US5039989A (en) * | 1989-10-27 | 1991-08-13 | Crystal Semiconductor Corporation | Delta-sigma analog-to-digital converter with chopper stabilization at the sampling frequency |
| US5745002A (en) * | 1994-06-24 | 1998-04-28 | Sgs-Thomson Microelectronics, S.R.L. | Low voltage, switched capacitance circuit employing switched operational amplifiers with maximized voltage swing |
| US5994960A (en) * | 1996-10-11 | 1999-11-30 | Sgs-Thomson Microelectronics S.R.L. | High speed switched op-amp for low supply voltage applications |
| US6201379B1 (en) * | 1999-10-13 | 2001-03-13 | National Semiconductor Corporation | CMOS voltage reference with a nulling amplifier |
| US6344767B1 (en) * | 2000-01-28 | 2002-02-05 | The Hong Kong University Of Science And Technology | Switched-opamp technique for low-voltage switched capacitor circuits |
| US6731263B2 (en) * | 1998-03-03 | 2004-05-04 | Hitachi, Ltd. | Liquid crystal display device with influences of offset voltages reduced |
| US6795752B1 (en) * | 2000-11-03 | 2004-09-21 | Memsic, Inc. | Thermal convection accelerometer with closed-loop heater control |
| WO2006034177A1 (en) * | 2004-09-17 | 2006-03-30 | Analog Devices, Inc. | Multi-bit continuous-time front-end sigma-delta adc using chopper stabilization |
| US20070109043A1 (en) * | 2005-10-27 | 2007-05-17 | Vincent Thiery | Operational amplifier with zero offset |
-
2008
- 2008-02-21 GB GB0803135A patent/GB2457683A/en not_active Withdrawn
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4939516A (en) * | 1988-06-13 | 1990-07-03 | Crystal Semiconductor | Chopper stabilized delta-sigma analog-to-digital converter |
| US4939516B1 (en) * | 1988-06-13 | 1993-10-26 | Crystal Semiconductor Corporation | Chopper stabilized delta-sigma analog-to-digital converter |
| US5039989A (en) * | 1989-10-27 | 1991-08-13 | Crystal Semiconductor Corporation | Delta-sigma analog-to-digital converter with chopper stabilization at the sampling frequency |
| US5745002A (en) * | 1994-06-24 | 1998-04-28 | Sgs-Thomson Microelectronics, S.R.L. | Low voltage, switched capacitance circuit employing switched operational amplifiers with maximized voltage swing |
| US5994960A (en) * | 1996-10-11 | 1999-11-30 | Sgs-Thomson Microelectronics S.R.L. | High speed switched op-amp for low supply voltage applications |
| US6731263B2 (en) * | 1998-03-03 | 2004-05-04 | Hitachi, Ltd. | Liquid crystal display device with influences of offset voltages reduced |
| US6201379B1 (en) * | 1999-10-13 | 2001-03-13 | National Semiconductor Corporation | CMOS voltage reference with a nulling amplifier |
| US6344767B1 (en) * | 2000-01-28 | 2002-02-05 | The Hong Kong University Of Science And Technology | Switched-opamp technique for low-voltage switched capacitor circuits |
| US6795752B1 (en) * | 2000-11-03 | 2004-09-21 | Memsic, Inc. | Thermal convection accelerometer with closed-loop heater control |
| WO2006034177A1 (en) * | 2004-09-17 | 2006-03-30 | Analog Devices, Inc. | Multi-bit continuous-time front-end sigma-delta adc using chopper stabilization |
| US20070109043A1 (en) * | 2005-10-27 | 2007-05-17 | Vincent Thiery | Operational amplifier with zero offset |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9924904B2 (en) | 2014-09-02 | 2018-03-27 | Medtronic, Inc. | Power-efficient chopper amplifier |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0803135D0 (en) | 2008-03-26 |
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