WO2006034177A1

WO2006034177A1 - Multi-bit continuous-time front-end sigma-delta adc using chopper stabilization

Info

Publication number: WO2006034177A1
Application number: PCT/US2005/033450
Authority: WO
Inventors: Paul John Morrow; Maria Del Mar Chamarro Marti; Colin G. Lyden; Mike Dominic Keane; Robert W. Adams; Richard Thomas O'brien; Paschal Thomas Minogue; Hans Johan Olof Mansson
Original assignee: Analog Devices, Inc.
Priority date: 2004-09-17
Filing date: 2005-09-16
Publication date: 2006-03-30
Also published as: CN101044684B; CN101044684A

Abstract

A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has an input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a feedback signal. An integrator integrates a sum of the generated current and input signal current on a continuous-time basis. The IDAC has a first output branch including a first biasing current source and a second output branch including a second biasing current source. The biasing current sources supply a bias current to a respective branch of the IDAC to bias the input stage in a mid-scale condition. The biasing current sources are connected to the branches via chopping switches which connect the biasing current sources to the branches in a first configuration and a second, reversed, configuration. The integrator amplifier can also be chopper-stabilized, although preferably only the first stage is chopper-stabilized.

Description

MULTI-BIT CONTINUOUS-TIME FRONT-END SIGMA-DELTA ADC USING

CHOPPER STABILIZATION

FIELD OF THE INVENTION This invention relates to sigma-delta analog-to-digital converters.

BACKGROUND TO THE INVENTION

The sigma-delta (ΣΔ) architecture has become the most popular architecture for realizing high-resolution analog-to-digital converters (ADC). Figure 1 illustrates a generalized topology as used in a sigma delta analog-to-digital converter (ADC). The integrator stages 15, 16, 17 depicted in Figure 1 can use continuous-time (C/T or CT) digital-to-analog converters (DACs) or discrete-time (D/T or DT) DACs. The continuous-time solution incorporates a current DAC (IDAC) in the feedback path, whereas a discrete-time solution incorporates a switched-capacitor (S/C) DAC in the feedback path.

Continuous-time Sigma Delta ADCs have received much attention in the last couple of years for applications that require signal bandwidths of several MHz. Continuous-time ADCs are more favourable over switched-capacitor ADCs due to their lower power requirements. Other advantages include better noise immunity due to their inherent anti-aliasing properties, which is especially advantageous in RF receivers. Also, the technology trend is towards very deep submicron processes dictate lower power supply voltages. Switched capacitor based circuits require boot-strapping techniques to drive the switches in order to extend the dynamic range and sampling rates of the converter. Continuous-time ADCs avoid such problems and much higher signal bandwidths can be attained.

Despite the advantages mentioned above in using continuous-time ΣΔ ADCs, audio band ADC implementations have remained in the discrete time domain. This is because discrete time ADCs achieve relatively high linearity, they are very tolerant of clock jitter, and as high signal bandwidths are not required moderate sampling rates can be employed in sigma-delta based ADCs. Also, chopper stabilisation can be readily employed in discrete-time to remove the flicker noise especially problematic in deep submicron MOS devices and the filter coefficients are very stable. The paper "A 114- dB 68-mW Chopper-stabilized stereo multi-bit audio ADC in 5.62mm² , by YuQing Yang; Chokhawala, A.; Alexander, M.; Melanson, J.; Hester, D.; IEEE Journal of Solid- State Circuits, Vol.38, Issue 12, Dec. 2003 Pages 2061-2068 describes the use of chopping in conjunction with a multi-bit discrete-time ADC. However, chopper stabilization is restricted to the op-amp used for the integrator stage. US Patent No. 5,039,989 (Welland et al.) uses chopping in conjunction with a continuous-time converter, but only with a single-bit ADC and single-bit feedback- DAC solution. Single-bit continuous-time ADCs are especially sensitive to jitter and the arrangement presented in Welland is unsuitable for a multi-bit converter.

A discrete-time ADC implementation would seem to be advantageous over a continuous-time ADC for audio band applications for the reasons mentioned already. However, relatively large signal ranges, e.g. 2 Vrms, used within audio television are outside the voltage range that switched-capacitor based circuits can easily interface to. In this case, the only solution would be to attenuate the input signal and thus surrender valuable dynamic range. Even after attenuating the input signal, anti-alias filtering circuitry and buffering circuitry would be required to drive the switched-capacitor input stage. OEMs typically demand that this functionality is provided on-chip, inevitably leading to an increased die cost along with deteriorated noise performance.

There is a desire to use a continuous-time front-end ΣΔ modulator in this application as it avoids having to attenuate, anti-alias filter and buffer the input. However, in using a continuous-time front-end ΣΔ ADC there remain issues of the continuous-time ΣΔ modulator being sensitive to clock jitter and distortion which is produced as a result of the inter-symbol interference within the IDAC. The technology trend towards very deep sub-micron processes dictates lower power supply voltages. Continuous-time ADCs are well suited to these processes. However, one limitation which has inhibited the use of continuous-time ADCs is flicker noise. Implementing a Continuous-time ADC in sub-micron technology would require the DC biasing current source to have a large area in order to achieve low noise. This is because flicker noise is inversely proportional to the area of a device. The input and output devices of the amplifiers would also require a large area for achieving high performance. However, a less area-intensive architecture would be desirable.

Accordingly, the present invention seeks to provide an improved continuous- time sigma-delta ADC. SUMMARY OF THE INVENTION

A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has an input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a feedback signal. The feedback signal is typically a multi-bit digital feedback signal derived from a flash ADC at a downstream stage. An integrator integrates a sum of the generated current and input signal current on a continuous-time basis. The IDAC has a first output branch including a first biasing current source and a second output branch including a second biasing current source. The biasing current sources supply a bias current to a respective branch of the IDAC to bias the input stage in a mid-scale condition. The biasing current sources are connected to the branches via chopping switches which alternately connect the biasing current sources to the branches in a first configuration and a second, reversed, configuration. Additionally, the integrator amplifier can also be chopper-stabilized. In an alternative arrangement the biasing current sources are removed entirely and the integrator amplifier is chopper- stabilized to reduce flicker noise.

Chopping the flicker noise present within the input stage circuitry allows higher noise performance ADCs to be implemented in small sub-micron technologies and reduces the overall size of the converter when implemented in an integrated circuit. This is because flicker noise is inversely proportional to area of a device. Where the IDAC comprises a set of unit IDACs, the feedback signal can be arranged such that it selects various combinations of the unit IDACs on a random or pseudo-random basis to achieve a given level of feedback current. The random/pseudo-random selection can be performed by a scrambler which operates on the feedback signals passed between the Flash ADC and IDAC.

Where the input stage comprises a set of bias current sources, chopping switches can act on the bias current sources which will have the effect of chopping the flicker noise generated by the bias current sources. Where the front-end has a pair of differential inputs the chopping switches can alternately connect the bias current sources to the pair of differential inputs in a first configuration and a second, reversed, configuration. Multi-bit continuous-time ADCs are advantageous over switched-capacitor based solutions in large mixed-signal integrated circuits (chips) since they are less sensitive to substrate noise. Other advantages include: there is lower thermal noise since aliasing does not occur; external interfacing is made easier since there are no discrete pockets of charge required from the input; and larger input signal ranges are possible since the headroom/footroom of a switch is not an obstacle. Employing a multi-bit current DAC alleviates the clock jitter sensitivity experienced by single-bit CT

ADCs. Employing a multi-bit architecture also alleviates the slew rate requirement of the integrator amplifier.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described with reference to the accompanying drawings in which:

Figure 1 schematically shows a multi-bit sigma delta ADC; Figure 2 schematically shows a multi-bit sigma delta ADC in accordance with the invention;

Figure 3 shows a modified single-ended front-end for use in the converter of Figure 2;

Figure 4 shows operation of the scrambler; Figure 5 shows another modified single-ended front-end for use in the converter of Figure 2;

Figure 6 schematically shows the two-stage chopper-stabilized amplifier used within the front-end of Figures 3 and 5;

Figure 7 shows the two-stage amplifier of Figure 6 in more detail; Figure 8 shows performance of a converter according to the invention;

Figure 9 shows a modified differential front-end for use in the converter of Figure 2; and

Figure 10 shows a two-stage chopper-stabilized amplifier for use within the front-end of Figure 9. DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of "including," "comprising," or "having," "containing," "involving," and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. Furthermore, the terms first, second, third and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequential or chronological order. Figure 2 illustrates a topology that combines chopping, multi-bit and continuous-time operation in one sigma-delta ADC. The first stage integrator 15 is a continuous-time (CT) variety and a multi-bit current DAC (IDAC) 50 is used to generate a multi-level current and to perform the subtraction from the incoming input signal current (I/P). Employing a multi-bit current DAC 50 alleviates the clock jitter sensitivity experienced by single-bit CT ADCs. Employing a multi-bit architecture also alleviates the slew rate requirement of the integrator amplifier 12. The subsequent integrator stages 16, 17 following the first stage 15 can be continuous-time or discrete- time. A Flash ADC 18 converts the output of the last stage 17 into a multi-bit digital code which is fed back to the DACs within stages 15, 16, 17. The code has one of 2^N+1 values. A digital filter and decimator 19 converts the output into a digital code having a desired resolution.

As will be described in more detail below, the IDAC 50 comprises a set of unit IDACs, i.e. a set of IDACs which each have the same value current source. For a Flash ADC having 2^N codes, the IDAC 50 in input stage 15 comprises a set of 2^N unit IDACs and there are 2^N feedback lines in the feedback path, one for each unit IDAC. The feedback signal from the Flash ADC 18 is fed to a scrambler 20. The mismatch of the unit elements in the IDAC is noise-shaped by the scrambler 20 employed in the feedback path. Stated another way, for a given value of feedback signal, the scrambler will vary the selection of unit IDACs to achieve that level of feedback signal. The use of the scrambler to select different combinations of IDACs in the continuous time stage has been found to have a chopping effect on flicker noise. For low level input signals, the output codes from the scrambler provide a spectrum that inherently chops (modulates) the current source flicker noise to a high frequency that is later removed by the digital decimation filter 19. The scrambler operates at the same clock rate as the flash ADC clock rate.

A front-end of an ADC according to a first embodiment of the invention is shown in Figure 3. This corresponds to stage 15 of the overall ADC shown in Figure 2. The front-end has a single-ended input Vin and a single-ended output 80. Typically, an input signal will connect to Vin via a dc decoupling capacitor (not shown). The front- end comprises two DC biasing current sources 31, 32 which each supply a bias current of value 2^N"2.I, where N is the number of bits used for the multi-bit feedback signal. A first biasing current source 31 is connected between a supply rail VD_D and a summing node 41 via chopping switches 35. A second biasing current source 32 is connected between the supply rail VDD and a node 42 via chopping switches 35. A multi-bit current digital-to-analog converter (IDAC) 50 is connected to the nodes 41, 42. The IDAC comprises a set of 2^N unit IDACs, one of which is shown as 55 in Figure 4. The IDAC 50 receives a multi-bit (i.e. N-bit) digital feedback signal which is used to select a number of the unit value IDACs 55. Each unit IDAC 55 comprises a current source 53, having a value of 1/2. A first end of the current source 53 is connected to a supply rail Vss- A first branch of each IDAC is connected between the second end of the current source 53 and summing node 41 via a switch 51. A second branch of each IDAC is connected between the second end of the current source 53 and node 42 via a switch 52. Each IDAC 55 receives a selection signal which is applied to an IDAC switch driver 56. The switch driver 56 generates a D and a D bar selection signal, with the D signal being applied to switch 51 and the D bar signal being applied to switch 52. In this manner, the branches of the IDAC are differentially-driven. Switch driver 56 responds to a clock signal, as will be more fully described below, which switches the outputs (D, D bar) in a symmetrical manner.

A set of chopping switches 35 alternately connect the biasing current sources 31, 32 to the nodes 41, 42 in a first configuration and a second configuration. In a first configuration, biasing current source 31 connects to node 41 and biasing current source 32 connects to node 42 (as previously described). In this configuration the switches Φl are closed and switches Φ2 are open. In a second configuration, the current sources are swapped around, with biasing current source 31 connecting to node 42 and biasing current source 32 connecting to node 41. In this configuration the switches Φ2 are closed and the switches Φl are open. A single-ended input signal Vin connects to node 41 via a resistor Rint.

Node 42 connects to an inverting input 61 of an op-amp 60. The non-inverting terminal 62 of op-amp 60 receives a reference voltage vref. Op-amp 60 in conjunction with resistor R 64 acts as a current-to-voltage converter. The output 63 of op-amp 60 is connected to node 42 via a resistor 64 of value R and to summing node 41 via a resistor 65 of value R. Node 41 connects to the summing junction of an integrator stage 70. Resistors 64, 65 are preferably of equal value in order to cancel differentially the supply noise and the even harmonics produced by the IDAC.

The integrator stage 70 comprises an op-amp 73 with an inverting input 71 which connects to node 41 and a non-inverting input 72 which receives a reference voltage vref. The output 74 of op-amp 73 connects to the inverting input 71 via the integrator capacitor Cint in the feedback path.

The operation of the circuit will now be described. Flicker noise on the gate of the unit current source 53 translates into a low frequency noise current when connected to node Out or Outb. When this noise current is connected to Outb via switch 52 its polarity is effectively inverted as seen at the summing junction 41 by the current-to- voltage arrangement in conjunction with resistor R 65. When this noise current is connected to node Out by switch 51 its polarity is un-altered as seen at the summing junction 41. When this noise current is switched between both paths Out and Outb at a sufficiently fast enough rate then their effects are summed or averaged to zero as seen at the summing junction. Stated another way, the Outb current in the second branch of the IDAC is converted to a voltage by the IDAC current-to-voltage converter (op-amp 60) and is converted back to a current with inverted polarity by the resistor 65 at the output of the current-to-voltage amplifier. This current is summed at the summing junction 41 with the current derived from the current Out. Currents derived from the Out current pull current in the direction away from the summing junction 41, while currents derived from the Outb current push currents into the summing junction 41. The noise currents are equal in magnitude but opposite in sign. The fact that the two different current paths to the summing junction 41 keep a differential structure allows the flicker noise of the current source to be shifted or modulated (also known as chopper-stabilized) to an undesirable (high) frequency that can be later removed by filtering, such as the integrator input filtering. This structure also allows even harmonic cancellation from the distortion produced by the switching of the current sources themselves. This structure also allows chopping of the DC biasing current source, which conventionally is not possible in a single-ended structure. The DC biasing current source allows the input to the ADC to be centered at mid-range within the output code range of the ADC itself. For most applications, an input signal is connected externally to node Vin via a dc decoupling capacitor (not shown). With no input signal present Vin will equal Vref. In this condition there will be no current flow through input resistor Rint. When using a 4-bit IDAC in the feedback path there is a total set of 2⁴ (16) unit current sources 50. During a state where there is no input signal (i.e. ADC at mid-scale) eight of these current sources 53 will be connected through the switches labelled D 51 to node Out 41 while the other eight current sources will have their currents pulled through the switches driven by D bar 52 to node Outb 42. The function of the upper current sources 31, 32 is to balance these currents such that there is no net current flow into, or out of, the summing junction 41 for the continuous-time integrator. In effect, the upper current sources 31, 32 are providing the mid-scale current bias that enables the IDACs 50 to output currents above and below mid-scale. Since the sigma-delta loop operates as a closed loop control system, the feedback code tracks the input signal. The function of the lower current sources 53 is to balance the input signal current that is flowing through the input resistor. The difference between the feedback current from the IDAC and the input current from the input resistor Rint is known as the error current. This error current is effectively transferred through to the integrator stage 70.

Figure 4 shows operation of the scrambler 20 in Figure 2. Each unit IDAC 55 is driven by a data bit. The data is thermometer coded so that in this example of a 4 bit IDAC there are 2⁴ = 16 data lines, one data line for each unit IDAC 55, which can take a value in the range 0-16. A data-directed scrambler 20 selects combinations of IDAC unit elements on a pseudo-random basis. The integrator stage 70 integrates the output on a continuous basis. Figure 4 shows an example situation where the required feedback value is 8. This requires eight of the unit IDACs 55 to have their current steered through switch 51 whilst the other eight have their current steered through switch 52. Rather than selecting the same set of eight IDACs on each occasion, the scrambler selects a different combination of IDACs on a pseudo-random basis to achieve the desired feedback current. In the simplest case, this selects the set of IDACs OOOOOOOOl 1111111 ' on a first cycle and the set of IDACs ' 1111111100000000' on a second cycle. The scrambler can, of course, select other combinations of IDACs to achieve a value of 8. The use of the scrambler 20 to select different combinations of IDACs has been found to have a chopping effect on flicker noise. For low level input signals, the output codes from the scrambler provide a spectrum that inherently chops the current source flicker noise to a high frequency that is removed by filtering.

A front-end according to a second embodiment of the invention is shown in Figure 5. In this embodiment the biasing current sources 31, 32 and chopping switches 35 are removed. The other components are the same as shown in Figure 3 and similar numbering is used. The inclusion of the amplifier 60 and resistor 64, which together form a current-to-voltage converter, along with the extra resistor 65, ensures that the IDAC produces a net zero current flowing into the summing junction during mid-scale range. By removing the DC biasing current source, there is a benefit of an improved noise performance as the DC biasing current source no longer contributes thermal and flicker noise. To illustrate operation of this arrangement, assume a mid-range (no input signal) condition where a 16 bit thermometer coded signal from the scrambler comprises 8 bits set high and 8 bits set low. This signal is applied to the 16 IDACs 50. This will set 8 of the IDACs 50 to have D enabled high. This causes current sources 53 of those IDACs to pull current out of the summing junction through node 'Out'. The other 8 IDACs have D set low, meaning that the current sources 53 of those IDACs have their current flowing through 'Outb'. The current that is being drawn from 'Outb' is sourced by the op-amp 60. This creates a voltage greater than 'vref at the output 63 of the op-amp 60 since that current must flow through the leftmost resistor 64. In creating that positive voltage above vref at the output 63 of the op-amp 60, this in turn injects a current that is equal in magnitude to the current flowing through node 'Outb' into the summing junction 41 through the rightmost resistor 65. So, the current that is drawn from the summing junction through the path denoted by 'Out' is balanced by the current that is injected by the other path. As the paths are balanced the uppermost (PMOS) current sources 31, 32 shown in Figure 3 are no longer required.

The front-end shown in Figures 3 and 5 provides a differential path for the IDAC current to flow to the summing junction while also providing a single-ended output current for a single-ended input continuous-time ADC.

Another benefit of the front-end shown in Figures 3 and 5 is that the total current through the switching portion of the IDAC is half that of the prior art. This is because all IDAC currents in the front-end configurations of Figures 3 and 5 are used to cancel the incoming signal current whereas conventionally a throw-away node has been used that made the use of half of the currents redundant when at mid-scale.

In the arrangement shown in Figure 3, where bias current sources 31, 32 are used, explicit chopping switches 35 and a sufficiently high frequency clock to drive the switches are required to chop the DC biasing current source flicker noise. In the arrangement of Figure 5 the switching properties of a data-directed scrambler 20 employed in the feedback path of a multi-bit ADC allow chopping of the noise of IDAC sources 53 to be accomplished without the need to explicitly employ chopping switches and high-frequency clocks. The present invention also allows the flicker noise of the IDAC current-to-voltage amplifier and the integrator amplifier to be chopped.

In Figures 3 and 5, the selection signal (D) is applied to NMOS transistors 51, 52 and the bias current is provided by PMOS current sources 31, 32 in Fig 3. It is possible to reverse the architecture. In this 'opposite' architecture the IDAC is implemented as PMOS transistors and the bias current is provided by NMOS current sources.

It is preferred that the current-to-voltage amplifier 60 and the integrator amplifier 73 in Figures 3 and 5 are each chopper-stabilized. Figures 6 and 7 show one example embodiment of a chopper-stabilized amplifier which is suitable for use as the IDAC amplifier 60 and integrating amplifier 73. This is a single-ended output Class- AB amplifier although it will be appreciated that other designs could equally be used. The amplifier has two gain stages 160, 180. The first gain stage 160 receives a pair of differential inputs Vinp, Vinn and includes an input pair of devices 161, 162 shown in Figure 7 which are loaded by a folded cascade stage. The second gain stage 180 comprises a pair of devices 181, 182 which are coupled together to form a single-ended output VOUT. The devices driven off Vb2 and Vb3 form a Class- AB biasing scheme for the second stage. The signals applied to the gates of devices 181, 182 form the outputs of the first gain stage. The first gain stage 160 differential inputs Vinp, Vinn are connected to devices 161, 162 via chopping switches 163-166. The outputs of the first gain stage are also chopped via chopping switches 183-186. The polarity within the amplifier alternates during each of the two cycles of operation, with switches Φl being closed and switches Φ2 open during the first cycle, and switches Φl being open and switches Φ2 closed during the second cycle. This has the effect of swapping the inputs and outputs of the first stage 160 between alternate cycles. It can be seen that during a first cycle Vinp is connected to the gate of device 161 via switch 163 and Vinn is connected to the gate of device 162 via switch 165. During a second cycle Vinn is connected to the gate of device 161 via switch 164 and Vinp is connected to the gate of device 162 via switch 166. The use of an amplifier having two stages, with chopper stabilization only of the first stage, has been found to provide a performance advantage in a continuous time ADC circuit. The chopping switches 163-166, 183-186 within amplifiers 60, 73 and the chopping switches 35 in Figure 3 can operate over a wide range of clock rates. The chopping control circuits have been designed to operate at the modulator clock rate as well as sub-multiples of this clock rate. In general, the chopping switches can operate at the same rate (Fs) as the main clock for the sigma-delta modulator (i.e. modulator clock rate) or at binary subdivisions of the modulator clock rate, e.g. Fs/2, Fs/4, Fs/8.

The single-ended front-end 15 shown in Figures 3 and 5 and described above provides a lot of the advantages of a differential architecture while providing a single- ended output for feedback IDAC. It enables:

(1) supply noise to be differentially cancelled in the IDAC structure; (2) even order harmonic cancellation produced with the IDAC because of the differential architecture;

(3) chopping of the IDAC current source flicker noise;

(4) chopping of the DC bias current source if a DC bias current source is used;

(5) removal of the DC biasing current source; (6) a reduced current to be dissipated in the IDAC.

Figure 8 compares the noise performance of a front-end of the type shown in Figure 3 without (trace 110) and with (trace 112) chopper stabilization. The input signal is a -6OdB full scale IKHz signal. A front-end of an ADC according to a second embodiment of the invention is shown in Figure 9. This corresponds to stage 15 of the overall ADC shown in Figure 2. The front-end has a pair of differential inputs Vinp, Vinn and a pair of differential outputs 175, 176. Typically, an input signal will connect to Vinp, Vinn via a dc decoupling capacitor (not shown). Each input Vinp, Vinn is connected in series with a resistor Rint. The front-end comprises two DC biasing current sources 131, 132 which each supply a bias current. The bias current is used to bias the front-end in a mid-scale condition in the absence of an analog input signal. A first current source 131 is connected between a supply rail VDD and a summing node 141 via chopping switches 135. A second current source 132 is connected between the supply rail V_DD and a summing node 142 via chopping switches 135. A multi-bit current digital-to-analog converter (IDAC) 150 is connected to the nodes 141, 142. The IDAC comprises a set of 2^N unit IDACs, one of which is shown as 155 in Figure 9. The IDAC receives a multi- bit digital feedback signal from a Flash ADC (18, Figure 2) which is used to select a number of the unit value IDACs 155. Each unit IDAC 155 comprises a current source 153. A first end of the current source 153 is connected to ground. A first branch of each IDAC 155 is connected between the second end of the current source 153 and summing node 141 via a switch 151. A second branch of each IDAC 155 is connected between the second end of the current source 153 and node 142 via a switch 152. Each IDAC 155 receives a selection signal D. The selection signal is applied directly to switch 151 and is inverted before being applied (D bar) to switch 152.

A set of chopping switches 135 alternately connect the biasing current sources 131, 132 to the nodes 141, 142 in a first configuration and a second configuration. In a first configuration, biasing current source 131 connects to node 141 and biasing current source 132 connects to node 142 (as previously described). In this configuration the switches Φl are closed and switches Φ2 are open. In a second configuration, the current sources are swapped around, with biasing current source 131 connecting to node 142 and biasing current source 132 connecting to node 141. In this configuration the switches Φ2 are closed and the switches Φl are open. The chopping switches receive a clock signal f_chop_mos which controls the switching rate of the switches 135.

An integrator stage comprises an integrator amplifier (op-amp) 170 with a feedback capacitor Cint connected between each output and input pair. Node 142 connects to a summing node 171 of integrator amplifierl70 and to the inverting input of integrator amplifier 170. Node 142 connects to a summing node 172 of integrator amplifier 170 and to the non-inverting input of integrator amplifier 170. The integrator amplifier 170 is chopper-stabilized and receives a signal f_chop amp which controls the rate of chopping. The chopping switches 153 can operate at the same rate (Fs) as the main clock for the sigma-delta modulator or at binary subdivisions of the modulator clock rate, e.g. F_s/2, F_s/4, F_s/8.-

The operation of the circuit will now be described. Three sources of flicker noise in the front-end are the unit current sources 153 within each IDAC 155, the bias current sources 131, 132 and the flicker noise present in the integrator amplifier 170. Chopping the bias current sources 131, 132 by connecting them alternately to one differential input and then the other has the effect of modulating their flicker noise to the frequency at which they are switched back and forth. This noise is also modulated to odd harmonics of this switching rate, i.e. Fs, 3Fs, 5Fs etc. The current sources 153 present within the IDAC are switched back and forth by the switching action of the scrambler. The differential amplifier 170 contains two sets of chopping switches that alternately switch back and forth. This causes the flicker noise present within the amplifier 170 to be shifted to the frequency of the clock that drives the chopping switches and to its associated odd harmonics. The chopping switches within the amplifier 170 can operate at the same rate (Fs) as the main clock for the sigma-delta modulator or at binary subdivisions of the modulator clock rate, e.g. Fs/2, Fs/4, Fs/8.

When an IDAC is selected, current source 153 is connected to Vinp via switch

151 and pulls current from node 141. Conversely, when an IDAC is not selected switch

152 in the second branch is turned on which connects current source 153 to node 142. This has the effect of pulling current from node 142. Differential amplifier 170 in conjunction with the integrating capacitors Cint integrates the difference of the net input current at nodes 171, 172 to generate a differential output voltage between outputs Intp and Intn.

Noise from the current source 153 within each IDAC 155 is chopped by the pseudo-random selection of IDACs by scrambler 20. The switching properties of the scrambler 20 employed in the feedback path of the multi-bit ADC allows chopping to be accomplished without the need to explicitly employ chopping switches and high- frequency clocks. Explicit chopping switches and a clock of sufficiently high frequency are required to chop the flicker noise of the DC biasing current sources 131, 132. Figure 10 shows one way of realizing a chopper-stabilized fully differential amplifier which can be used as the amplifier 170 of the integrator stage. The amplifier has two gain stages. The amplifier has inputs Vinp, Vinn and outputs Voutp, Voutn. Figure 6 shows one way of realising amplifier 170. The first gain stage receives a pair of differential inputs Vinp, Vinn and comprises devices 261, 262 which are loaded by a folded cascode stack of devices. The polarity of the input pair within the amplifier varies during each of the two cycles of operation, with switches Φl being closed and switches Φ2 open during the first cycle, and switches Φl being open and switches Φ2 closed during the second cycle. This has the effect of swapping the inputs and outputs of the first stage 260 between alternative clock cycles. It can be seen that during a first cycle Vinp is connected to the gate of device 261 via switch 263 and Vinn is connected to the gate of device 262 via switch 265. During a second cycle Vinn is connected to the gate of device 261 via switch 264 and Vinp is connected to the gate of device 262 via switch 266. The overall polarity of the amplifier is unchanged as a result of the chopping switches 271-278 at the output of the first gain stage. The second gain stage comprises devices 281-284 are provides outputs Voutp, Voutn. The use of an amplifier having two gain stages, with chopper stabilization only of the first gain stage, has been found to provide a performance advantage in a continuous time ADC circuit. The modified architectures retain the advantages of a low-area ADC while also providing high performance. The differential structure of Figure 9 and pseudo differential architectures of Figures 3 and 5 also allow even harmonic cancellation from the distortion produced by the switching of the current sources themselves.

It is appreciated that certain features of the invention, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub-combination.

The invention is not limited to the embodiments described herein, which may be modified or varied without departing from the scope of the invention.

Claims

1. A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) with an input stage comprising: an input which is operable to receive an analog input signal current; a multi-bit feedback current digital-to-analog converter (IDAC) which is operable to generate a multi-level feedback current depending on a feedback signal; and, an integrator which is operable to integrate a sum of the generated current and input signal current on a continuous-time basis; wherein the IDAC has a first output branch including a first biasing current source and a second output branch including a second biasing current source, the biasing current sources each being operable to supply a bias current to a respective output branch of the IDAC to bias the input stage in a mid-scale condition, the biasing current sources being connected to the output branches via chopping switches which are operable to alternately connect the biasing current sources to the output branches in a first configuration and a second, reversed, configuration.

2. A converter according to claim 1 which is operable to receive a modulator clock signal at a frequency Fs and wherein the chopping switches operate at Fs or a binary subdivision thereof.

3. A converter according to claim 1 or 2 wherein the input stage further comprises: a first differential input line which connects to the first output branch; a second differential input line which connects to the second output branch; and wherein the integrator comprises a first differential input which connects to the first output branch and a second differential input which connects to the second output branch.

4. A converter according to any one of the preceding claims wherein the integrator comprises an amplifier and the integrator amplifier is chopper-stabilized.

5. A converter according to claim 4 wherein the integrator amplifier comprises two gain stages and wherein only the first gain stage is chopper-stabilized.

6. A converter according to claim 4 or 5 which is operable to receive a modulator clock signal at a frequency Fs and wherein the integrator amplifier is chopper-stabilized at Fs or a binary subdivision thereof.

7. A converter according to any one of the preceding claims wherein the IDAC comprises a set of individual IDACs, each having a current source which is selectably connectable to the first output branch and the second output branch.

8. A converter according to claim 7 wherein the feedback signal individually selects each individual IDAC, the current source within each individual IDAC being connectable to one of the first output branch and the second output branch.

9. A converter according to claim 7 or 8 wherein the IDAC receives a feedback signal from a scrambler which varies the selection of individual IDACs to achieve each level of feedback current.

10. A converter according to any one of claims 7 to 9 wherein the individual IDACs are unit value IDACs.

11. A converter according to any one of the preceding claims wherein the first output branch connects to a summing node at an input of the integrator via a first path and the second output branch connects to the summing node via a second path, the first path transmitting current from the IDAC to the summing node with a first polarity, and the second path transmitting current from the IDAC to the summing node with an inverted polarity.

12. A converter according to claim 11 wherein the second path comprises a current- to-voltage converter and a first resistor.

13. A converter according to claim 12 wherein the current-to-voltage converter comprises an amplifier having an inverting input which connects to the second output branch of the IDAC and an output which connects to the inverting input via a second resistor.

14. A converter according to any one of the preceding claims in the form of an integrated circuit.

15. A method of generating a signal using a multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) comprising: providing an analog input signal current; generating a multi-level feedback current in a first output branch of an IDAC and in a second output branch of the IDAC, the generated current depending on a received feedback signal; integrating a sum of the generated current and input signal current on a continuous-time basis; providing a first biasing current source and a second biasing current source which each provide a biasing current to bias a respective output branch of the IDAC in a mid-scale condition; and, alternately connecting the biasing current sources to the output branches in a first configuration and a second, reversed, configuration.

16. A signal resulting from the method of claim 15.

17. A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) with an input stage comprising: an input which is operable to receive an analog input signal current; a multi-bit feedback current digital-to-analog converter (IDAC) which is operable to generate a multi-level feedback current depending on a feedback signal; and, an integrator which is operable to integrate a sum of the generated current and input signal current on a continuous-time basis, the integrator comprising an amplifier; wherein the amplifier of the integrator is chopper-stabilized.

18. A converter according to claim 17 wherein the integrator amplifier comprises two gain stages and wherein only the first gain stage is chopper-stabilized.

19. A converter according to claim 17 or 18 which is operable to receive a modulator clock signal at a frequency Fs and wherein the chopping switches operate at Fs or a binary subdivision thereof.

20. A converter according to any one of claims 17 to 19 wherein the IDAC has a first output branch which connects to a summing node at an input of the integrator via a first path and a second output branch which connects to the summing node via a second path, the first path transmitting current from the IDAC to the summing node with a first polarity, and the second path transmitting current from the IDAC to the summing node with an inverted polarity such that the IDAC can bias the converter in a mid-scale condition without bias current sources.

21. A converter according to claim 20 wherein the second path comprises a current- to-voltage converter and a first resistor.

22. A converter according to claim 21 wherein the current-to-voltage converter comprises an amplifier having an inverting input which connects to the second branch of the IDAC and an output which connects to the inverting input via a second resistor.

23. A converter according to any one of claims 17 to 22 in the form of an integrated circuit.

24. A method of generating a signal at a multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) comprising: providing an analog input signal current; generating a multi-level feedback current depending on a feedback signal; and, integrating a sum of the generated current and input signal current on a continuous-time basis; and, chopper stabilizing the integrator.