GB2450037A - Dual Metal Schottky Diode - Google Patents
Dual Metal Schottky Diode Download PDFInfo
- Publication number
- GB2450037A GB2450037A GB0817102A GB0817102A GB2450037A GB 2450037 A GB2450037 A GB 2450037A GB 0817102 A GB0817102 A GB 0817102A GB 0817102 A GB0817102 A GB 0817102A GB 2450037 A GB2450037 A GB 2450037A
- Authority
- GB
- United Kingdom
- Prior art keywords
- metal
- schottky diode
- layer
- barrier layer
- metal area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 110
- 239000002184 metal Substances 0.000 title claims abstract description 110
- 230000009977 dual effect Effects 0.000 title description 32
- 230000004888 barrier function Effects 0.000 claims abstract description 32
- 239000004065 semiconductor Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 21
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 claims description 5
- 229910021340 platinum monosilicide Inorganic materials 0.000 claims description 5
- 229910008479 TiSi2 Inorganic materials 0.000 claims description 4
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 claims description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 2
- 229910021341 titanium silicide Inorganic materials 0.000 abstract 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 abstract 1
- 238000000034 method Methods 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 239000000203 mixture Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910018999 CoSi2 Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 2
- -1 VSI2 Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910021354 zirconium(IV) silicide Inorganic materials 0.000 description 2
- 241000252506 Characiformes Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910012990 NiSi2 Inorganic materials 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910004217 TaSi2 Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010348 incorporation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 239000007800 oxidant agent Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28537—Deposition of Schottky electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
A Schottky diode 22 comprising: a semiconductor substrate 3 including silicon (Si), a first metal area 24 including platinum-silicide (PtSi) coupled to the semiconductor substrate, and a second metal area 28 including titanium-silicide (TiSi2), wherein the first metal area includes islands comprised of the first metal. In a further embodiment, a barrier layer 26 including e.g. silicon dioxide (SiO2) or silicon nitride (SiN) may be coupled to the first metal area with the second metal area coupled to the barrier layer.
Description
DUAL METAL SCHOTTKY DIODE
BACKGROUND OF THE INVENTION
This invention relates to the structure and method of making a dual metal Schottky diode.
BRIEF DESCRIPTION OF THE DRAWINGS
FIGS. lA-lB are cross-section views of a partial integrated circuit in accordance with a first embodiment of the present invention.
FIGS. 2-5 are cross-sectional diagrams of a process for forming the dual metal Schottky diode shown in FIG. lB.
FIGS. 6-7 are cross-sectional diagrams of a process for forming a dual metal Schottky diode in accordance with a second embodiment of the present invention.
FIGS. 8-10 are cross-sectional diagrams of a process for forming a dual metal Schottky diode in accordance with a third embodiment of the present invention.
Detailed Description of the Invention
Referring to the drawings, FIG. lA is a cross-section view of a partial integrated circuit 2 in accordance with a first embodiment of the present invention. The integrated circuit is divided into two parts based on the fabrication or process flow: the Front-End-Of -Line (FEOL) section 4 and the Back-End-Of -Line (BEOL) section 5. The section that includes the silicon substrate 3 is called the FEOL of the integrated circuit 2. In general, the FEOL section 4 is the transistor layer formed on (and within) the semiconductor substrate 3. The partial FEOL 4 shown in FIGS. 1A and lB includes a dual metal Schottky diode 22 of the present invention plus a transistor having a gate oxide 6, a gate electrode 7, and source/drain 8, 9; however, it is within the scope of the invention to have any form of logic within the FEOL section 4.
Immediately above the Schottky diode 22 and the transistor is a layer of dielectric insulation 10 containing metal contacts 11 that electrically tie the Schottky diode 22 and the transistor to the other logic elements (not shown) of the FEOL section 4.
Preferably, the dielectric insulation 10 is comprised of Si02 and the contacts 11 are comprised of W. However, the dielectric insulation 10 may be comprised of any suitable material such as SIN, SIC, SiON, or a low-k dielectric. In addition, the contacts may be comprised of any suitable material such as Al, Ti, or Cu.
The BEOL section 5 contains a single damascene metal layer 12 and at least one dual damascene metal layer 13. However, it is within the scope of the invention to have an integrated circuit 2 with only one (single or dual damascene) metal layer. Layers 12 and 13 contain metal lines 14, 15 that properly route electrical signals and power properly throughout the electronic device. Layer 13 also contains viasl6 that properly connect the metal lines of one metal layer (e.g. 14) to the metal lines of another metal layer (e.g. 15). The metal lines 14, 15 may be comprised of any suitable material such as Al. Furthermore, metal lines 14, 15 may be formed by any suitable process such as deposition, plating, or growth.
The single damascene metal layer 12 has dielectric material 17 and possibly a dielectric barrier layer 18 that electrically insulates the metal lines 14. Similarly, the dual damascene layer 13 contains dielectric material 19 and possibly a dielectric barrier layer 20 that electrically insulates metal lines 15 and vias 16.
In accordance with a preferred embodiment of the present invention, the integrated circuit 2 has a dual metal Schottky diode 22, shown in FIG. lB. The Schottky diode 22 consists of a lightly doped semiconductor substrate 3, a metal area (or metal islands) 24, a barrier layer 26, a metal area (or metal layer) 28, and a metal area (or metal layer) 30. The semiconductor substrate 3 may be comprised of any suitable material such as Si, GaAs, or InP (or a composite or layers of those elements) . In addition, the barrier layer 26 may be a Si02 or SIN dielectric film. However, other materials such as a deposited SIC or a spin-on-glass ("SOG") could be used for the barrier layer 26. Furthermore, the barrier layer 26 may be removed during the process of fabricating the Schottky diode 22.
Preferably, the metal islands 24 are comprised of PtS , the metal layer 28 is comprised of TiSi2 and the metal layer 30 is comprised of Ti. However, it is within the scope of the invention to have metal layers 24 and 28 comprised of any suitable materials such as CoSi2, VSI2, NiSi, NiSi2, ZrSi2, WSi2, TaSi2, MoSi2, or NbSi. Moreover, it is within the scope of the invention to omit barrier layer 26 and/or metal layer 30.
Referring again to the drawings, FIGS. 2-5 show the process for manufacturing the dual metal Schottky diode 22 shown in FIG. 13.
Before the dual metal Schottky diode is fabricated, a layer of photoresist (not shown) is applied and patterned using a lithography process. The openings in this photoresist layer define the locations and size of the dual metal Schottky diodes. In a preferred application, a barrier layer 26 is now formed over the entire substrate, The barrier layer may be formed using any manufacturing process such as Chemical Vapor Deposition ("CVD") or Plasma-Enhanced Chemical Vapor Deposition ("PECVD") . In addition, the barrier layer 26 may be formed chemically by reacting the silicon surface with an oxidizer (such as hydrogen peroxide or nitric acid) In this example application, the barrier layer 26 is comprised of Si02 and is 20A (20 nm) thick. However, it is within the scope of the invention to have any suitable barrier layer thickness appropriate for the composition of the dual metal layers 24, 28, the barrier composition, and the desired voltage drop Vf of the final dual metal Schottky diode.
Also as shown in FIG. 2, a first metal layer 23 is formed over the barrier layer 26. In a preferred application, the first metal layer 23 contains Pt and is approximately 300A thick. However, the thickness of the Pt layer 23 may be anything above 150A. In addition, the thickness of the first metal layer 23 may vary depending on the metal composition used.
The semiconductor wafer is now annealed. In the example application, a rapid thermal process ("RTP") is used to heat the wafer to approximately 5750 C for 30-60 seconds in an 02 and a N2 ambient. For example, a horizontal or vertical furnace may by used to heat the wafer to 500 C for 20 minutes in an 02 or a N2 ambient. During the anneal process the barrier layer 26 will limit the diffusion of Pt from the first layer metal 23 into the Si substrate 3.
After annealing, islands of PtSi 24 are formed within the semiconductor substrate 3, as shown in FIG. 3. It is to be noted that the temperature for the anneal process is selected so that the first metal layer 23 reacts with the semiconductor substrate 3 but not other materials such as the field oxides or gate oxides.
In a preferred application, the unreacted Pt layer 23 is now removed with an isotropic chemical etch process. More specifically, a standard chemical bench tool is used to etch Pt layer 23 (e.g. in a chemistry of H20:HC1:HNO for 10 minutes at 75 C). However, it is within the scope of the invention to use any method to remove the unreacted portions of the unreacted first metal layer 23. In addition, it is within the scope of the invention to perform an additional anneal after the removal of the unreacted Pt layer 23.
As shown in FIG. 4, a second metal layer 30 is formed over the semiconductor wafer (i.e. over the barrier layer 26 if the barrier layer is not removed, or over the silicon and first metal islands if the barrier layer is removed) . In a preferred application, the second metal layer 30 contains Ti and is approximately 400A thick.
However, the thickness of the Ti layer 30 may range from 300-800A.
In addition, the thickness of the second metal layer 30 may vary depending on the type of metal used.
The semiconductor wafer is now annealed. In the example application, a rapid thermal process ("RTP") is used to heat the wafer to approximately 625-750 C for 20-40 seconds in a N2 ambient. For example, a horizontal or vertical furnace may by used to heat the wafer to 600-675 C for 30-60 minutes in a N2 ambient.
After annealing, the Si from the semiconductor substrate 3 diffuses into the second metal layer 30 and forms a layer 28 of TIS12 24, as shown in FIG. 5. It is to be noted that the temperature for the anneal process is selected so that the second metal layer 30 reacts with the semiconductor substrate 3 but not other materials such as the field oxides or gate oxides.
In the example application, a step of etching the unreacted second metal layer 30 (or selected portions of that layer) is optional. If the second metal layer 30 is not removed than it may be used as an electrical contact for the dual metal Schottky diode 22. If the second metal layer 30 is removed, any well-known etch process may be used. For example, sulfuric based (piranha) chemistry or a chemistry of H20/H202 (5:1 ratio) at 40-60 C for 30-60 minutes may be used to strip the unreacted Ti (or the selected portions of Ti) . In the example application, a second anneal is now performed; however, this additional anneal is optional. Any standard process may be used for the second anneal.
For example, a Centura RTP could be used at 820-910 C for 10-30 seconds in a N2 ambient, or a furnace could be used to heat the wafer to 750-850 C in a N2 ambient for 30-60 minutes.
At this point, the fabrication of the semiconductor wafer continues until the integrated circuit is complete. That fabrication process would include the formation of contacts 11 shown in FIGS. 1A and lB that electrically connect the dual metal Schottky diode 22 to the proper components of the integrated circuit 2.
It is within the scope of the invention to use any suitable metal for the first metal area 24 and the second metal area 28 of the dual metal Schottky diode 22. As stated above, the metal components 24, 28 of the dual metal Schottky diode may be any suitable metal composition such as PtSi, TiSi2, CoSi2, VSi2, NiSi, ZrSi2, WS12, TaS12, MoSi2, or NbSi.
It is also within the scope of the invention to use one or more masks to create a dual metal Schottky diode 22 in any one of many configurations. An example variation of the dual metal Schottky diode 22 is shown in FIGS. 6-7. A first mask is used to form the areas (i.e. a first amount) of a Pt first metal 32 and a second mask is used to form the areas (i.e. a first amount) of a Ti second metal 34 shown in FIG. 6. After the anneal and subsequent etch of the unreacted metal 32 and 34, the final dual metal Schottky diode structure 22 would contain areas of PtSi 36 and areas of TiSi2 38, as shown in FIG. 7.
Alternatively, a lithography process could be used to create a patterned photoresist mask layer 40 that is then used to create sections of a Pt first metal 42, as shown in FIG. 8. After removing the exposed metal and ashing the semiconductor wafer to remove the photoresist layer 40, the semiconductor wafer is annealed to form areas of reacted PtSi 44, as shown in FIG. 9. In this alternative embodiment, a Ti second metal layer 46 is deposited and the wafer is then annealed to form a layer of reacted TIS12 48, as shown in FIG. 10.
When one or more masks are used to fabricate the Schottky diode in accordance with this invention, it is within the scope of the invention to use a dual metal Schottky diode with the barrier layer 26 removed. If such a diode is desired then the dual metal Schottky diode is fabricated without a barrier layer 26, or the barrier layer 26 is eliminated with the removal of the first unreacted metal or after the removal of the first unreacted metal.
Moreover, it is within the scope of the invention to use photoresist masks to create different dual metal Schottky diodes 22 throughout the integrated circuit 2. For example, patterned photoresist layers could be used throughout the fabrication process to form the dual metal Schottky diode 22 of FIG. 5 and the dual metal Schottky diode 22 of FIG. 10 at different locations within the same integrated circuit 2.
It is to be noted that a variety of structures and metals can be used to create a dual metal Schottky diode having a Vf that is anywhere between the Vf of a Schottky diode containing the first metal and the Vf of a Schottky diode containing the second metal.
Specifically, by using a barrier layer to limit the interaction of the first metal with the substrate, or by using a mask to apportion the area of the diode between the first and second metals, a Schottky diode can be fabricated to have any desired Vf between the Vf levels obtained with Schottky diodes comprised of single metals.
The use of one or more photoresist masks during wafer fabrication also facilitates the incorporation of dual metal Schottky diodes having different voltage drops at different locations throughout the integrated circuit 2.
Various modifications to the invention as described above are within the scope of the claimed invention. As an example, instead of placing the dual metal Schottky diode 22 immediately above the semiconductor substrate 3 as described above, the dual metal Schottky diode 22 may be placed in any location (or various locations simultaneously) within the front end section 4 or back end section 5 of the integrated circuit. Also, the present invention may be used in any integrated circuit configuration, including integrated circuits having different semiconductor substrates, metal layers, barrier layers, dielectric layers, device structures, active elements, passive elements, etc. In addition, barrier layer 26 may be a metal barrier film (TiSiN, TIN, TaN) instead of a dielectric barrier film. Furthermore, the invention can be used on a non-semiconductor substrate by using a deposited silicide formed by Chemical Vapor Deposition (using WSI), Physical Vapor Deposition (using a composite target), or by reactive sputtering. Moreover, the invention is applicable to other semiconductor technologies such as BiCMOS, bipolar, 301, strained silicon, pyroelectric sensors, opto-electronic devices, microelectrical mechanical system ("MEMS"), or SiGe.
Claims (7)
- SCLAIMS: 1. A Schottky diode comprising: a semiconductor substrate; a first metal area coupled to said semiconductor substrate; and a second metal area coupled to said first metal; wherein said first metal area includes islands comprised of said first metal.
- 2. A Schottky diode comprising: a semiconductor substrate; a first metal area coupled to said semiconductor substrate; a barrier layer coupled to said first metal area; and a second metal area coupled to said barrier layer.wherein said first metal area includes islands comprised of said first metal.
- 3. The Schottky diode of claim 2 wherein said barrier layer includes SiC2.
- 4. The Schottky diode of claim 2 wherein said barrier layer includes SiN.
- 5. The Schottky diode of any preceding claim, wherein said second metal area includes TiSi2.
- 6. The Schottky diode of any preceding claim, wherein said semiconductor substrate includes Si.
- 7. The Schottky diode of any preceding claim, wherein said first metal area includes PtSi.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0817102A GB2450037B (en) | 2004-03-30 | 2005-03-29 | Schottky diode |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/814,673 US6972470B2 (en) | 2004-03-30 | 2004-03-30 | Dual metal Schottky diode |
| GB0817102A GB2450037B (en) | 2004-03-30 | 2005-03-29 | Schottky diode |
| GB0506276A GB2412787B (en) | 2004-03-30 | 2005-03-29 | Dual metal schottky diode |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0817102D0 GB0817102D0 (en) | 2008-10-29 |
| GB2450037A true GB2450037A (en) | 2008-12-10 |
| GB2450037B GB2450037B (en) | 2009-05-27 |
Family
ID=40018388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0817102A Expired - Fee Related GB2450037B (en) | 2004-03-30 | 2005-03-29 | Schottky diode |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2450037B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010132403A1 (en) * | 2009-05-13 | 2010-11-18 | Cree, Inc. | Schottky diodes containing high barrier metal islands in a low barrier metal layer and methods of forming the same |
| CN103904133A (en) * | 2014-03-19 | 2014-07-02 | 中航（重庆）微电子有限公司 | Schottky diode balancing forward voltage drop and reverse leakage current and preparing method |
| CN104916864A (en) * | 2015-05-08 | 2015-09-16 | 曾碚凯 | Copper and aluminum bimetal bipolar plate type transitional unit lithium battery, high-voltage and low-internal resistance battery stack formed through serially connecting batteries, and packaging method of battery stack |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1188082A (en) * | 1967-04-05 | 1970-04-15 | Hitachi Ltd | Method of making Semiconductor Device and Semiconductor Device made thereby |
| GB1289651A (en) * | 1970-01-20 | 1972-09-20 | ||
| GB1312171A (en) * | 1970-05-12 | 1973-04-04 | Siemens Ag | Semiconductor arrangements for use as fixed value stores |
| GB1401554A (en) * | 1972-04-14 | 1975-07-16 | Ibm | Met-semiconductor junction devices |
| US4096622A (en) * | 1975-07-31 | 1978-06-27 | General Motors Corporation | Ion implanted Schottky barrier diode |
| JPH04365378A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Semiconductor integrated circuit |
-
2005
- 2005-03-29 GB GB0817102A patent/GB2450037B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1188082A (en) * | 1967-04-05 | 1970-04-15 | Hitachi Ltd | Method of making Semiconductor Device and Semiconductor Device made thereby |
| GB1289651A (en) * | 1970-01-20 | 1972-09-20 | ||
| GB1312171A (en) * | 1970-05-12 | 1973-04-04 | Siemens Ag | Semiconductor arrangements for use as fixed value stores |
| GB1401554A (en) * | 1972-04-14 | 1975-07-16 | Ibm | Met-semiconductor junction devices |
| US4096622A (en) * | 1975-07-31 | 1978-06-27 | General Motors Corporation | Ion implanted Schottky barrier diode |
| JPH04365378A (en) * | 1991-06-13 | 1992-12-17 | Nec Corp | Semiconductor integrated circuit |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010132403A1 (en) * | 2009-05-13 | 2010-11-18 | Cree, Inc. | Schottky diodes containing high barrier metal islands in a low barrier metal layer and methods of forming the same |
| US7915703B2 (en) | 2009-05-13 | 2011-03-29 | Cree, Inc. | Schottky diodes containing high barrier metal islands in a low barrier metal layer and methods of forming the same |
| CN103904133A (en) * | 2014-03-19 | 2014-07-02 | 中航（重庆）微电子有限公司 | Schottky diode balancing forward voltage drop and reverse leakage current and preparing method |
| CN103904133B (en) * | 2014-03-19 | 2017-01-18 | 中航（重庆）微电子有限公司 | Schottky diode balancing forward voltage drop and reverse leakage current and preparing method |
| CN104916864A (en) * | 2015-05-08 | 2015-09-16 | 曾碚凯 | Copper and aluminum bimetal bipolar plate type transitional unit lithium battery, high-voltage and low-internal resistance battery stack formed through serially connecting batteries, and packaging method of battery stack |
| CN104916864B (en) * | 2015-05-08 | 2018-01-16 | 深圳藈花新能源科技有限公司 | The height that a kind of bipolar template transitionality unit lithium battery of Cu-Al bimetal and its series connection are formed forces down changeable internal damp bvattery heap and method for packing |
Also Published As
| Publication number | Publication date |
|---|---|
| GB0817102D0 (en) | 2008-10-29 |
| GB2450037B (en) | 2009-05-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7229871B2 (en) | Integrated circuit containing polysilicon gate transistors and fully silicidized metal gate transistors | |
| CN101542710B (en) | Low resistance contact structure and fabrication thereof | |
| US6103610A (en) | Integrated circuit structure with dual thickness cobalt silicide layers and method for its manufacture | |
| US7396767B2 (en) | Semiconductor structure including silicide regions and method of making same | |
| US7521309B2 (en) | Method of manufacturing semiconductor device | |
| US20060166457A1 (en) | Method of making transistors and non-silicided polysilicon resistors for mixed signal circuits | |
| JP2007150293A (en) | Method for forming semiconductor structure comprising different species of silicide/germanide with cmos technique | |
| US8298934B2 (en) | Structure and method of creating entirely self-aligned metallic contacts | |
| US10109524B2 (en) | Recessing of liner and conductor for via formation | |
| US20070298600A1 (en) | Method of Fabricating Semiconductor Device and Semiconductor Device Fabricated Thereby | |
| US7902055B2 (en) | Method of manufacturing a dual metal Schottky diode | |
| US6878624B1 (en) | Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi | |
| JP3152739B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| GB2450037A (en) | Dual Metal Schottky Diode | |
| US20070099407A1 (en) | Method for fabricating a transistor using a low temperature spike anneal | |
| US7943499B2 (en) | FUSI integration method using SOG as a sacrificial planarization layer | |
| US20080299767A1 (en) | Method for Forming a Semiconductor Device Having a Salicide Layer | |
| US7018865B2 (en) | Method of protecting an element of an integrated circuit against the formation of a metal silicide | |
| JPH06349771A (en) | Manufacture of semiconductor integrated circuit device and semiconductor integrated circuit device | |
| JP2009094458A (en) | Thin film, and method for manufacturing semiconductor device using the thin film | |
| JPH11284184A (en) | Semiconductor device and manufacture thereof | |
| JP2004281604A (en) | Semiconductor device and its manufacturing method | |
| JPH11243068A (en) | Manufacture of semiconductor device | |
| JP2009130189A (en) | Method for manufacturing semiconductor device | |
| JP2009099611A (en) | Semiconductor device and method of manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20210329 |