JP2009130189A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for acquiring different desired thresholds between a pMOSFET and an nMOSFET. <P>SOLUTION: A first metal-containing layer 9 is formed on a first gate electrode layer and a second gate electrode layer, and a film 10 containing a photosensitive organic film is formed at the upper part of the first metal-containing layer, and a film containing the photosensitive organic film positioned at the upper part of the first gate electrode layer is selectively removed to expose the section of the first metal-containing layer, which is positioned at the upper part of the first gate electrode layer, and a second metal-containing layer 19 is formed on a film containing the photosensitive organic film and the first metal-containing layer, and metal contained in the first metal-containing layer and the second metal-containing layer and the second gate electrode layer are made to react by heating treatment to alloy the second gate electrode layer, and metal contained in the first metal-containing layer and the second gate electrode layer are made to react by heating treatment to alloy the second gate electrode layer. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to, for example, a metal gate electrode, and more particularly to a method of manufacturing a semiconductor device in which a metal gate electrode having a different composition is formed by an nMOS (MeTal Oxide Semiconductor) FET (Field-Effect Transistor) and a pMOSFET.

  Conventionally, a metal gate electrode is used to suppress a gate depletion layer of a MOS transistor. A FUSI (full siliconized) gate is more preferable because it is easily compatible with a currently used method for manufacturing a semiconductor device.

However, it is difficult to control the work function of this FUSI gate. Here, it is possible to change the work function of the FUSI gate (change the threshold value) by introducing As, P, and B into SiO ₂ that is the gate insulating film. However, a desired value is not obtained by this method.

Further, in order to suppress the leakage current at the gate, a high dielectric insulating film is used as the gate insulating film instead of SiO ₂ .

For example, a hafnium silicate oxynitride (HfSiON) film is used for the high dielectric insulating film. However, the range in which the threshold changes with respect to the composition of the gate electrode (for example, Ni _x Si _y ) is further reduced.

  Therefore, there is a conventional method of manufacturing a semiconductor device in which a FUSI gate having a threshold value closer to a desired value is formed by changing and combining the composition of the FUSI gate (see, for example, Patent Document 1). ).

  Here, in the above prior art, in order to silicide the polysilicon of the gate electrode layer, Ni is deposited on the polysilicon. Then, using TiN as a protective film, Ni is selectively removed by a mixed solution of hydrochloric acid and hydrogen peroxide solution corresponding to the pMOS structure and the nMOS structure, respectively. Then, the polysilicon of the gate electrode layer is selectively silicided by heat treatment.

  Thus, in the above prior art, it is necessary to perform the silicide process twice corresponding to each of the pMOS structure and the nMOS structure.

In addition, after the composition of the FUSI gate is made differently in the pMOS structure and the nMOS structure, impurities (such as Al) may be diffused and segregated in the nMOS structure as necessary. In this case, a hard mask of an insulating film such as SiO ₂ or SiN is formed on the pMOS structure.

  Therefore, in the above case, a step of finally peeling the mask material is required. Alternatively, when leaving the mask material, a step of planarizing the insulating film is necessary.

That is, the above-described prior art has a problem that the number of steps for forming FUSI gates having different threshold values for the pMOSFET and the nMOSFET is large.
JP 2005-167251 A

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the number of steps for forming FUSI gates having different threshold values for a pMOSFET and an nMOSFET.

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes:
A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
Forming a gate insulating film of a high dielectric insulating film on the semiconductor substrate;
A first gate electrode layer including at least one of Si or Ge is formed on the gate insulating film in a gate electrode region in which a gate electrode of the first conductivity type MOSFET is formed, and the second conductivity type MOSFET is Forming a second gate electrode layer containing at least one of Si or Ge on the gate insulating film in the gate electrode region where the gate electrode is formed;
Forming a first metal-containing layer on the first gate electrode layer and the second gate electrode layer;
Forming a film including a photosensitive organic film on the first metal-containing layer;
By selectively removing the film including the photosensitive organic film located above the first gate electrode layer, the portion of the first metal-containing layer located above the first gate electrode layer is removed. To expose
Forming a second metal-containing layer on the film including the photosensitive organic film and on the first metal-containing layer;
The metal contained in the first metal-containing layer and the second metal-containing layer reacts with the second gate electrode layer by heat treatment to alloy the second gate electrode layer. The heat treatment causes the metal contained in the first metal-containing layer to react with the second gate electrode layer to alloy the second gate electrode layer.

A method for manufacturing a semiconductor device according to another aspect of the present invention includes:
A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
Forming a gate insulating film of a high dielectric insulating film on the semiconductor substrate;
A first gate electrode layer including at least one of Si or Ge is formed on the gate insulating film in a gate electrode region in which a gate electrode of the first conductivity type MOSFET is formed, and the second conductivity type MOSFET is Forming a second gate electrode layer containing at least one of Si or Ge on the gate insulating film in the gate electrode region where the gate electrode is formed;
Forming a first metal-containing layer on the first gate electrode layer and the second gate electrode layer;
Forming a diffusion prevention layer above the first metal-containing layer, and forming a photosensitive organic film on the diffusion prevention layer;
By selectively removing the photosensitive organic film located above the first gate electrode layer, a portion of the diffusion prevention layer located above the first gate electrode layer is exposed,
Removing the portion of the diffusion preventing layer to expose a portion of the first metal-containing layer located above the first gate electrode layer;
Forming a second metal-containing layer above the diffusion preventing layer and on the first metal-containing layer;
The metal contained in the first metal-containing layer and the second metal-containing layer reacts with the second gate electrode layer by heat treatment to alloy the second gate electrode layer. The heat treatment causes the metal contained in the first metal-containing layer to react with the second gate electrode layer to alloy the second gate electrode layer.

A method for manufacturing a semiconductor device according to still another aspect of the present invention includes:
A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
Forming a gate insulating film of a high dielectric insulating film on the semiconductor substrate;
A first gate electrode layer including at least one of Si or Ge is formed on the gate insulating film in a gate electrode region in which a gate electrode of the first conductivity type MOSFET is formed, and the second conductivity type MOSFET is Forming a second gate electrode layer containing at least one of Si or Ge on the gate insulating film in the gate electrode region where the gate electrode is formed;
Forming a metal-containing layer on the first gate electrode layer and the second gate electrode layer;
Forming a film including a photosensitive organic film on the metal-containing layer;
By selectively removing the film including the photosensitive organic film located above the first gate electrode layer, a portion of the metal-containing layer located above the second gate electrode layer is exposed,
Thinning the portion of the metal-containing layer,
The metal contained in the metal-containing layer is reacted with the first gate electrode layer by heat treatment to alloy the first gate electrode layer, and the metal-containing layer is formed by the heat treatment. The contained metal and the second gate electrode layer are reacted to alloy the second gate electrode layer.

A method for manufacturing a semiconductor device according to still another aspect of the present invention includes:
A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
A first gate electrode layer made of an alloy containing at least one of Si or Ge is formed in a region where the gate electrode of the first conductivity type MOSFET is formed, and the gate electrode of the second conductivity type MOSFET is formed. A second gate electrode layer made of an alloy containing at least one of Si or Ge and having a composition different from that of the first gate electrode layer,
Forming a film including a photosensitive organic film above the first gate electrode layer and the second gate electrode layer;
Selectively removing the film including the photosensitive organic film located above the second gate electrode layer to expose the second gate electrode layer;
Forming a diffusion metal-containing layer containing a metal for inclusion in the second gate electrode layer on the second gate electrode layer and on the film including the photosensitive organic film;
By heat treatment, the metal contained in the diffusion metal-containing layer is contained in the second gate electrode layer,
The diffusion metal-containing layer and the film including the photosensitive organic film are simultaneously removed.

  According to the method for manufacturing a semiconductor device of one embodiment of the present invention, a desired threshold value that is different between the pMOSFET and the nMOSFET can be obtained.

  Embodiments to which the present invention is applied will be described below with reference to the drawings. In each embodiment, for simplicity, a pair of nMOSFETs and pMOSFETs in an LSI are shown side by side, but the present invention is not limited to this arrangement.

  A method for manufacturing a semiconductor device in which a first conductivity type MOSFET according to the first embodiment and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate will be described.

  In this embodiment, for example, a case will be described in which the first conductivity type MOS transistor is a pMOSFET, the second conductivity type MOS transistor is an nMOSFET, and a silicon substrate is selected as the semiconductor substrate. However, the same applies to the case where the conductivity type is reversed (the same applies to other embodiments).

  1A to 1I are cross-sectional views of nMOSFET and pMOSFET regions in respective steps of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, as shown in FIG. 1A, a trench is formed in the silicon substrate 1, and an insulating film such as a silicon oxide film is buried in the trench, thereby forming an STI (Shallow Trench Isolation) 2. Thereafter, an n well is selectively formed by injecting impurities into the pMOSFET region of the silicon substrate 1 and thermally diffusing, and at the same time selectively injecting impurities into the nMOSFET region of the silicon substrate 1 and thermally diffusing the p well. Form.

  Next, a hafnium silicate film (HfSiO film) is formed on the silicon substrate 1, nitrogen is added to the HfSiO film, and then heat treatment is performed to form a high dielectric insulating film having a thickness of about 3 nm, for example. The hafnium silicate nitride film (HfSiON film) 3 is modified. The HfSiON film 3 functions as a gate insulating film (high dielectric insulating film).

  That is, the polysilicon layer 4 that is a gate electrode layer containing Si is formed on the HfSiON film (gate insulating film) 3 in the gate electrode region where the gate electrode of the pMOSFET is formed. Similarly, a polysilicon layer 4 which is a gate electrode layer having the same composition as the gate electrode layer is formed on the HfSiON film (gate insulating film) 3 in the gate electrode region where the gate electrode of the nMOSFET is formed. Note that a layer containing poly-Ge may be selected as the gate electrode layer. The polysilicon layer 4 is formed by CVD (Chemical Vapor Deposition) and has a film thickness of about 100 nm, for example.

  Then, a SiN film 5 as a hard mask material is formed on the polysilicon layer 4 (FIG. 1B).

  As the gate insulating film, instead of the HfSiON film 3, a film containing at least one of Hf, Zr, Al, La and Si, O, N may be selected.

  Next, a poly-Si / HfSiON gate is formed using the SiN film 5 as a hard mask (FIG. 1C).

  Next, sidewall SiN 51 is formed by CVD and RIE (Reactive Ion Etching) (FIG. 1D).

  Next, after a source / drain diffusion layer is formed on the silicon substrate 1, a source / drain silicide contact (for example, NiPtSi layer, NiSi, PtSi, PdSi, CoSi, TiSi, etc. may be used) 6 using a salicide process 6 (FIG. 1E).

  Next, an SiN film 7 is formed on the pMOSFET region and the nMOSFET region by, for example, CVD (FIG. 1F).

Next, a SiO ₂ layer 8 is formed on the SiN film 7 with a thickness at least larger than that of the polysilicon layer 4 by, eg, CVD (FIG. 1G).

Next, the SiO ₂ layer 8 is flattened by CMP (Chemical Mechanical Polishing) using the SiN film as an etching stopper (FIG. 1H).

Next, the SiN film 7 and the SiO ₂ layer 8 on the polysilicon layer 4 are removed by etching by RIE or CMP (FIG. 1I).

  Here, a description will be given focusing on the configuration of the gate electrode region of the pMOSFET and the nMOSFET. 2A to 2D are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention.

  First, after forming the HfSiON film 3 as a gate insulating film and the polysilicon layer 4 as a gate electrode layer by the steps of FIGS. 1A to 1I described above (FIG. 1I), a natural oxide film is formed by dilute hydrofluoric acid treatment or the like. Etc. are removed, and a Ni film 9 which is a first metal-containing layer is formed on the polysilicon layer 4 by sputtering. Then, a photosensitive organic film 10 such as a resist or polyimide is formed on the Ni film 9.

  Then, the photosensitive organic film 10 located above the polysilicon layer 4 in the pMOSFET region is selectively removed by lithography. As a result, a portion of the Ni film 9 located above the gate electrode layer 4 in the pMOSFET region is exposed (FIG. 2A).

  The photosensitive organic film 10 also has a function of preventing metal diffusion.

  The first metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, La, or Ni, Co, Pt, Ti, Hf, Zr, Al, instead of Ni. You may make it contain the alloy containing either of La. One or more layers may be stacked.

  Next, a Ni film 19 as a second metal-containing layer is formed on the photosensitive organic film 10 and the Ni film 9 by sputtering (FIG. 2B).

  The second metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, Pd, and La, or Ni, Co, Pt, Ti, Hf, Zr, instead of Ni. You may make it contain the alloy containing either Al, Pd, or La. One or more layers may be stacked.

  In this embodiment, for example, the film is formed so that the ratio of the film thickness of the first metal-containing layer (Ni film 9) to the film thickness of the second metal-containing layer (Ni film 19) is 2: 1. To do. It is also possible to selectively remove the exposed first metal-containing layer (Ni film 9) and re-deposit the second metal-containing layer (Ni film 19) on the polysilicon layer 4 in the pMOSFET region. However, when alloying with a gate electrode layer containing Si or Ge, such as when siliciding polysilicon, it is very important to remove and control the natural oxide film on the gate electrode. It is very effective to prevent exposure.

  Through the above steps, the metal-containing layer located on the gate electrode layer in the pMOSFET region has a different film thickness from the metal-containing layer located on the gate electrode layer in the nMOSFET region. In addition, when the compositions of the first metal-containing layer and the second metal-containing layer are different, the laminated structure is different.

Next, for example, RTA (Rapid Thermal Annealing) is performed at 500 ° C. for 30 seconds to silicide (alloy) the polysilicon layer 4. As a result, the Ni ₂ Si layer 4a is formed as the gate electrode of the nMOSFET region, and the Ni ₃ Si layer 4b is formed as the gate electrode of the pMOSFET (FIG. 2C).

  That is, the metal (Ni) contained in the first and second metal-containing layers (Ni film 9, Ni film 19) and the gate electrode layer (polysilicon layer 4) in the pMOSFET region are reacted by heat treatment, This gate electrode layer is alloyed. Further, by the same heat treatment, the metal (Ni) contained in the second metal-containing layer (Ni film 9) reacts with the gate electrode layer (polysilicon layer 4) in the nMOSFET region, and this gate electrode layer is Alloy to form gate electrodes of different composition.

  Note that since the ratio of Ni alloying is higher in the gate electrode layer in the pMOSFET region, the volume of the gate electrode layer in the nMOSFET region is expanded (FIG. 2C).

  Here, as described above, the film thickness of the metal-containing layer on the gate electrode layer in the pMOSFET region is larger than the film thickness of the metal-containing layer on the gate electrode layer in the nMOSFET region. Is also different.

That is, for example, the composition of one gate electrode layer (in this embodiment, the gate electrode layer in the pMOSFET region) is represented by Ni _X1 Si _Y1 , and the composition of the other gate electrode layer (in this embodiment, the gate electrode layer in the nMOSFET region). _Is represented by Ni _X2 Si _Y2 . At this time, the coefficients X1, X2, Y1, and Y2 satisfy the relationship of X1 / Y1> X2 / Y2.

  Thus, the gate electrode in the nMOSFET region and the gate electrode in the pMOSFET region have different compositions.

  Therefore, at this time, the threshold values of these nMOSFETs and pMOSFETs are different.

Next, planarization is performed by CMP using the SiO ₂ film 8 as an etching stopper (FIG. 2D). However, it is not necessarily flat.

  A process for wiring the nMOSFET and the pMOSFET having the gate electrode formed as described above will be described.

  3A to 3D are cross-sectional views of nMOSFET and pMOSFET regions in each step of the method of manufacturing a semiconductor device according to the first embodiment of the present invention. Note that the process shown in FIG. 3A corresponds to the process shown in FIG.

After forming silicided gate electrodes (Ni ₂ Si film 4a, Ni ₃ Si layer 4b) by the steps of FIGS. 2A to 2I (FIG. 3A), the SiO ₂ film 8 is etched by RIE (FIG. 3B). .

Next, the SiN film 11 is formed by PCVD using SiH ₄ , NH ₃ or the like. Then, an interlayer insulating film SiO ₂ layer 14 using TEOS or the like is deposited on the entire surface. Then, the interlayer insulating film SiO ₂ layer 14 is planarized by CMP (FIG. 3C).

Next, contact holes are formed in the interlayer insulating film SiO ₂ layer 14 so as to be connected to the source / drain regions (NiPtSi layer 6) and the gate electrodes (Ni ₂ Si film 4a, Ni ₃ Si layer 4b). The plug (15) is formed by filling the metal. Then, a wiring layer 16 (for example, an Al / TiN / Ti layer, or a layer connecting the source / drain region (NiPtSi layer 6), the gate electrode (Ni ₂ Si film 4a, Ni ₃ Si layer 4b) and another circuit configuration, or Cu / TiN / Ti layer, Cu / Ta layer, Cu / Ta layer, etc.) are formed (FIG. 3D). At this time, the Cu wiring is formed by a damascene method.

  Thereafter, the LSI is completed by performing the wiring process of the second layer or more.

  As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, a desired threshold value that differs between the pMOSFET and the nMOSFET can be obtained in one silicide process.

  In the first embodiment, the semiconductor device manufacturing method in which the gate electrode layer is silicided in order to change the threshold values of the pMOSFET and the nMOSFET has been described.

  In this embodiment, another method for manufacturing a semiconductor device in which the gate electrode layer is silicided in order to change the threshold values of the pMOSFET and the nMOSFET will be described.

  The manufacturing method of the semiconductor device according to the second embodiment is the same as the steps from FIGS. 1A to 1I described in the first embodiment.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  4A to 4G are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  First, after the HfSiON film 3 and the polysilicon layer 4 are formed by the steps of FIGS. 1A to 1I, the Ni film 9 and the TiN film 10a are sequentially formed on the polysilicon layer 4 by sputtering.

  That is, the Ni film 9 as the first metal-containing layer is formed on the gate electrode layer in the pMOSFET region and the gate electrode layer (polysilicon layer 4) in the nMOSFET region.

  Further, a TiN film 10a serving as a diffusion preventing layer for preventing metal diffusion is formed on the Ni film 9. A photosensitive organic film 10b such as a resist or polyimide is formed on the TiN film 10a.

  Then, the photosensitive organic film 10b located above the polysilicon layer 4 in the pMOSFET region is selectively removed by lithography. Thereby, a portion of the TiN film 10a located above the gate electrode layer 4 in the pMOSFET region is exposed.

  Further, using the remaining photosensitive organic film 10b as a mask, hydrogen peroxide solution, hydrofluoric acid, a mixture solution of hydrofluoric acid and hydrogen peroxide solution, a mixture solution of hydrofluoric acid and nitric acid, a mixture of hydrochloric acid, hydrochloric acid and hydrogen peroxide solution Liquid, mixed liquid of hydrochloric acid and nitric acid, mixed liquid of sulfuric acid, sulfuric acid and hydrogen peroxide, ammonia water, mixed liquid of ammonia and hydrogen peroxide, choline, mixed liquid of choline and hydrogen peroxide, TMAH, TMAH The TiN film 10a located above the polysilicon layer 4 in the pMOSFET region is peeled off with a mixed solution of hydrogen peroxide and water. As a result, the upper surface of the Ni film 9 in the pMOSFET region is exposed (FIG. 4A). The TiN film 10a may be removed by RIE using a gas containing chlorine or fluorine, using the photosensitive organic film 10b as a mask.

  Through the above steps, a portion of the Ni film 9 located above the gate electrode layer 4 in the pMOSFET region is exposed. That is, the diffusion preventing film is selectively removed.

  Note that, as in Example 1, the first metal-containing layer was replaced with Ni, and any one of Co, Pt, Ti, Hf, Zr, Al, La, or Ni, Co, Pt, Ti , Hf, Zr, Al, or an alloy containing any one of La may be contained. One or more layers may be stacked.

  Further, the diffusion prevention layer is replaced with TiN, and any of W, WN, TaN, HfN, ZrN, TaC, and MoN, or TiN, W, WN, TaN, HfN, ZrN, TaC, and MoN. You may make it contain the alloy containing. One or more layers may be stacked.

  Next, after removing the photosensitive organic film 10b, a Ni film 19 as a second metal-containing layer is formed on the TiN film 10a and the Ni film 9 by sputtering (FIG. 4B). At this time, the photosensitive organic film 10b is removed by ashing or an organic solvent. Note that, when a resist containing a novolac resin is used for the photosensitive film, it is desirable to remove it. However, when a polyimide or the like is used, it is not necessarily removed.

  The second metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, Pd, and La, or Ni, Co, Pt, Ti, Hf, Zr, instead of Ni. You may make it contain the alloy containing either Al, Pd, or La. One or more layers may be stacked.

  In this embodiment, for example, the film is formed so that the ratio of the film thickness of the first metal-containing layer (Ni film 9) to the film thickness of the second metal-containing layer (Ni film 19) is 2: 1. To do. It is also possible to selectively remove the exposed first metal-containing layer (Ni film 9) and re-deposit the second metal-containing layer (Ni film 19) on the polysilicon layer 4 in the pMOSFET region. However, when alloying with a gate electrode layer containing Si or Ge, such as when siliciding polysilicon, it is very important to remove and control the natural oxide film on the gate electrode. It is very effective to prevent exposure.

  Through the above steps, the metal-containing layer located on the gate electrode layer in the pMOSFET region has a different film thickness from the metal-containing layer located on the gate electrode layer in the nMOSFET region. In addition, when the compositions of the first metal-containing layer and the second metal-containing layer are different, the laminated structure is different.

Next, as in Example 1, for example, RTA is performed at 500 ° C. for 30 seconds to silicide (alloy) the polysilicon layer 4. Thereby, the Ni ₂ Si layer 4a is formed as the gate electrode of the nMOSFET region, and the Ni ₃ Si layer 4b is formed as the gate electrode of the pMOSFET (FIG. 4C).

  That is, the metal (Ni) contained in the first and second metal-containing layers (Ni film 9, Ni film 19) and the gate electrode layer (polysilicon layer 4) in the pMOSFET region are reacted by heat treatment, This gate electrode layer is alloyed. Further, by the same heat treatment, the metal (Ni) contained in the second metal-containing layer (Ni film 9) reacts with the gate electrode layer (polysilicon layer 4) in the nMOSFET region, and this gate electrode layer is Alloy to form gate electrodes of different composition.

  Note that since the ratio of Ni alloying is higher in the gate electrode layer in the pMOSFET region, the volume of the gate electrode layer in the nMOSFET region is expanded (FIG. 4C).

  Here, as in Example 1, since the thickness of the metal-containing layer on the gate electrode layer in the pMOSFET region is larger than the thickness of the metal-containing layer on the gate electrode layer in the nMOSFET region, it is obtained by silicidation. The composition is also different.

  Therefore, at this time, the threshold values of these nMOSFETs and pMOSFETs are different.

  Next, planarization is performed by CMP using the SiN film 7 as an etching stopper (FIG. 4D). However, it is not necessarily flat.

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process shown in FIG. 3A corresponds to the process shown in FIG. 4D.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

  In the first and second embodiments, the method of manufacturing a semiconductor device in which the gate electrode layer is silicided in order to change the threshold values of the pMOSFET and the nMOSFET has been described.

  In the third embodiment, another method for manufacturing a semiconductor device in which the gate electrode layer is silicided in order to change the threshold values of the pMOSFET and the nMOSFET will be described.

  The manufacturing method of the semiconductor device according to the third embodiment is similar to the steps from FIGS. 1A to 1I described in the first embodiment.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  5A to 5G are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  First, after the HfSiON film 3 and the polysilicon layer 4 are formed by the steps of FIGS. 1A to 1I, a Ni film 9 is formed on the polysilicon layer 4 by sputtering.

  That is, the Ni film 9 as the first metal-containing layer is formed on the gate electrode layer in the pMOSFET region and the gate electrode layer (polysilicon layer 4) in the nMOSFET region.

  Further, a photosensitive organic film 10 such as a resist or polyimide is formed on the Ni film 9.

  Then, the photosensitive organic film 10 located above the polysilicon layer 4 in the nMOSFET region is selectively removed by lithography. As a result, a portion of the Ni film 9 located above the gate electrode layer in the nMOSFET region is exposed (FIG. 5A).

  Note that, as in Example 1, the first metal-containing layer was replaced with Ni, and any one of Co, Pt, Ti, Hf, Zr, Al, La, or Ni, Co, Pt, Ti , Hf, Zr, Al, or an alloy containing any one of La may be contained. One or more layers may be stacked.

  Next, the upper part of the Ni film 9 is selectively removed by RIE using the photosensitive organic film 10 as a mask. Thereby, the Ni film 9 positioned above the gate electrode layer in the nMOSFET region is thinned (FIG. 5B). The photosensitive organic film 10 is used as a protective film, and a mixture of hydrochloric acid, hydrochloric acid and hydrogen peroxide solution, a mixture of hydrochloric acid and nitric acid, hydrofluoric acid, a mixture of hydrofluoric acid and hydrogen peroxide, or a mixture of hydrofluoric acid and nitric acid. The upper portion of the Ni film 9 may be selectively removed by a mixed solution, a mixed solution of acid, an acid and an oxidizing agent, such as a mixed solution, sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution, or the like.

  In this embodiment, for example, the ratio between the film thickness of the first metal-containing layer (Ni film 9) in the nMOSFET region after the RIE and the film thickness of the first metal-containing layer (Ni film 9) in the pMOSFET region is 2: 3.

  Through the above steps, the metal-containing layer located on the gate electrode layer in the pMOSFET region has a different film thickness from the metal-containing layer located on the gate electrode layer in the nMOSFET region.

Next, as in Example 1, for example, RTA is performed at 500 ° C. for 30 seconds to silicide (alloy) the polysilicon layer 4. As a result, the Ni ₂ Si layer 4a is formed as the gate electrode of the nMOSFET region, and the Ni ₃ Si layer 4b is formed as the gate electrode of the pMOSFET (FIG. 5C).

  That is, the metal (Ni) contained in the first metal-containing layer (Ni film 9) is reacted with the gate electrode layer (polysilicon layer 4) in the pMOSFET region by heat treatment, and this gate electrode layer is alloyed. Turn into. Further, by the same heat treatment, the metal (Ni) contained in the first metal-containing layer (Ni film 9) reacts with the gate electrode layer (polysilicon layer 4) in the nMOSFET region, and this gate electrode layer is Alloy to form gate electrodes of different composition.

  Note that since the ratio of Ni alloying is higher in the gate electrode layer in the pMOSFET region, the volume of the gate electrode layer in the nMOSFET region is expanded (FIG. 5C).

  Similar to Example 1, since the thickness of the metal-containing layer on the gate electrode layer in the pMOSFET region is larger than the thickness of the metal-containing layer on the gate electrode layer in the nMOSFET region, the composition obtained by silicidation is also different. .

  Therefore, at this time, the threshold values of these nMOSFETs and pMOSFETs are different.

  Next, planarization is performed by CMP using the SiN film 7 as an etching stopper (FIG. 5D). However, it is not necessarily flat.

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process shown in FIG. 3A corresponds to the process shown in FIG. 5D.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

  In the first to third embodiments, the method of manufacturing a semiconductor device in which the gate electrode layer is silicided in order to change the threshold values of the pMOSFET and the nMOSFET has been described.

  In the fourth embodiment, a method for manufacturing a semiconductor device will be described in which the threshold value is changed by further incorporating a metal into the gate electrode layer after siliciding the gate electrode layer.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  6A to 6C are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

First, for example, a gate electrode layer (for example, Ni ₃ Si) made of an alloy containing at least one of Si and Ge in a region where the gate electrode of the pMOSFET is formed by the process described in the first to third embodiments. Layer) 4b. Similarly, a gate electrode layer (for example, Ni ₂ Si layer) 4a made of an alloy containing at least one of Si or Ge and having a composition different from that of the gate electrode layer 4b is formed in a region where the gate electrode of the nMOSFET is formed.

  Further, a photosensitive organic film 20 is formed on the gate electrode layer 4a and the gate electrode layer 4b.

  Further, the photosensitive organic film 20 located above the gate electrode layer 4a is selectively removed by lithography to expose the gate electrode layer 4a (FIG. 6A).

  Next, an Al film 21 that is a diffusion metal-containing layer is formed on the gate electrode layer 4a and the photosensitive organic film 20 by sputtering (FIG. 6B).

  Note that the diffusion metal-containing layer is formed of at least one of Ni, Co, Pt, Ti, Hf, Zr, Y, La, Ta, In, Ga, Tl, and W instead of Al, or Ni, Co, You may make it contain either the alloy containing at least 1 metal of Pt, Ti, Hf, Zr, Al, Y, La, Ta, In, Ga, Tl, and W. One or more layers may be stacked.

  Next, by heat treatment (for example, RTA at 500 ° C. for 30 seconds), the metal Al contained in the diffusion metal-containing layer (Al film 21) is converted into the interface between the gate insulating film 3 and the gate electrode layer 4a (that is, the gate It diffuses and segregates in the gate electrode layer 4a so as to reach the interface between the insulating film and the gate electrode.

Thereby, the threshold value of the gate electrode of the nMOSFET can be changed more significantly as compared with the case where Al is not diffused into the gate electrode layer (Ni ₂ Si film) 4a.

  Further, for example, the Al film 21 and the photosensitive organic material are mixed with sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM), a mixed solution of sulfuric acid and ozone (SOM), a mixed solution of sulfuric acid, hydrogen peroxide solution, and ozone. The film 20 is removed simultaneously (FIG. 6C).

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process shown in FIG. 3A corresponds to the process shown in FIG. 6C.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

  In the fourth embodiment, the method for manufacturing a semiconductor device is described in which the threshold value is changed by further diffusing metal into the gate electrode layer after siliciding the gate electrode layer.

  In the fifth embodiment, another method of manufacturing a semiconductor device in which the threshold value is changed by further diffusing metal into the gate electrode layer after siliciding the gate electrode layer will be described.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  7A to 7C are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the semiconductor device manufacturing method according to the fifth embodiment of the present invention. In the figure, the same reference numerals as in the fourth embodiment indicate the same configurations as in the fourth embodiment.

First, similarly to Example 4 described above, a gate electrode layer (for example, Ni ₃ Si layer) 4b made of an alloy containing at least one of Si or Ge is formed in a region where the gate electrode of the pMOSFET is formed. Similarly, a gate electrode layer (for example, Ni ₂ Si layer) 4a made of an alloy containing at least one of Si or Ge and having a composition different from that of the gate electrode layer 4b is formed in a region where the gate electrode of the nMOSFET is formed.

  Next, a TiN film 22 which is a diffusion preventing layer for preventing metal diffusion is formed on the gate electrode layer 4a and the gate electrode layer 4b.

  The diffusion prevention layer 22 is replaced with TiN, and any of W, WN, TaN, HfN, ZrN, TaC, and MoN, or any of TiN, W, WN, TaN, HfN, ZrN, TaC, and MoN. An alloy including One or more layers may be stacked.

  Further, a photosensitive organic film 23 such as a resist or polyimide is formed above the gate electrode layer 4a and the gate electrode layer 4b.

  Thereafter, the photosensitive organic film 23 positioned above the gate electrode layer 4a is selectively removed by lithography, for example.

  Further, the TiN film 22 located on the gate electrode layer 4a is selectively removed by etching or dry etching using the photosensitive organic film 23 as a mask. Thereby, the gate electrode layer 4a is exposed (FIG. 7A). Etching with a chemical solution includes hydrogen peroxide solution, hydrofluoric acid, a mixture solution of hydrofluoric acid and hydrogen peroxide solution, a mixture solution of hydrofluoric acid and nitric acid, hydrochloric acid, a mixture solution of hydrochloric acid and hydrogen peroxide solution, hydrochloric acid and nitric acid. Liquid mixture of sulfuric acid, sulfuric acid and hydrogen peroxide solution, ammonia water, ammonia water and hydrogen peroxide solution, choline, choline and hydrogen peroxide solution, TMAH, TMAH and hydrogen peroxide solution It is possible to use a mixed solution of Further, as dry etching, etching using a gas containing chlorine or fluorine can be used.

  Thereafter, the remaining photosensitive organic film 23 is removed by ashing or an organic solvent. At this time, when a resist containing a novolac resin is used for the photosensitive film, it is desirable to remove it. However, when a polyimide or the like is used, it is not always necessary to remove it.

  Next, an Al film 24 that is a diffusion metal-containing layer containing a metal to be diffused into the gate electrode layer 4a is formed on the gate electrode layer 4a and the TiN film 22 by, for example, sputtering (FIG. 7B).

  The diffusion metal-containing layer is made of Ni, Co, Pt, Ti, Hf, Zr, Y, La, Ta, In, Ga, Tl, or W, or Ni, Co, Pt, instead of Al. You may make it contain either the alloy containing at least 1 metal of Ti, Hf, Zr, Al, Y, La, Ta, In, Ga, Tl, and W. One or more layers may be stacked.

  Next, by heat treatment (for example, RTA at 500 ° C. for 30 seconds), the metal Al contained in the diffusion metal-containing layer (Al film 21) is converted into the interface between the gate insulating film 3 and the gate electrode layer 4a (that is, the gate It diffuses and segregates in the gate electrode layer 4a so as to reach the interface between the insulating film and the gate electrode.

Thereby, the threshold value of the gate electrode of the nMOSFET can be changed more significantly as compared with the case where Al is not diffused into the gate electrode layer (Ni ₂ Si film) 4a.

  Further, for example, the Al film 21 and the TiN film 22 are made of sulfuric acid, a mixed liquid of sulfuric acid and hydrogen peroxide solution (SPM), a mixed liquid of sulfuric acid and ozone (SOM), a mixed liquid of sulfuric acid, hydrogen peroxide solution, and ozone. Are simultaneously removed (FIG. 7C).

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process illustrated in FIG. 3A corresponds to the process illustrated in FIG. 7C.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

  When the photosensitive organic film 23 is not removed, sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM), a mixed solution of sulfuric acid and ozone (SOM), sulfuric acid, hydrogen peroxide solution and ozone are used as chemical solutions. If a mixed solution of the above is used, the photosensitive organic film 23 and the diffusion preventing layer can be removed at the same time.

  Further, when the photosensitive organic film 23 is removed, a mixed solution of sulfuric acid and hydrogen peroxide solution, a mixed solution of hydrochloric acid and nitric acid, a mixed solution of hydrochloric acid and hydrogen peroxide solution, a mixed solution of ammonia water and hydrogen peroxide solution. , Tetramethylammonium hydroxide (TMAH) and hydrogen peroxide solution mixture, Choline and hydrogen peroxide solution mixture, inorganic acid, organic acid, acid and oxidant mixture, inorganic alkali, organic alkali, alkali A mixture of oxidant and oxidant can be used.

  In addition, as oxidizing agents, hydrogen peroxide, ozone, nitric acid, sulfuric acid, chlorous acid, perchloric acid, hypochlorous acid, iodic acid, periodic acid, bromic acid, perbromic acid, chromic acid, permanganese An acid or the like can be used.

  In the first to third embodiments, the method of manufacturing a semiconductor device in which the gate electrode layer is silicided in order to change the threshold values of the pMOSFET and the nMOSFET has been described.

  In the sixth embodiment, a method for manufacturing a semiconductor device in which the threshold value is changed by silicidizing the gate electrode layer and diffusing metal into the gate electrode layer will be described.

  The manufacturing method of the semiconductor device according to the sixth embodiment is the same as the steps from FIGS. 1A to 1I described in the first embodiment.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  8A to 8D are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the method of manufacturing a semiconductor device according to the sixth embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment indicate the same configurations as those in the first embodiment.

  First, after forming the HfSiON film 3 as a gate insulating film and the polysilicon layer 4 as a gate electrode layer by the steps of FIGS. 1A to 1I described above (FIG. 1I), the natural oxide film and the like are removed, On the silicon layer 4, a Ni film 9 which is a first metal-containing layer is formed by sputtering.

  Further, an Al film 25 that is a diffusion metal-containing layer containing a metal for diffusing into the gate electrode layer 4 is formed on the Ni film 9 by, for example, sputtering.

  Then, a photosensitive organic film 10 such as a resist or polyimide is formed on the Al film 25.

  Then, the photosensitive organic film 10 located above the polysilicon layer 4 in the pMOSFET region is selectively removed by lithography.

  Further, using the remaining photosensitive organic film 10 as a mask, the Al film 25 on the Ni film 9 is selectively removed by dry etching or wet etching.

  As a result, a portion of the Ni film 9 located above the gate electrode layer 4 in the pMOSFET region is exposed (FIG. 8A).

Here, for the dry etching, for example, a gas containing Cl such as Cl ₂ or BCl ₃ is used.

In the wet etching, for example, an acid containing hydrochloric acid, hydrofluoric acid, sulfuric acid, nitric acid or the like, a mixed solution of an acid and an oxidizing agent (for example, H ₂ O ₂ or ozone), NH ₄ OH, TMAH, choline, etc. A mixed liquid of an alkali or an alkali and an oxidizing agent (for example, H ₂ O ₂ or ozone) is used.

  Note that the diffusion metal-containing layer is formed of at least one of Ni, Co, Pt, Ti, Hf, Zr, Y, La, Ta, In, Ga, Tl, and W instead of Al, or Ni, Co, You may make it contain either the alloy containing at least 1 metal of Pt, Ti, Hf, Zr, Al, Y, La, Ta, In, Ga, Tl, and W. One or more layers may be stacked.

  The first metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, La, or Ni, Co, Pt, Ti, Hf, Zr, Al, instead of Ni. You may make it contain the alloy containing either of La. One or more layers may be stacked.

  Next, a Ni film 19 as a second metal-containing layer is formed on the photosensitive organic film 10 and the Ni film 9 by sputtering (FIG. 8B).

  The second metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, Pd, and La, or Ni, Co, Pt, Ti, Hf, Zr, instead of Ni. You may make it contain the alloy containing either Al, Pd, or La. One or more layers may be stacked.

  In this embodiment, for example, the film is formed so that the ratio of the film thickness of the first metal-containing layer (Ni film 9) to the film thickness of the second metal-containing layer (Ni film 19) is 2: 1. To do.

  Through the above steps, the metal-containing layer located on the gate electrode layer in the pMOSFET region has a different film thickness from the metal-containing layer located on the gate electrode layer in the nMOSFET region. In addition, when the compositions of the first metal-containing layer and the second metal-containing layer are different, the laminated structure is different.

Next, similarly to Example 1, heat treatment (for example, RTA) is performed at 500 ° C. for 30 seconds, and the polysilicon layer 4 is silicided (alloyed). Thereby, the Ni ₂ Si layer 4a is formed as the gate electrode of the nMOSFET region, and the Ni ₃ Si layer 4b is formed as the gate electrode of the pMOSFET.

  Similar to the first embodiment, at this time, the threshold values of the nMOSFET and the pMOSFET are different.

  Furthermore, by the heat treatment, the metal Al contained in the diffusion metal-containing layer (Al film 25) reaches the interface between the gate insulating film 3 and the gate electrode layer 4a (that is, the interface between the gate insulating film and the gate electrode). In this manner, it is diffused and segregated in the gate electrode layer 4a (FIG. 8B).

Thereby, the threshold value of the gate electrode of the nMOSFET can be changed more significantly as compared with the case where Al is not diffused into the gate electrode layer (Ni ₂ Si film) 4a.

  Next, for example, the Al film 21 and the photosensitivity with sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM), a mixed solution of sulfuric acid and ozone (SOM), a mixed solution of sulfuric acid, hydrogen peroxide solution, and ozone. The organic film 20 is removed at the same time (FIG. 8C).

  Note that since the ratio of Ni alloying is higher in the gate electrode layer in the pMOSFET region, the volume of the gate electrode layer in the nMOSFET region is expanded (FIG. 8C).

  Next, planarization is performed by CMP using the SiN film 7 as an etching stopper (FIG. 8D). However, it is not always necessary to flatten.

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process shown in FIG. 3A corresponds to the process shown in FIG. 8D.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

  In the sixth embodiment, the semiconductor device manufacturing method in which the threshold value is changed by siliciding the gate electrode layer and diffusing metal in the gate electrode layer has been described.

  In the sixth embodiment, another method for manufacturing a semiconductor device in which the threshold value is changed by siliciding the gate electrode layer and diffusing metal in the gate electrode layer will be described.

  The manufacturing method of the semiconductor device according to the seventh embodiment is the same as the steps from FIGS. 1A to 1I described in the first embodiment.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  9A to 9D are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the semiconductor device manufacturing method according to Embodiment 7 of the present invention. In the figure, the same reference numerals as in the sixth embodiment indicate the same configurations as in the sixth embodiment.

  First, after forming the HfSiON film 3 as a gate insulating film and the polysilicon layer 4 as a gate electrode layer by the steps of FIGS. 1A to 1I described above (FIG. 1I), the natural oxide film and the like are removed, On the silicon layer 4, a Ni film 9 which is a first metal-containing layer is formed by sputtering.

  Further, an Al film 25 that is a diffusion metal-containing layer containing a metal for diffusing into the gate electrode layer 4 is formed on the Ni film 9 by, for example, sputtering.

  Further, a TiN film 10a which is a diffusion preventing layer for preventing metal diffusion is formed on the Al film 25. A photosensitive organic film 10b such as a resist or polyimide is formed on the TiN film 10a.

  Then, the photosensitive organic film 10b located above the polysilicon layer 4 in the pMOSFET region is selectively removed by lithography. Thereby, a portion of the TiN film 10a located above the gate electrode layer 4 in the pMOSFET region is exposed.

  Further, using the remaining photosensitive organic film 10 as a mask, hydrogen peroxide solution, hydrofluoric acid, a mixed solution of hydrofluoric acid and hydrogen peroxide solution, a mixed solution of hydrofluoric acid and nitric acid, a mixture of hydrochloric acid, hydrochloric acid and hydrogen peroxide solution Liquid, mixed liquid of hydrochloric acid and nitric acid, mixed liquid of sulfuric acid, sulfuric acid and hydrogen peroxide water, ammonia water, mixed liquid of ammonia water and hydrogen peroxide water, choline, mixed liquid of choline and hydrogen peroxide water, TMAH, TMAH The TiN film 10a located above the polysilicon layer 4 in the pMOSFET region is peeled off with a mixed solution of hydrogen peroxide and water. Thereby, the upper surface of the Al film 25 in the pMOSFET region is exposed. The TiN film 10a may be removed by RIE using the photosensitive organic film 10 as a mask.

  Further, using the remaining photosensitive organic film 10 as a mask, the Al film 25 on the Ni film 9 is selectively removed by dry etching or wet etching.

  As a result, a portion of the Ni film 9 located above the gate electrode layer 4 in the pMOSFET region is exposed (FIG. 9A).

Here, for the dry etching, for example, a gas containing Cl such as Cl ₂ or BCl ₃ is used.

In the wet etching, for example, an acid containing hydrochloric acid, hydrofluoric acid, sulfuric acid, nitric acid or the like, a mixed solution of an acid and an oxidizing agent (for example, H ₂ O ₂ or ozone), NH ₄ OH, TMAH, choline, etc. A mixed liquid of an alkali or an alkali and an oxidizing agent (for example, H ₂ O ₂ or ozone) is used.

  Note that the diffusion metal-containing layer is formed of at least one of Ni, Co, Pt, Ti, Hf, Zr, Y, La, Ta, In, Ga, Tl, and W instead of Al, or Ni, Co, You may make it contain either the alloy containing at least 1 metal of Pt, Ti, Hf, Zr, Al, Y, La, Ta, In, Ga, Tl, and W. One or more layers may be stacked.

  The first metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, La, or Ni, Co, Pt, Ti, Hf, Zr, Al, instead of Ni. You may make it contain the alloy containing either of La. One or more layers may be stacked.

  Next, a Ni film 19 that is a second metal-containing layer is formed on the photosensitive organic film 10 and the Ni film 9 by sputtering (FIG. 9B).

  The second metal-containing layer is made of any one of Co, Pt, Ti, Hf, Zr, Al, Pd, and La, or Ni, Co, Pt, Ti, Hf, Zr, instead of Ni. You may make it contain the alloy containing either Al, Pd, or La. One or more layers may be stacked.

  In this embodiment, for example, the film is formed so that the ratio of the film thickness of the first metal-containing layer (Ni film 9) to the film thickness of the second metal-containing layer (Ni film 19) is 2: 1. To do.

  Through the above steps, the metal-containing layer located on the gate electrode layer in the pMOSFET region has a different film thickness from the metal-containing layer located on the gate electrode layer in the nMOSFET region. In addition, when the compositions of the first metal-containing layer and the second metal-containing layer are different, the laminated structure is different.

Next, as in Example 6, heat treatment (for example, RTA at 500 ° C. for 30 seconds) is performed to silicidize (alloy) the polysilicon layer 4. Thereby, the Ni ₂ Si layer 4a is formed as the gate electrode of the nMOSFET region, and the Ni ₃ Si layer 4b is formed as the gate electrode of the pMOSFET.

  As in the sixth embodiment, at this time, the threshold values of the nMOSFET and the pMOSFET are different.

  Furthermore, by the heat treatment, the metal Al contained in the diffusion metal-containing layer (Al film 25) reaches the interface between the gate insulating film 3 and the gate electrode layer 4a (that is, the interface between the gate insulating film and the gate electrode). Thus, it is diffused and segregated in the gate electrode layer 4a (FIG. 9B).

Thereby, the threshold value of the gate electrode of the nMOSFET can be changed more significantly as compared with the case where Al is not diffused into the gate electrode layer (Ni ₂ Si film) 4a.

  Next, for example, the Al film 21 and the photosensitivity with sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM), a mixed solution of sulfuric acid and ozone (SOM), a mixed solution of sulfuric acid, hydrogen peroxide solution, and ozone. The organic film 20 is removed simultaneously (FIG. 9C).

  Note that since the ratio of Ni alloying is higher in the gate electrode layer in the pMOSFET region, the volume of the gate electrode layer in the nMOSFET region is expanded (FIG. 9C).

  Next, planarization is performed by CMP using the SiN film 7 as an etching stopper (FIG. 9D). However, it is not always necessary to flatten.

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process shown in FIG. 3A corresponds to the process shown in FIG. 9D.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

  In the sixth and seventh embodiments, the semiconductor device manufacturing method is described in which the threshold value is changed by siliciding the gate electrode layer and diffusing metal in the gate electrode layer.

  In the eighth embodiment, another method for manufacturing a semiconductor device will be described in which the threshold value is changed by siliciding the gate electrode layer and diffusing metal in the gate electrode layer.

  The manufacturing method of the semiconductor device according to the eighth embodiment is the same as the steps from FIGS. 1A to 1I described in the first embodiment.

  Hereinafter, description will be made with attention paid to the configuration of the gate electrode region of the pMOSFET and the nMOSFET.

  10A to 10D are cross-sectional views of main parts of the pMOSFET and nMOSFET regions in each step of the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention. In the figure, the same reference numerals as in the sixth embodiment indicate the same configurations as in the sixth embodiment.

  First, after forming the HfSiON film 3 as a gate insulating film and the polysilicon layer 4 as a gate electrode layer by the steps of FIGS. 1A to 1I described above (FIG. 1I), the natural oxide film and the like are removed, On the silicon layer 4, a Ni film 9 which is a first metal-containing layer is formed by sputtering.

  That is, the Ni film 9 as the first metal-containing layer is formed on the gate electrode layer in the pMOSFET region and the gate electrode layer (polysilicon layer 4) in the nMOSFET region.

  Further, a photosensitive organic film 10 such as a resist or polyimide is formed on the Ni film 9.

  Then, the photosensitive organic film 10 located above the polysilicon layer 4 in the nMOSFET region is selectively removed by lithography. As a result, a portion of the Ni film 9 located above the gate electrode layer in the nMOSFET region is exposed (FIG. 10A).

  Note that, as in Example 1, the first metal-containing layer was replaced with Ni, and any one of Co, Pt, Ti, Hf, Zr, Al, La, or Ni, Co, Pt, Ti , Hf, Zr, Al, or an alloy containing any one of La may be contained. One or more layers may be stacked.

  Next, the upper part of the Ni film 9 is selectively removed by RIE using the photosensitive organic film 10 as a mask. Thereby, the Ni film 9 located above the gate electrode layer in the nMOSFET region is thinned. The photosensitive organic film 10 is used as a protective film, and a mixture of hydrochloric acid, hydrochloric acid and hydrogen peroxide solution, a mixture of hydrochloric acid and nitric acid, hydrofluoric acid, a mixture of hydrofluoric acid and hydrogen peroxide, or a mixture of hydrofluoric acid and nitric acid. The upper portion of the Ni film 9 may be selectively removed by a mixed solution, a mixed solution of acid, an acid and an oxidizing agent, such as a mixed solution, sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution, or the like.

  In this embodiment, for example, the ratio between the film thickness of the first metal-containing layer (Ni film 9) in the nMOSFET region after the RIE and the film thickness of the first metal-containing layer (Ni film 9) in the pMOSFET region is 2: 3.

  Further, on the Ni film 9 and the photosensitive organic film 10, an Al film 25 that is a diffusion metal-containing layer containing a metal for diffusing into the gate electrode layer 4 is formed by sputtering, for example.

  Through the above steps, the metal-containing layer located on the gate electrode layer in the pMOSFET region has a different film thickness from the metal-containing layer located on the gate electrode layer in the nMOSFET region.

Next, as in Example 6, heat treatment (for example, RTA at 500 ° C. for 30 seconds) is performed to silicidize (alloy) the polysilicon layer 4. Thereby, the Ni ₂ Si layer 4a is formed as the gate electrode of the nMOSFET region, and the Ni ₃ Si layer 4b is formed as the gate electrode of the pMOSFET.

  As in the sixth embodiment, at this time, the threshold values of the nMOSFET and the pMOSFET are different.

  Furthermore, by the heat treatment, the metal Al contained in the diffusion metal-containing layer (Al film 25) reaches the interface between the gate insulating film 3 and the gate electrode layer 4a (that is, the interface between the gate insulating film and the gate electrode). Thus, it is diffused and segregated in the gate electrode layer 4a (FIG. 10B).

Thereby, the threshold value of the gate electrode of the nMOSFET can be changed more significantly as compared with the case where Al is not diffused into the gate electrode layer (Ni ₂ Si film) 4a.

  Next, for example, the Al film 21 and the photosensitivity with sulfuric acid, a mixed solution of sulfuric acid and hydrogen peroxide solution (SPM), a mixed solution of sulfuric acid and ozone (SOM), a mixed solution of sulfuric acid, hydrogen peroxide solution, and ozone. The organic film 20 is removed simultaneously (FIG. 10C).

  Note that since the ratio of Ni alloying is higher in the gate electrode layer in the pMOSFET region, the volume of the gate electrode layer in the nMOSFET region is expanded (FIG. 10C).

  Next, planarization is performed by CMP using the SiN film 7 as an etching stopper (FIG. 10D). However, it is not always necessary to flatten.

  The steps for wiring the nMOSFET and pMOSFET having the gate electrode formed as described above to form an LSI are the same as those in FIGS. 3A to 3D of the first embodiment. Note that the process shown in FIG. 3A corresponds to the process shown in FIG. 10D.

  As described above, according to the method for manufacturing a semiconductor device according to the present embodiment, a desired threshold value different between the pMOSFET and the nMOSFET can be obtained.

It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and pMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and pMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and pMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the area | region of nMOSFET and pMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 5 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention. It is sectional drawing of the principal part of the area | region of pMOSFET and nMOSFET in the process of the manufacturing method of the semiconductor device which concerns on Example 6 of this invention.

Explanation of symbols

1 Silicon substrate 2 STI
3 Hafnium silicate nitride film (HfSiON film)
4 Polysilicon layer 4a Ni ₂ Si layer 4b Ni ₃ Si layer 5 SiN film 51 SiN film 6 Source / drain silicide contact (NiPtSi layer)
7 SiN film 8 SiO ₂ layer 9, 19 Ni film 10, 10b, 20, 23 Photosensitive organic film 10a TiN film 11 SiN film 14 Interlayer insulating film SiO ₂ layer 15 Wiring layers 21, 24, 25 Diffusion metal containing layer 22 Diffusion Prevention layer

Claims (6)

A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
Forming a gate insulating film of a high dielectric insulating film on the semiconductor substrate;
A first gate electrode layer including at least one of Si or Ge is formed on the gate insulating film in a gate electrode region in which a gate electrode of the first conductivity type MOSFET is formed, and the second conductivity type MOSFET is Forming a second gate electrode layer containing at least one of Si or Ge on the gate insulating film in the gate electrode region where the gate electrode is formed;
Forming a first metal-containing layer on the first gate electrode layer and the second gate electrode layer;
Forming a film including a photosensitive organic film on the first metal-containing layer;
By selectively removing the film including the photosensitive organic film located above the first gate electrode layer, the portion of the first metal-containing layer located above the first gate electrode layer is removed. To expose
Forming a second metal-containing layer on the film including the photosensitive organic film and on the first metal-containing layer;
The metal contained in the first metal-containing layer and the second metal-containing layer reacts with the second gate electrode layer by heat treatment to alloy the second gate electrode layer. The semiconductor device characterized in that the second gate electrode layer is alloyed by reacting the metal contained in the first metal-containing layer with the second gate electrode layer by the heat treatment. Manufacturing method. A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
Forming a gate insulating film of a high dielectric insulating film on the semiconductor substrate;
A first gate electrode layer including at least one of Si or Ge is formed on the gate insulating film in a gate electrode region in which a gate electrode of the first conductivity type MOSFET is formed, and the second conductivity type MOSFET is Forming a second gate electrode layer containing at least one of Si or Ge on the gate insulating film in the gate electrode region where the gate electrode is formed;
Forming a first metal-containing layer on the first gate electrode layer and the second gate electrode layer;
Forming a diffusion prevention layer above the first metal-containing layer, and forming a photosensitive organic film on the diffusion prevention layer;
By selectively removing the photosensitive organic film located above the first gate electrode layer, a portion of the diffusion prevention layer located above the first gate electrode layer is exposed,
Removing the portion of the diffusion preventing layer to expose a portion of the first metal-containing layer located above the first gate electrode layer;
Forming a second metal-containing layer above the diffusion preventing layer and on the first metal-containing layer;
The metal contained in the first metal-containing layer and the second metal-containing layer reacts with the second gate electrode layer by heat treatment to alloy the second gate electrode layer. The semiconductor device characterized in that the second gate electrode layer is alloyed by reacting the metal contained in the first metal-containing layer with the second gate electrode layer by the heat treatment. Manufacturing method. After forming the first metal-containing layer, a diffusion metal-containing layer containing a metal for inclusion in the second gate electrode layer is further formed on the first metal-containing layer, and the diffusion metal-containing layer is formed. Forming a film containing the photosensitive organic film above the layer;
The first gate electrode of the first metal-containing layer is selectively removed by selectively removing the film including the photosensitive organic film positioned above the first gate electrode layer and the diffusion metal-containing layer. Exposing the part located above the layer,
Forming the second metal-containing layer on the film including the photosensitive organic film and on the first metal-containing layer;
The heat treatment causes the metal contained in the first metal-containing layer and the second metal-containing layer to react with the first gate electrode layer to alloy the first gate electrode layer. The metal contained in the first metal-containing layer reacts with the second gate electrode layer by the heat treatment, and the second gate electrode layer is alloyed and contained in the diffusion metal-containing layer. The method for manufacturing a semiconductor device according to claim 1, wherein the second metal is included in the second gate electrode layer. A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
Forming a gate insulating film of a high dielectric insulating film on the semiconductor substrate;
A first gate electrode layer including at least one of Si or Ge is formed on the gate insulating film in a gate electrode region in which a gate electrode of the first conductivity type MOSFET is formed, and the second conductivity type MOSFET is Forming a second gate electrode layer containing at least one of Si or Ge on the gate insulating film in the gate electrode region where the gate electrode is formed;
Forming a metal-containing layer on the first gate electrode layer and the second gate electrode layer;
Forming a film including a photosensitive organic film on the metal-containing layer;
By selectively removing the film including the photosensitive organic film located above the first gate electrode layer, a portion of the metal-containing layer located above the second gate electrode layer is exposed,
Thinning the portion of the metal-containing layer,
The metal contained in the metal-containing layer is reacted with the first gate electrode layer by heat treatment to alloy the first gate electrode layer, and the metal-containing layer is formed by the heat treatment. A method of manufacturing a semiconductor device, comprising reacting the contained metal and the second gate electrode layer to alloy the second gate electrode layer. A method for manufacturing a semiconductor device, wherein a first conductivity type MOSFET and a second conductivity type MOSFET having a conductivity type different from that of the first conductivity type MOSFET are formed on a semiconductor substrate,
A first gate electrode layer made of an alloy containing at least one of Si or Ge is formed in a region where the gate electrode of the first conductivity type MOSFET is formed, and the gate electrode of the second conductivity type MOSFET is formed. A second gate electrode layer made of an alloy containing at least one of Si or Ge and having a composition different from that of the first gate electrode layer,
Forming a film including a photosensitive organic film above the first gate electrode layer and the second gate electrode layer;
Selectively removing the film including the photosensitive organic film located above the second gate electrode layer to expose the second gate electrode layer;
Forming a diffusion metal-containing layer containing a metal for inclusion in the second gate electrode layer on the second gate electrode layer and on the film including the photosensitive organic film;
By heat treatment, the metal contained in the diffusion metal-containing layer is contained in the second gate electrode layer,
The method of manufacturing a semiconductor device, wherein the diffusion metal-containing layer and the film including the photosensitive organic film are simultaneously removed. 6. The semiconductor device according to claim 1, wherein the first metal-containing layer, the second metal-containing layer, and the film including the photosensitive organic film or the pre-diffusion preventive layer are simultaneously peeled off. Production method.

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