GB2418067A - Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process - Google Patents

Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process Download PDF

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Publication number
GB2418067A
GB2418067A GB0521254A GB0521254A GB2418067A GB 2418067 A GB2418067 A GB 2418067A GB 0521254 A GB0521254 A GB 0521254A GB 0521254 A GB0521254 A GB 0521254A GB 2418067 A GB2418067 A GB 2418067A
Authority
GB
United Kingdom
Prior art keywords
dielectric layer
enhance
patterned dielectric
uniformity
electroplating copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB0521254A
Other versions
GB2418067B (en
GB0521254D0 (en
Inventor
Gerd Franz Marxsen
Axel Preusse
Markus Nopper
Frank Mauersberger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10319135A external-priority patent/DE10319135B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of GB0521254D0 publication Critical patent/GB0521254D0/en
Publication of GB2418067A publication Critical patent/GB2418067A/en
Application granted granted Critical
Publication of GB2418067B publication Critical patent/GB2418067B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches (205), a surface roughness is created by e.g. reducing the amount of leveler in the plating bath at least on non-patterned regions (206) of the dielectric layer (203) to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.

Description

GB 2418067 A continuation (72) Inventor(s): Gerd Franz Marxsen Axel
Preusse Markus Napper Frank Mauersberger (74) Agent and/or Address for Service: Brookes Batchellor LLP 102-108 Clerkenwell Road, LONDON, EC1M USA, United Kingdom
GB0521254A 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process Expired - Fee Related GB2418067B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10319135A DE10319135B4 (en) 2003-04-28 2003-04-28 A method of electroplating copper over a patterned dielectric layer to improve process uniformity of a subsequent CMP process
US10/666,195 US6958247B2 (en) 2003-04-28 2003-09-19 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process
PCT/US2003/041181 WO2004097932A2 (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process

Publications (3)

Publication Number Publication Date
GB0521254D0 GB0521254D0 (en) 2005-11-30
GB2418067A true GB2418067A (en) 2006-03-15
GB2418067B GB2418067B (en) 2007-02-14

Family

ID=33419999

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0521254A Expired - Fee Related GB2418067B (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process

Country Status (5)

Country Link
JP (1) JP2006515467A (en)
KR (1) KR101136139B1 (en)
AU (1) AU2003302261A1 (en)
GB (1) GB2418067B (en)
WO (1) WO2004097932A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100761360B1 (en) * 2006-03-29 2007-09-27 주식회사 하이닉스반도체 Method for fabricating metal line in flash memory device
US10541140B2 (en) 2011-01-26 2020-01-21 Macdermid Enthone Inc. Process for filling vias in the microelectronics
US20230279576A1 (en) * 2022-03-03 2023-09-07 Applied Materials, Inc. Plating and deplating currents for material co-planarity in semiconductor plating processes
US20230304183A1 (en) * 2022-03-22 2023-09-28 Applied Materials, Inc. Methods and apparatus for altering lithographic patterns to adjust plating uniformity

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179691B1 (en) * 1999-08-06 2001-01-30 Taiwan Semiconductor Manufacturing Company Method for endpoint detection for copper CMP
EP1191128A2 (en) * 2000-09-20 2002-03-27 Ebara Corporation Plating method and plating apparatus
US20020175080A1 (en) * 2001-03-23 2002-11-28 Ivo Teerlinck Multi-step method for metal deposition

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891161B2 (en) 1996-02-15 1999-05-17 日本電気株式会社 Wiring formation method
KR20000043909A (en) * 1998-12-29 2000-07-15 김영환 Method for forming metal line of semiconductor device
KR20000056852A (en) * 1999-02-26 2000-09-15 로버트 에이치. 씨. 챠오 Method of fabricating a metal-interconnect structure in integrated circuit
US6350364B1 (en) * 2000-02-18 2002-02-26 Taiwan Semiconductor Manufacturing Company Method for improvement of planarity of electroplated copper
JP3725054B2 (en) * 2000-09-20 2005-12-07 株式会社荏原製作所 Electrolytic plating method and electrolytic plating apparatus for substrate
JP3797860B2 (en) * 2000-09-27 2006-07-19 株式会社荏原製作所 Plating apparatus and plating method
JP2003068689A (en) * 2001-08-22 2003-03-07 Tokyo Seimitsu Co Ltd Apparatus for feedback polishing and method for polishing
JP3807295B2 (en) * 2001-11-30 2006-08-09 ソニー株式会社 Polishing method
JP2003277985A (en) * 2002-03-20 2003-10-02 Fujitsu Ltd Plating film forming method and plating film forming apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179691B1 (en) * 1999-08-06 2001-01-30 Taiwan Semiconductor Manufacturing Company Method for endpoint detection for copper CMP
EP1191128A2 (en) * 2000-09-20 2002-03-27 Ebara Corporation Plating method and plating apparatus
US20020175080A1 (en) * 2001-03-23 2002-11-28 Ivo Teerlinck Multi-step method for metal deposition

Also Published As

Publication number Publication date
KR101136139B1 (en) 2012-04-20
KR20060008946A (en) 2006-01-27
WO2004097932A2 (en) 2004-11-11
GB2418067B (en) 2007-02-14
WO2004097932A3 (en) 2004-12-16
AU2003302261A1 (en) 2004-11-23
GB0521254D0 (en) 2005-11-30
JP2006515467A (en) 2006-05-25

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)

Free format text: REGISTERED BETWEEN 20091210 AND 20091216

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20111222