WO2004097932A3 - Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process - Google Patents

Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process Download PDF

Info

Publication number
WO2004097932A3
WO2004097932A3 PCT/US2003/041181 US0341181W WO2004097932A3 WO 2004097932 A3 WO2004097932 A3 WO 2004097932A3 US 0341181 W US0341181 W US 0341181W WO 2004097932 A3 WO2004097932 A3 WO 2004097932A3
Authority
WO
WIPO (PCT)
Prior art keywords
dielectric layer
enhance
patterned dielectric
uniformity
electroplating copper
Prior art date
Application number
PCT/US2003/041181
Other languages
French (fr)
Other versions
WO2004097932A2 (en
Inventor
Gerd Franz Marxsen
Axel Preusse
Markus Nopper
Frank Mauersberger
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE10319135A external-priority patent/DE10319135B4/en
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Priority to GB0521254A priority Critical patent/GB2418067B/en
Priority to AU2003302261A priority patent/AU2003302261A1/en
Priority to JP2004571478A priority patent/JP2006515467A/en
Priority to KR1020057020605A priority patent/KR101136139B1/en
Publication of WO2004097932A2 publication Critical patent/WO2004097932A2/en
Publication of WO2004097932A3 publication Critical patent/WO2004097932A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

In a new method of plating metal onto dielectric layers including small diameter vias and large diameter trenches (205), a surface roughness is created by e.g. reducing the amount of leveler in the plating bath at least on non-patterned regions (206) of the dielectric layer (203) to enhance the uniformity of material removal in a subsequent chemical mechanical polishing (CMP) process.
PCT/US2003/041181 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process WO2004097932A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
GB0521254A GB2418067B (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process
AU2003302261A AU2003302261A1 (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process
JP2004571478A JP2006515467A (en) 2003-04-28 2003-12-22 Method for electroplating copper on a patterned dielectric layer to improve process uniformity of a subsequent chemical mechanical polishing (CMP) process
KR1020057020605A KR101136139B1 (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10319135A DE10319135B4 (en) 2003-04-28 2003-04-28 A method of electroplating copper over a patterned dielectric layer to improve process uniformity of a subsequent CMP process
DE10319135.6 2003-04-28
US10/666,195 US6958247B2 (en) 2003-04-28 2003-09-19 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent CMP process
US10/666,195 2003-09-19

Publications (2)

Publication Number Publication Date
WO2004097932A2 WO2004097932A2 (en) 2004-11-11
WO2004097932A3 true WO2004097932A3 (en) 2004-12-16

Family

ID=33419999

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2003/041181 WO2004097932A2 (en) 2003-04-28 2003-12-22 Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process

Country Status (5)

Country Link
JP (1) JP2006515467A (en)
KR (1) KR101136139B1 (en)
AU (1) AU2003302261A1 (en)
GB (1) GB2418067B (en)
WO (1) WO2004097932A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100761360B1 (en) * 2006-03-29 2007-09-27 주식회사 하이닉스반도체 Method for fabricating metal line in flash memory device
JP5981455B2 (en) * 2011-01-26 2016-08-31 エンソン インコーポレイテッド Filling via holes in the microelectronics industry
US20230279576A1 (en) * 2022-03-03 2023-09-07 Applied Materials, Inc. Plating and deplating currents for material co-planarity in semiconductor plating processes
US20230304183A1 (en) * 2022-03-22 2023-09-28 Applied Materials, Inc. Methods and apparatus for altering lithographic patterns to adjust plating uniformity

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179691B1 (en) * 1999-08-06 2001-01-30 Taiwan Semiconductor Manufacturing Company Method for endpoint detection for copper CMP
EP1191128A2 (en) * 2000-09-20 2002-03-27 Ebara Corporation Plating method and plating apparatus
US20020175080A1 (en) * 2001-03-23 2002-11-28 Ivo Teerlinck Multi-step method for metal deposition

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2891161B2 (en) 1996-02-15 1999-05-17 日本電気株式会社 Wiring formation method
KR20000043909A (en) * 1998-12-29 2000-07-15 김영환 Method for forming metal line of semiconductor device
KR20000056852A (en) * 1999-02-26 2000-09-15 로버트 에이치. 씨. 챠오 Method of fabricating a metal-interconnect structure in integrated circuit
US6350364B1 (en) * 2000-02-18 2002-02-26 Taiwan Semiconductor Manufacturing Company Method for improvement of planarity of electroplated copper
JP3725054B2 (en) * 2000-09-20 2005-12-07 株式会社荏原製作所 Electrolytic plating method and electrolytic plating apparatus for substrate
JP3797860B2 (en) * 2000-09-27 2006-07-19 株式会社荏原製作所 Plating apparatus and plating method
JP2003068689A (en) * 2001-08-22 2003-03-07 Tokyo Seimitsu Co Ltd Apparatus for feedback polishing and method for polishing
JP3807295B2 (en) * 2001-11-30 2006-08-09 ソニー株式会社 Polishing method
JP2003277985A (en) * 2002-03-20 2003-10-02 Fujitsu Ltd Plating film forming method and plating film forming apparatus

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6179691B1 (en) * 1999-08-06 2001-01-30 Taiwan Semiconductor Manufacturing Company Method for endpoint detection for copper CMP
EP1191128A2 (en) * 2000-09-20 2002-03-27 Ebara Corporation Plating method and plating apparatus
US20020175080A1 (en) * 2001-03-23 2002-11-28 Ivo Teerlinck Multi-step method for metal deposition

Also Published As

Publication number Publication date
WO2004097932A2 (en) 2004-11-11
KR20060008946A (en) 2006-01-27
GB0521254D0 (en) 2005-11-30
JP2006515467A (en) 2006-05-25
KR101136139B1 (en) 2012-04-20
GB2418067A (en) 2006-03-15
AU2003302261A1 (en) 2004-11-23
GB2418067B (en) 2007-02-14

Similar Documents

Publication Publication Date Title
EP1261021A3 (en) Method of production of circuit board, semiconductor device, and plating system
EP1167585A3 (en) Method and apparatus for forming interconnects, and polishing liquid and polishing method
IL157828A0 (en) Semiconductor structure implementing sacrificial material and methods for making and implementing the same
EP1843383A3 (en) Patterns of conductive objects on a substrate and method of producing thereof
MY136159A (en) Apparatus and method for depositing and planarizing thin films of semiconductor wafers
EP1122989A3 (en) Method of plating for filling via holes
EP1361023A3 (en) Polishing articles for electrochemical mechanical polishing of substrates
WO2006060520A3 (en) Membrane-limited selective electroplating of a conductive surface
WO2005113164A3 (en) Superconductor fabrication processes
CN1156948A (en) Method of making circuitized substrate using two different metallization processes
ATE445034T1 (en) INTEGRATED METAL DEPOSITION AND PLANARIZATION METHOD AND APPARATUS THEREOF
US7562447B2 (en) Method of manufacturing printed circuit board for fine circuit formation
WO2004097932A3 (en) Method of electroplating copper over a patterned dielectric layer to enhance process uniformity of a subsequent cmp process
SG128453A1 (en) Metal barrier cap fabrication by polymer lift-off
US7670473B1 (en) Workpiece surface influencing device designs for electrochemical mechanical processing and method of using the same
EP1229580A3 (en) Electrochemical reduction of copper seed for reducing voids in electrochemical deposition
SG147420A1 (en) Method of forming an in-situ recessed structure
WO2002092878A3 (en) Electroless plating method and device, and substrate processing method and apparatus
US7247560B1 (en) Selective deposition of double damascene metal
MXPA05008066A (en) Sacrificial metal liner for copper interconnects.
US9496172B2 (en) Method for forming interconnection structures
WO2003038890A3 (en) Method for planarization etch with in-situ monitoring by interferometry prior to recess etch
WO2003085166A3 (en) Electroless deposition methods
TW200644160A (en) Method for fabricating metal line in semiconductor device
WO2004068576A3 (en) Method of forming a catalyst containing layer over a patterned dielectric

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DK DM DZ EC EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ OM PH PL PT RO RU SC SD SE SG SK SL TJ TM TN TR TT TZ UA UG UZ VC VN YU ZA ZM ZW

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): BW GH GM KE LS MW MZ SD SL SZ TZ UG ZM ZW AM AZ BY KG KZ MD RU TJ TM AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LU MC NL PT RO SE SI SK TR BF BJ CF CG CI CM GA GN GQ GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: 0521254

Country of ref document: GB

WWE Wipo information: entry into national phase

Ref document number: 2004571478

Country of ref document: JP

Ref document number: 20038B02869

Country of ref document: CN

Ref document number: 1020057020605

Country of ref document: KR

WWP Wipo information: published in national office

Ref document number: 1020057020605

Country of ref document: KR

122 Ep: pct application non-entry in european phase