GB2413699A - Overvoltage protection device and manufacturing process - Google Patents
Overvoltage protection device and manufacturing process Download PDFInfo
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- GB2413699A GB2413699A GB0409591A GB0409591A GB2413699A GB 2413699 A GB2413699 A GB 2413699A GB 0409591 A GB0409591 A GB 0409591A GB 0409591 A GB0409591 A GB 0409591A GB 2413699 A GB2413699 A GB 2413699A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0626—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a localised breakdown region, e.g. built-in avalanching region
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
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Abstract
An overvoltage protection device has a voltage-limiting region 33 parallel to its central junction to produce a transverse junction breakdown. The spacing between the voltage-limiting region and the central junction defines the breakdown voltage. Via varying the size and location of the voltage-limiting region, the protection device can has various breakdown voltages and lower breakover currents. Thereby, the sensitivity of the protection device can be
Description
OVERVOLTAGE PROTECTION DEVICE AND
MANUFACTURING PROCESS FOR THE SAME
FIELD OF THE INVENTION
The present invention is directed to an overvoltage protection device and s manufacturing process for the same, and more particularly, to an overvoltage protection device having a voltage-limiting region disposed on a central contacting surface thereof for defining the breakdown voltage and breakover current.
BACKGROUND OF THE INVENTION
To Recently, manufacturing processes for electronic components have become more and more precise and also the sizes of such components have become smaller and smaller. Hence, the devices used to protect electronic components from the damage resulting from electric effects, such as static electricity, overvoltage, electric arc and so on, are also becoming more and more important. For instance, thyristor overvoltage protection devices are extensively used in the modern communication systems. These devices are used to protect the communication system from damage resulting from lighting strikes on transmission lines, short circuits of neighboring power lines or other unexpected events. These devices can prevent any damage resulting from the overvoltage effects.
A thyristor overvoltage protection device is a semiconductor device designed to lead the overvoltage surge away from the transmission line before it reaches the communication system. Hence, it can be used to protect the communication system. When the system operates regularly, this protection device is kept in a high-resistance status, i.e. in an off status. At this moment, only Ike leakage current, which is lower than a microampere, can pass through this device. lIence, it won't affect the operation of the whole system. When an overvoltage surge occurs on the transmission lines, this device will switch to a low-resistance status, i. e. an on status. Thereby, this device can lead the overvoltage surge away from the communication system. After the overvoltage surge passes away, the overvoltage protection device will switch back to the off status and the communication system will return to regular operations.
The characteristics of the current and voltage of this overvoltage protection device are shown in fig. 1, which is a curve diagram of the voltage (V) versus the current (I) of the conventional overvoltage protection device.
In general, the thyristor overvoltage protection device has two metal electrodes and a four-layer semiconductor structure, for example, composed of NPNP-type or PNPN-type layers. The top layer of this protection device Is an emitter region, i.e. the cathode region; the second layer is a base region; the third layer is a substrate region; and the fourth layer is an anode region. Therein, the two metal electrodes are disposed on the surfaces of the emitter region and the anode region, respectively.
The junction between the base region and the substrate region is the central junction of this protection device. Under regular operation, the central junction will be reverse biased. When the reverse bias increases, the central junction will breakdown. As shown in the figure, when the breakdown current reaches 1 mA, the voltage across the protection device is defined as the breakdown voltage (Vz). If the voltage increases constantly at this moment, the breakdown current will increase rapidly and make the protection device switch to the on status. The voltage and current for malting the protection switch to the on status are defined as to breakover voltage (VBO) and the breakover current (IBO). When the overvoltage surge occurs and reaches the breakover voltage (VBO), the overvoltage protection device will turn on to lead the induced current through the protection device and keep the voltage across the protection device in a relatively low value. When the overvoltage surge passes away, the current passing through the protection device will decrease constantly. When the current is lower than the holding current (IEl) of the protection device, the overvoltage protection device will switch back to the off status (as shown in the figure) to make the voltage across the protection device return to normal and malce the communication system operate regularly.
Reference is made to fig. 2, which is a schematic diagram of a overvoltage protection device disclosed in U.S. Patent No. 4,967,256. The thyristor overvoltage protection device has a four-layer semiconductor Structure (PNPN), including emitter regions 22 (n - ), shorting dots 23 (referred to as "holes" in US '256) disposed between the emitter regions 22, a substrate 20, a single buried region25 (n) disposed inside the substrate 20, a base region 21 (p+), an anode region 24, a first metal electrode region 26 connected with the upper components, a second metal electrode region 27 connected with the lower components and a guard ring 28 (n++) surrounding the central junction. The guard ring 28 is used to make the potential difference of the component surface evenly distributed to improve the stability of the whole device. Further, the guard ring 28 won't result in the breakdown of this semiconductor device.
As shown in fig. 2, the buried region 25 and the substrate 20 both are Ntype semiconductors, but the buried region 25 has a higher impurity concentration. The breakdown voltage of the junction between the buried region and the substrate 20 is lower than that between the base region 21 and the substrate 20. I-Ience, when the voltage across the protection device increases, the breakdown effect will first occur at the junction between the base region 21 and the buried region 25 and make the breakdown current pass through the buried lO region 25 first. This effect can improve the precision for controlling the breakdown voltage during manufacturing process of the device. Further, it can make this device leave a breakover current even lower than that of the traditional device without the buried region.
However, in application, this overvoltage protection device still has ] 5 drawbacks. Since it employs a single buried region with relative small size, its conductivity will be limited during the on status. Hence, it will cause a bottleneck effect, which will lower the current carrying capacity of the device.
In order to prevent the bottleneck effect, U.S Patents No. 5,001,537 and No. 5,516,705 disclose two kinds of overvoltage protection devices employing 2() multiple buried regions. However, since the operation principle of the devices is still unchanged, i.e., as described above, controlling the breakdown voltage and breakover current via employing the effect that the junction between the base region and the buried region will breakdown first, which is different to the present invention. s
SUMMARY OF THE INVENTION
An objective of the present invention is to provide an overvoltage protection device and manufacturing process for the same.
In one embodiment a voltage-limiting region is peripherally disposed about s the central junction of the overvoltage protection device during the manufacturing process for defining the breakdown voltage and the breakover current of the device. The device exhibits a transverse junction breakdown.
The conventional buried region can be omitted, resulting in a higher current carrying capacity.
to The voltage-limiting region can be used to define the breakdown voltage and breakover current of the protection device. By varying the size and location of the voltage-limiting region, the sensitivity of the protection device for the overvoltage surge can be improved considerably.
Furthermore, in one embodiment the manufacturing process of the present invention forms a first masking layer on a substrate, etches the first masking layer to form a plurality of masking regions to define a first region and a second region, forms the base region in the second region, forms the voltage limiting region in the first region; forms an emitter region on the base region, and forms an electrode region on the emitter region.
Numerous additional features, benefits and details are described in the
detailed description, which follows.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention w ill be more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein: Iig. 1 is a curve diagram of the voltage (V) versus the current (I) of the conventional overvoltage protection device; Fig. 2 is a schematic diagram of a overvoltage protection device disclosed in U.S. Patent No. 4,967,256; Fig. 3 is a cross-sectional diagram of an overvoltage protection device in accordance with the present invention; Fig. 4a is a top-view diagram of the first embodiment of the overvoltage protection device in accordance with the present invention; Fig. 4b is a top-view diagram of the second embodiment of the overvoltage protection device in accordance with the present invention; Fig. 4c is a top-view diagram of the third embodiment of the overvoltage protection device in accordance with the present invention; Fig. 5 is a schematic diagram of a bi-directional overvoltage protection device in accordance with the present invention; and Figs. 6a6f illustrate a manufacturing process of the overvoltage protection device in accordance with the present invention.
DETALED DESCRIPTION
Reference is made to fig. 3, which is a cross-sectional diagram of an overvoltage protection device in accordance with the present invention. As does the prior art, it also has a four-layer interleaving semiconductor structure (PNI'N). Therein, a P-type base region 32, which has a relatively high impurity concentration (p+), is disposed on an N-type substrate 30, which has a relatively low impurity concentration (n-). An anode region 32' is disposed on the other side of the device. The base region 32 has emitter regions 34 disposed thereon.
The f mister regions, 3,4 hake a high impurity concentration and have multiple emitter shorting dots (holes) 35 formed therebetween. The PN junction between the base region 32 and the substrate 30 is the central junction of the protection device.
The present invention further disposes a voltage-limiting region 33, which is shaped as a ring, a partial ring or segmented pieces and has higher impurity concentration (n+), parallel to the central junction. Further, the protection device has a first electrode region 31 and a second electrode region 31' disposed on its upper and lower surfaces, respectively.
The voltage-limiting region 33 is made of an N-type semiconductor with a relatively high impurity concentration. Since its impurity concentration is higher than that of the substrate 30, the transverse breakdown voltage of the base region 32 is lower than the PN junction located between the lower portion of the base region 32 and the substrate 30. Hence, the breakdown voltage of the protection device is primarily determined according to the spacing between the base region 32 (p+) and the voltagelimiting region 33. The larger the spacing is, the higher the breakdown voltage is that can be obtained. Conversely, the smaller the spacing is, the lower the breakdown voltage is that can be obtained.
In practical application, the breakdown voltage can be changed via adjusting the spacing between the voltage-limiting region 33 and the base region 32 according to practical needs.
As shown in fig. 3, the voltage-limiting region 33 is disposed on one side of the base region 32. In practice, it is not limited. The total length of the voltage-limiting region 33 can be used to determine the breakover current of the overvoltage protection device. In other words, a breakdown region is formed between the voltage-limiting region 33 and the base region 32 and the breakdown current can only pass through this region. When the breakdown phenomenon occurs, the total length of the voltage-limiting region 33 will dominate the size of the breakdown region and control the amount of the breakdown current passing through this breakdown region. Therein, if the length of the voltage-limiting region 33 is short, the breakdown region will be small and tlae breakdown current will be low. As shown in fig. 1, when the protection device is switched to the on status, the breakdown current is defined as the breakover current (IBO) of the protection device. Hence, using the voltage-limiting region 33 with short length can lower the breakover current (IBO) effectively. Further, since the breakover current for switching the protection device to on status is lowered, an overvoltage protection device sensitive to the overvoltage can be obtained. Therein, the preferred embodiments are described as follows.
Reference is made to fig. 4A, which is a top-view diagram of the first 1 1 embodiment of the overvoltage protection device in accordance with the present invention. The upper portion of the semiconductor substrate 30 is surrounded by a voltage-l,miting region 33a made of an N-type semiconductor. There is a gap located between the voltage-limiting region 33a and the base region 32 made of a P-type semiconductor. The emitter region 34 is disposed inside the base region 32. The multiple holes shown in the figure are emitter shorting dots 35. The emitter region 34 has a first electrode region 31 disposed thereon. In general, the first electrode region 31 is a metal layer used to connect with other components.
Reference is made to fig. 4B, which is a top-view diagram of the second embodiment of the overvoltage protection device in accordance with the present invention. The section line 40 shown in this figure corresponds to the cutaway view shown in fig. 3. The components of the present invention can be modified according to the practical requirements.
l5 ['herein, the upper portion of the semiconductor substrate 30 is surrounded by a semicircular voltage-limiting region 33b made of an Ntype semiconductor.
There is a gap located between the voltage-limiting region 33b and the base region 32 made of a P-type semiconductor. The emitter region 34 is disposed inside the base region 32 and has the multiple emitter shorting dots 35. The emitter region 34 has the first electrode region 31 disposed thereon.
Reference is made to fig. 4C, which is a top-viewidiagram of the third embodiment of the, overyolta,ge protection device in accordance with the present invention. The section line 40 shown in this figure corresponds to the cutaway view shown in fig. 3. The present invention can be modified according to the practical requirements.
Therein, the upper portion of the semiconductor substrate 30 is surrounded by a semicircular segmented voltage-limiting region 33c made of an N-type semiconductor. There is a gap located between the voltage- limiting region 33c and the base region 32 made of a P-type semiconductor. The emitter region 34 is disposed inside the base region 32 and has the multiple emitter shorting dots 35.
The emitter region 34 has the first electrode region 31 disposed thereon.
Talking fig. 4C as an example, using segmented voltage-limiting region not only can reduce the total length of this voltage-limiting region but also can equally distribute the breakdown phenomenon to a longer length around the device. Hence, it can lower the breakover current and increase the power dissipation capacity to increase the stability of the device.
Reference is made to fig. 5, which is a schematic diagram of a bidirectional overvoltage protection device in accordance with the present l5 invention. Therein, the two opposed sides of the substrate 50 both have a overvoltage protection device, including a first and second base regions 52a, 52b made of P-type semiconductors, a first and second voltage-limiting regions 53a, 53b disposed at the two sides, a first and second emitter regions 54a, 54b respectively disposed on the base regions, multiple first and second emitter shorting dots 55a, 55b formed inside the emitter regions, and a first and second electrode regions 51a, 51b disposed at the two surfaces of the device. The overvoltage protection device shown in fig. 3 is a uni- directional device, which only has uni-directional overvoltage protection functions. However, the bi-directional overvoltage protection device shown in fig. 5 can provide bi-directional protection functions for the communication systems operated under alternative voltages.
Reference is made to Figs. 6a-f, which illustrate a manufacturing process of one overvoltage protection device in accordance with the present invention. This s manufacturing process is used to produce a unidirectional protection device. As for the bi-directional or multidirectional devices, they can also be produced according to this process.
As shown in Fig. 6a, a first masking layer 61 is formed on a substrate 60 via oxidation or deposition process. The substrate 60 is mainly made of silicon (Si) and lo the first masking layer 61 can be made of SiO2 or other film-forming material (e.g. Si3N4).
As shown in Fig. 6b, via lithography and etching processes, the first masking layer 61 can be etched to form the masking regions 61a, 61b, 61c and multiple regions as shown in Fig. fib. Therein, the first region 601, which will become the Is voltage-limiting region, is defined between the masking regions 61a and 61b. The second region 602, which will become the base region, is defined between the masking regions 61b and 61c. The width of the masking region 61b is the spacing of the first region 601 (voltage-limiting region) and the second region 602 (base region) and used to determine the breakdown voltage value of this device.
As shown in Fig. 6c, a selected diffusion process or ion implantation process is used to diffuse or implant the impurity atoms into the second region 602 to form the base region 62 of the device, i.e. the P-type semiconductor region shown in the figure.
As shown in Fig. 6d, the selected diffusion process or ion implantation process is also used to diffuse or implant the impurity atoning into the first region 601 to form the voltage-limiting region 63 of the present embodiment.
As shown in fig. 6e, the selected diffusion process or ion implantation process is also used to diffuse or implant high-concentration impurity atoms into the base region 62 to form the high-concentration emitter regiori 64 and the emitter holes or shorting dots 65.
As shown in fig. 6f, finally, a metal layer is deposited on the emitter region 64 as an electrode region 66 for electric conduction. And the manufacturing process of the protection device is ended at this step.
Furthermore, in fig. be mentioned above, the step for fanning the emitter region can also be performed right after the base region is formed. The present invention is not limited to the manufacturing order described above. The steps described above can also be repeated or performed simultaneously on Me two sides of the substrate to manufacture a bidirectional or multi-directional overvoltage protectiondevice.
The described device utilises a voltage-limiting region parallel to the central junction of the overvoltage protection device. By varying the size and location of the voltage-limiting region, the breakdown voltage and breakover current can be set so as to produce an overvoltage protection device sensitive to the overvoltage phenomenon.
Although the present invention has been described with reference to the preferred embodiments thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to Hose of ordinary skill in the art. Therefore, all such substitutions and modifications are embraced within the scope of the invention as defined in the appended claims.
CLAIMS: 1. A method for manufacturing an overvoltage protection device, wherein a voltage-limiting region is peripherally disposed about a base region of the overvoltage protection device to control the breakdown voltage and breakover current of the device, the method comprising the steps of: forming a first masking layer on a substrate; etching the first masking layer to form a plurality of masking regions to define a first region and a second region; forming the voltage-limiting region in the first region; lo forming the base region in the second region; forming an emitter region on the base region; and forming an electrode region on the emitter region.
2. The method as claimed in claim 1, wherein the voltage-limiting region has a first impurity concentration larger than a second impurity concentration of the substrate.
3. The method as claimed in claim 1 or claim 2, wherein the voltagelimiting region and the base region produce a transverse breakdown phenomenon therebetween.
4. The method as claimed in any preceding claim, wherein the breakdown voltage is defined according to a spacing between the voltage-limiting region and the base region.
5. The method as claimed in any preceding claim, wherein the base region is completely or partially surrounded by the voltage-limiting region with a continuous shape or a segmented shape.
6. The method as claimed in any preceding claim, wherein the step for lo forming the base region, the voltage-limiting region or emitter region is performed via a diffusion process or an ion implantation process.
7. The method as claimed in any preceding claim, wherein the substrate, the voltage-limiting region or the emitter region is made of an N-type semiconductor and the base region is made of a P-type semiconductor.
8. The method as claimed in any of claims 1 to 6, wherein the voltagelimiting region or the emitter region is made of a P-type semiconductor and the base region is made of an N-type semiconductor.
9. The method as claimed in any preceding clam, wherein said steps are repeated to form a bi-directional or multi-directional overvoltage protection device. r / 16 /
10. An overvoltage protection device, comprising: a substrate; a base region disposed on the substrate; a plurality of emitter regions disposed on the base region; and a voltage-limiting region disposed adjacent a periphery of the base region.
11. The device as claimed in claim 10, wherein the substrate, the voltage limiting region or the emitter region is made of an N-type semiconductor and the lo base region is made of a P-type semiconductor.
12. The device as claimed in claim 10, wherein the voltage-limiting region or the emitter region is made of a P-type semiconductor and the base region is made of an N-type semiconductor.
13. The device as claimed in any of claims 10 to 12, wherein the voltage limiting region has a first impurity concentration larger than a second impurity concentration of the substrate.
so 14. | The device as claimed in any of claims 10 to 13, wherein the overvoltage protection device is a bi-directional or multi-directional overvoltage protection device. )
15. The device as claimed in any of claims 10 to 14, wherein the base region is completely or partially surrounded by the voltage-limiting region with a continuous shape or a segmented shape.
16. An overvoltage protection device having a voltage-limiting region peripherally disposed about a base region of the device and exhibiting a transverse junction breakdown.
17. An overvoltage protection device according to any of claims 10 to 16, lo wherein the conventional buried region beneath the base region is omitted.
18. An overvoltage protection device substantially as described hereinabove with reference to Figure 3 and any of Figures 4A to 4C or with reference to Figure 5 of the accompanying drawings.
19. A method of manufacturing an overvoltage protection device, the method being substantially as described hereinabove with reference to Figures 6A to OF of the accompanying drawings.
Claims (19)
- Amendments to the claims have been filed as followsACLAIMS: 1. A method for manufacturing an overvoltage protection device, wherein a voltage-limiting region is peripherally disposed about a base region of the overvoltage protection device to control the breakdown voltage and breakover current of the device, the method comprising the steps of: forming a first masking layer on a substrate; etching the first masking layer to form a plurality of masking regions to define a first region and a second region; forming the voltage-limiting region in the first region; JO forming the base region in the second region; forming an emitter region on the base region; and forming an electrode region on the emitter region.
- 2. The method as claimed in claim 1, wherein the voltage-limiting region has Is a first impurity concentration larger than a second impurity concentration of the substrate.
- 3. The method as claimed in claim 1 or claim 2, wherein the voltagelimiting region and the base region produce a transverse breakdown phenomenon ?0 therebetween. 1C-'
- 4. The method as claimed in any preceding claim, wherein the breakdown voltage is defined according to a spacing between the voltage-limiting region and the base region.
- 5. The method as claimed In any preceding claim, wherein the base region is completely or partially surrounded by the voltage-limiting region with a continuous shape or a segmented shape.
- 6. The method as claimed in any preceding claim, wherein the step for to Forming the base region, the voltage-limiting region or emitter region is performed via a diffusion process or an ion implantation process.
- 7. The method as claimed in any preceding claim, wherein the substrate, the voltage-limiting region or the emitter region is made of an N-type semiconductor is and the base region is made of a P-type semiconductor.
- 8. The method as claimed in any of claims 1 to 6, wherein the voltage!imiting region or the emitter region is made of a P-type semiconductor and the base region is made of an N-type semiconductor.
- 9. he method as claimed in any preceding clam, wherein said steps are repeated to form a bi-directional or multi-directional overvoltage protection device. Am
- 10. An overvoltage protection device, comprising: a substrate; a base region disposed on the substrate; a plurality of emitter regions disposed on the base region; and a voltage-limiting region disposed adjacent a periphery of the base region.
- 11. The device as claimed in claim 10, wherein the substrate, the voltagelimiting region or the emitter region is made of an N-type semiconductor and the to base region is made of a P-type semiconductor.
- 12. The device as claimed in claim 10, wherein the voltage-limiting region or . Ale, the emitter region is made of a P-type semiconductor and the base region is e made of an N-type semiconductor. q i 15
- 13. The device as claimed in any of claims 10 to 12, wherein the voltage He limiting region has a first impurity concentration larger than a second impurity concentration of the substrate.
- 14. The device as claimed in any of claims 10 to 13, wherein the overvoltage protection device is a bi-directional or multi-directional overvoltage protection device. [Eli
- 15. The device as claimed in any of claims 10 to 14, wherein the base region is completely or partially surrounded by the voltage-limiting region with a continuous shape or a segmented shape.
- 16. An overvoltage protection device having a voltage-limiting region peripherally disposed about a base region of the device and exhibiting a transverse junction breakdown.
- 17. An overvoltage protection device according to any of claims 10 to 16, JO wherein the conventional buried region beneath the base region is omitted.
- 18. An overvoltage protection device substantially as described hereinabove e.. with reference to Figure 3 and any of Figures 4A to 4C or with reference to e..e Figure 5 of the accompanying drawings. cc.
- 19. A method of manufacturing an overvoltage protection device, the method :..id, being substantially as described hereinabove with reference to Figures 6A to OF Of the accompanying drawings.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0409591A GB2413699B (en) | 2004-04-29 | 2004-04-29 | Overvoltage protection device and manufacturing process for the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB0409591A GB2413699B (en) | 2004-04-29 | 2004-04-29 | Overvoltage protection device and manufacturing process for the same |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB0409591D0 GB0409591D0 (en) | 2004-06-02 |
| GB2413699A true GB2413699A (en) | 2005-11-02 |
| GB2413699B GB2413699B (en) | 2006-02-15 |
Family
ID=32408255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB0409591A Expired - Fee Related GB2413699B (en) | 2004-04-29 | 2004-04-29 | Overvoltage protection device and manufacturing process for the same |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB2413699B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2960944A1 (en) * | 2006-10-03 | 2015-12-30 | Vishay General Semiconductor LLC | High breakdown voltage diode and method of forming same |
| CN111933686A (en) * | 2020-06-29 | 2020-11-13 | 株洲中车时代半导体有限公司 | Power semiconductor device and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4967256A (en) * | 1988-07-08 | 1990-10-30 | Texas Instruments Incorporated | Overvoltage protector |
| US5001537A (en) * | 1987-06-09 | 1991-03-19 | Texas Instruments Incorporated | Semiconductor device for electrical overstress protection |
| EP0657933A1 (en) * | 1993-12-13 | 1995-06-14 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Integrated structure active clamp for the protection of power semiconductor devices against overvoltages |
| US20030168682A1 (en) * | 2000-06-06 | 2003-09-11 | Stephan Mettler | Protection device against electrostatic discharges |
-
2004
- 2004-04-29 GB GB0409591A patent/GB2413699B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5001537A (en) * | 1987-06-09 | 1991-03-19 | Texas Instruments Incorporated | Semiconductor device for electrical overstress protection |
| US4967256A (en) * | 1988-07-08 | 1990-10-30 | Texas Instruments Incorporated | Overvoltage protector |
| EP0657933A1 (en) * | 1993-12-13 | 1995-06-14 | Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe | Integrated structure active clamp for the protection of power semiconductor devices against overvoltages |
| US20030168682A1 (en) * | 2000-06-06 | 2003-09-11 | Stephan Mettler | Protection device against electrostatic discharges |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2960944A1 (en) * | 2006-10-03 | 2015-12-30 | Vishay General Semiconductor LLC | High breakdown voltage diode and method of forming same |
| CN111933686A (en) * | 2020-06-29 | 2020-11-13 | 株洲中车时代半导体有限公司 | Power semiconductor device and manufacturing method thereof |
| CN111933686B (en) * | 2020-06-29 | 2022-06-24 | 株洲中车时代半导体有限公司 | Power semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2413699B (en) | 2006-02-15 |
| GB0409591D0 (en) | 2004-06-02 |
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| Date | Code | Title | Description |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20160429 |