GB2413444A

GB2413444A - Circuits for use in radio communications

Info

Publication number: GB2413444A
Application number: GB0408831A
Authority: GB
Inventors: Ariel Luzzatto; Haim Friedlander; Gadi Shirazi
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 2004-04-21
Filing date: 2004-04-21
Publication date: 2005-10-26
Anticipated expiration: 2024-04-21
Also published as: GB0408831D0; GB2413444B; WO2005107076B1; CA2562752A1; WO2005107076A1

Abstract

A frequency synthesiser circuit for use in wireless communications including a phase locked loop including a VCO (voltage controlled oscillator), wherein the synthesiser circuit includes a further oscillator which in operation is a free running oscillator at a frequency higher than the VCO and a mixer connected to receive input signals from the VCO and from the further oscillator and to combine such signals. Also described is a wireless communications transmitter or receiver incorporating the frequency synthesiser circuit.

Description

24 1 3444 TITLE: CIRCUITS FOR USE IN RADIO COMMUNICATIONS

Field of the Invention

This invention relates to circuits for use in wireless communications. In particular, it relates to frequency synthesizer circuits which incorporate a VCO (voltage controlled oscillator). Such circuits are useful in wireless transmitters and receivers for generating stable radio frequency signals.

Background of the Invention

Carrier frequency signals in RF (radio frequency) communications transmitters are conventionally generated by a frequency synthesiser circuit. Such a circuit usually includes a VCO connected in a phase locked loop (PLL). The loop, including the VCO, provides an appropriate stable output at a precisely defined frequency. The VCO usually employs one or more voltage controlled devices, e.g. a varactor (variable capacitance device), to provide tuning of the VCO to an output frequency related to an input control voltage.

Such a circuit may also be employed to generate a local osillator signal for use in a radio receiver. In many cases the transmitter and receiver are combined in a single transceiver unit.

Wireless communications systems are now being designed for use at high frequencies, e.g. greater than l GHz. For example, local area networks in accordance with the 802.lla standard are being designed to operate in available operating bands close to 5 GHz. With the use of such high frequencies, the design of suitable low-noise VCOs becomes more and more difficult, primarily due to the resistive loading caused by the voltage controlled device(s) on the VCO resonator.

This loading significantly reduces the resonator loaded Q-factor, with consequent increase of phase noise. This effect worsens as the frequency increases.

However even at relatively low frequency bands such as VHF (136-174 MHz), the loading produced by the voltage controlled device is the limiting factor for phase noise performance, which in turn is the limiting factor for selectivity and coexistence specifications. (Coexistence is the capability of receiving a signal from a given transmitter in the presence of other nearby transmitters).

For instance, at VHF, where the resonator unloaded Q-factor is of the order of 150-600, the transistor loading reduces the Q-factor value to about half its unloaded value, and the loading by the voltage controlled device further reduces the Q-factor value to about a quarter of the already reduced value. For instance if the unloaded Q-factor is 150, the loaded Q- factor will be around 15. Starting with an unloaded Q factor of 600, the loaded Q-factor is reduced to about 30. As the frequency increases, the reduction in Q- factor due to the voltage controlled device increases sharply.

In the prior art, known techniques involve

splitting the VCO into sub-bands using multi- resonator arrangements, thus obtaining the effect of reducing the loading of the voltage controlled device on the resonator. These techniques are however both limited in effect end require a substantial amount of additional hardware and also software arrangements to switch the resonators. Undesirably, such additional hardware adds to the size and complexity of the circuit and such additional hardware and software adds to the cost.

Summary of the Invention

According to the present invention in a first aspect there is provided for use in wireless communications a frequency synthesizer circuit including a phase locked loop including a VCO (voltage controlled oscillator), wherein the synthesiser circuit includes a further oscillator which in operation is a free running oscillator at a mean frequency higher than that of the VCO and a mixer connected to receive input signals from the VCO and from the further oscillator and to combine such signals.

The mixer provides an output signal at a frequency which is a combination of the frequencies of its respective inputs. The mixer produces a first frequency component having (i) a sum of the respective input frequencies; and (ii) a difference between the respective input frequencies. Either component may be selected as the desired frequency. The unwanted component may be removed by filtering.

Desirably, the output signal provided by the mixer is passed through a RF filter, which may be a band pass, low pass or high pass filter or a combination of two or more such filters, to filter out individual frequency components directly from the VCO and the further oscillator and the undesired components of their combination. Whilst meeting these criteria, the filter may have a frequency pass band which is greater than 10 per cent, e.g. 15 to 25 per cent, of the desired output frequency.

The mean frequency of the further oscillator may be much higher than that of the VCO. For example, the mean frequency of the further oscillator may be at least 1.5 times, preferably at least 3 times, that of the VCO. In fact the VCO frequency may be as low as possible, provided that it covers the required frequency band of the output and any drift in the output frequency of the further free running oscillator (typically a few per cent during the life of the oscillator). Thus, the mean frequency of the further oscillator may be typically ten times or more greater than that of the VCO.

The lower frequency VCO and the higher frequency further oscillator together provide a source of oscillations at their combined frequency (sum or difference as selected). The output signal from the mixer at this combined frequency, desirably passed through the RF filter, is an RF signal locked in phase by the phase locked loop. The phase locked loop may have, apart from the combined arrangement comprising the VCO, the further oscillator, the mixer and the RF filter, a known construction and operation.

Desirably, the further, free running oscillator includes a high Q-factor resonator, e.g. one having an unloaded Q-factor of at least 100, preferably at least 300, especially at least 500. Desirably, the Q-factor is reduced to not less than half of its unloaded value when loaded in the synthesizer circuit. Ceramic type resonators for use in this way are well known to those skilled in the art. An example of a suitable resonator is a coaxial resonator supplied by Temex of 29 Avenue de la Baltique, 91953 Les Ulis Cedex, France. Such a resonator, and an oscillator incorporating it, may contribute little to the phase noise of the circuit.

The present invention helps to solve or reduce the problem of loading and Q-factor reduction caused thereby as described earlier in the Background section. Since the higher frequency further oscillator is free running it contributes little to the circuit phase noise, since its load to the resonator is small as illustrated later.

The VCO still contributes to loading phase noise.

However, since it operates at a lower frequency, the VCO (together with the further free running oscillator which makes only a minor contribution to the phase noise) will exhibit a phase noise much better (lower level) than a VCO operating near to the desired output frequency and phase locked using the conventional approach of the

prior art.

Although the invention is of greatest potential benefit when used to synthesise frequencies greater than 1 GHz, e.g. in one or more bands from 4 GHz to 6 GHz as used in WLAN, it is applicable also to much lower frequency bands, e.g. providing very low- noise oscillators for professional high-tier radios, for instance for use in emergency services, public safety and military applications, where strong coexistence and selectivity specifications are required, which may give the possibility of an improved oscillator noise performance that cannot be obtained with conventional methods. The output frequency synthesized may for example be lOO KHz or higher for VHF applications or lMHz or higher for higher frequency applications.

Moreover, the invention can allow easy and straightforward extension of oscillators (in such applications over a range of frequencies) to multiband operation, while keeping substantially constant phase noise performance.

In the frequency synthesizer circuit according to the first aspect of the invention, the phase locked loop may include a frequency divider for dividing a frequency of an output of the mixer, preferably after passing through an RF filter, a phase detector for comparing the phase of an output of the frequency divider with a phase of a further divider receiving in operation an input from a reference oscillator, and a loop filter to filter an output voltage of the phase detector to produce a control voltage for supply to the VCO.

According to the present invention in a second aspect there is provided a transmitter and/or receiver for use in wireless communications which includes a frequency synthesizer according to the first aspect of the present invention. The transmitter may for example include a modulator which is operable to modulate an output signal provided by the frequency synthesizer, an RF amplifier to amplify an RF output signal of the modulator and an antenna to radiate an amplified output signal of the RF amplifier.

Embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which:

Brief description of the drawings

FIG. 1 is a schematic block circuit diagram of a conventional phase locked loop frequency synthesiser circuit.

FIG. 2 is a schematic block circuit diagram of a phase locked loop frequency synthesizer circuit embodying the present invention.

Description of embodiments of the invention

Reference is now made to FIG. 1, which is a schematic block circuit illustration of a conventional phase locked loop frequency synthesiser circuit, generally referenced as 100. The frequency synthesiser circuit 100 includes a reference oscillator 102, e.g. a crystal oscillator, a reference frequency divider 104, a controller 108, a phase detector 110, a loop filter 118, a VCO 120 and a feedback frequency divider 114. The VCO 120 includes as constituent parts a VCO tuning and resonating block 112 and a VCO active block 116.

The reference frequency divider 104 is connected to the reference oscillator 102, the controller 108 and the phase detector 110. The feedback frequency divider 114 is connected to the phase detector 110, the controller 108 and the VCO active block 116. The loop filter 118 is connected to the phase detector 110 and to the VCO tuning and resonating block 112. The VCO active block 116 is connected to the VCO tuning and resonating block 112 and to the feedback frequency divider 114. The loop including the VCO, the divider 114, the phase detector 110 and the loop filter 118 forms a phase locked loop 130.

IO The reference frequency divider 104 receives a signal, having a frequency FR, from the reference oscillator 102. The reference frequency divider 104 further divides the frequency of this signal by N and provides the resultant signal, having the frequency FR/N, to the phase detector 110. The feedback frequency divider 114 receives a feedback signal, having a frequency FOUT, as an output from the VCO active block 116. The feedback frequency divider 114 further divides the frequency of this signal by M and provides the resultant signal, having the frequency FOOT/M, to the phase detector 110. The phase detector compares these two signals, generates a respective output control signal and provides it to the loop filter 118. Typically, the loop filter 118 is a low pass filter. The loop filter 118 integrates the output control signal and provides a resultant output voltage VOUT to the VCO tuning and resonating block 112.

Depending on the value of VOUT, related to the ratio of M to N. the VCO tuning and resonating block 112 adjusts the output frequency FOUT SO that it is equal to a desired value. The controller 108 provides control of the values of M and N and thereby provides adjustment of the value of VOUT and FOUT.

As described earlier, the prior art circuit 100

shows the problem of resonator loading and Q-factor reduction in the VCO 120 especially at high frequencies.

Reference is now made to Figure 2, which is a schematic circuit diagram of a frequency synthesizer circuit 200 embodying the invention. Parts having the same reference numerals as in FIG. 1 operate in the same manner. In FIG.2, the voltage VOUT is applied to a correcting voltage controlled oscillator (CVCO) 201 the output from which is a RF signal which is applied as a first input to a mixer 203. A free running oscillator (FRO) 205 generates a further RF signal, of higher frequency than that from the CVCO 201, which is applied as a second input to the mixer 203. The mixer 203 combines the two input RF signals applied thereto and produces an output RF signal having components equivalent to (i) the sum; and (ii) the difference; of the respective frequencies of the two inputs. The output signal from the mixer 203 is fed to a RF filter 207 which may be a band pass filter which passes one of these components, e.g. the component which is the frequency sum, but not the other. The RF filter 207 also filters out RF components which are uncombined individual outputs of the CVCO 201 and the FRO 205.

The band pass filter 207 produces an output signal at a required frequency F' OUT.

N

Although the RF output signal of the CVCO 201 and that of the FRO 205 are constantly floating in frequency, the output RF frequency F' OUT iS locked and fixed. In fact, the CVCO 201 which is in a phase locked loop 230 (replacing the loop 130 of FIG.1) eliminates the frequency/phase flotation of the FRO 205.

The RF filter 207 may conveniently be such as to pass a wide band of the output signal from the mixer 203, e.g. 20 per cent or more of the frequency of the output of the mixer 203.

In a particular application, for use in WLAN applications where the desired output frequency is close to 5 GHz in a band having a bandwidth of 40 MHz, IS the FRO 205 may produce an output RF signal having a frequency of 4(1-e) GHz, where O < e < 0.01 MHz, and the CVCO 201 may produce an output signal having a frequency in the range of from 1 (1-e) + 0.02 GHz to 1 (l+e) + 0.02 GHz. The RF filter 203 may pass frequencies in the range 4.5 GHz to 5.5 GHz. The resultant output frequency F' OUT is in the range 4. 98 GHz to 5.02 GHz.

The frequency range of the output signal of frequency F' OUT (provided by the combination of the FRO 205 and CVCO 201 and the mixer 203 and band pass filter 207) may be changed simply by replacing the resonator of the FRO 205 and the RF filter 207.

Beneficially, the phase noise performance is mainly limited by the CVCO 201 and can be relatively low because the phase noise of the CVCO 201 can be \ relatively low. This phase noise can for example be 20 to 30 dB lower than if a high frequency VCO only is

used in the configuration of the prior art. 1)

Claims

1. A frequency synthesiser circuit for use in wireless communications including a phase locked loop including a VCO (voltage controlled oscillator), wherein the synthesiser circuit includes a further oscillator which in operation is a free running oscillator at a frequency higher than the VCO and a mixer connected to receive input signals from the VCO and from the further oscillator and to combine such signals.

2. A frequency synthesiser circuit according to claim l wherein in operation the mean frequency of the further oscillator is at least 1.5 times that of the VCO.

3. A frequency synthesiser circuit according to claim 2 wherein in operation the mean frequency of the further oscillator is at least 3 times that of the VCO.

4. A frequency synthesiser circuit according to claim 3 wherein in operation the mean frequency of the further oscillator is at least lO times that of the VCO.

5. A frequency synthesiser circuit according to claim l, claim 2 or claim 3 wherein in operation an output signal from the mixer is provided at a frequency which is a combined frequency of respective output signals from the VCO and the further oscillator and the combined frequency is locked in phase by the phase locked loop.

6. A frequency synthesiser circuit according to claim 4 wherein the combined frequency is at least lOO KHz.

7. A frequency synthesiser circuit according to claim wherein the combined frequency is at least 1 MHz.

8. A frequency synthesiser circuit according to claim 7 wherein the combined frequency is at least 1 GHz.

9. A frequency synthesiser circuit according to claim 8 wherein the combined frequency is from 4 GHz to 6 GHz.

10. A frequency synthesiser circuit according to claim 9 wherein the further oscillator is operable to produce an output signal having a mean frequency of 4(1-e) GHz, JO where O < e < 0.01 MHz, and the VCO is operable to produce an output signal having a mean frequency in the range of from 1 (1-e) + 0.02 GHz to 1 (l+e) + 0.02 GHz.

11. A frequency synthesiser circuit according to any one of the preceding claims wherein the mixer is connected to an RF filter to filter an output signal provided by the mixer.

12. A frequency synthesiser circuit according to claim 11 wherein the band pass filter has a frequency pass band which is greater than 10 per cent of the desired output frequency of the synthesiser circuit.

13. A frequency synthesiser circuit according to claim 12 wherein the RF filter has a frequency pass band which has a frequency width of from 15 per cent to 25 per cent of the desired output frequency of the synthesiser circuit.

14. A frequency synthesiser circuit according to any one of the preceding claims wherein the further oscillator is operable to have an unloaded Qfactor of at least 100.

15. A frequency synthesiser circuit according to claim 14 wherein the further oscillator is operable to have a i; loaded Q-factor of not less half that of its unloaded Q- factor.

16. A frequency synthesizer circuit according to any one of the preceding claims wherein the phase locked loop includes a first frequency divider for dividing a frequency of an output of the mixer, a second phase detector for comparing the phase of an output of the frequency divider with a phase of a further divider receiving in operation an input from a reference lO oscillator,and a loop filter to filter an output voltage of the phase detector to produce a control voltage for supply to the VCO.

17. A synthesizer circuit according to claim 16 including an RF filter for filtering an output signal IS produced by the mixer and wherein the first frequency divider is operable to divide the frequency of an output signal provided by the RF filter.

18. A synthesizer circuit according to claim 1 and substantially as herein described with reference to FIG. 2 of the accompanying drawings.

19. A wireless communications transmitter or receiver including a frequency synthesizer circuit according to any one of the preceding claims.