GB2395383A

GB2395383A - Vector Dot Product Multipliers and Digital to Analogue Converters

Info

Publication number: GB2395383A
Application number: GB0225846A
Authority: GB
Inventors: Calvin Sim; Christofer Toumazou
Original assignee: Toumaz Technology Ltd
Current assignee: Toumaz Technology Ltd
Priority date: 2002-11-06
Filing date: 2002-11-06
Publication date: 2004-05-19
Anticipated expiration: 2022-11-06
Also published as: GB0225846D0; GB0509235D0; WO2004042931A3; AU2003285493A1; DE10393686T5; CN1736029A; GB2409941B; WO2004042931A2; JP2006505984A; GB2395383B; GB2409941A; AU2003285493A8

Abstract

Apparatus for converting an M-bit digital signal into an analogue signal. The apparatus comprising means 12,13 for mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or approximates the value of the M-bit digital signal. First and second digital to analogue converters 14,15 are provided, the first digital to analogue converter 14 having an input for receiving said first digital value and the second digital to analogue converter 15 having an input for receiving said second digital value. Circuit means 16 is coupled to the analogue outputs of the digital to analogue converters 14,15 for dividing one of the analogue outputs by the other, and for providing the result to an output. Further claimed is a vector dot product multiplier that has a plurality of multiplication elements, each having 2 inputs and an output. Also, a control device generates a digital weight for the multiplication elements, which outputs their valves to an output means the selectively couples inputs/outputs together. The control means also provides a signal to the output means for effecting the selective coupling.

Description

Vector Dot Product Multipliers and Digital to Analogue Converters The

present invention relates to vector dot product multipliers and to digital to analogue converters. The digital to analogue converters of the present 5 invention are applicable in particular, though not necessarily, for use in vector dot product multipliers.

Vector dot product multiplication is a fundamental operation in discretetime signal processing, and is stated mathematically as: K 1 0 y = WkXk ( 1) k=l where wk and xk are the kth element of the weights and input vector respectively, y is the output and K is the size of the input vector.

By allowing for a discrete time dimension, denoted by the subscript n in the 15 output and the weight, equation (1) may be restated for vector matrix multiplication (VMM) operations: K In Wk,nXk (2) k=} where the output vector Yn is obtained sequentially in time according to the periodic change in weight Wk,n. Together, vector dot product and VMM are at 20 the core of numerous applications, such as those performing finite impulse response filters, discrete Fourier transforms and the discrete cosine transforms. When referring to system implementations of vector dot product and VMM 25 operations, the following properties may be relevant: Programmability - refers to the ability to change at run-time the coefficients of the individual weight elements so as to change the functionality of the device.

Scalability 30 a) of precision - refers to the ability to change at runtime the SNR characteristic of the system;

b) of complexity - refers to the ability to change at run-time the size of the operation Reconfigurability - refers to the ability to change at run-time the number of operations that are carried out in parallel in a given network, and 5 hence reconfigurability embodies and extends the definition of scalability of complexity.

In purely digital systems, digital signal processors (DSPs) are typically used to implement vector dot product and VMM operations. However, such 10 implementations are often power hungry and inefficient due to the large number of multiplications involved. With a DSP, a multiply operation is performed bit-wise, and is multi-staged, requiring clock frequencies that are several times higher than the signal frequency.

15 Vector dot product and VMM operations are not limited to the digital domain and examples of analogue and mixed-signal vector dot product and VMM cells exist. Such operations are described for example in: [1] R. Genov and G. Cauwenberghs, "Charge-Mode Parallel Architecture for Vector Matrix Multiplication," Circuits and Systems Il: 20 Analog and Digital Signal Processing, IEEE Transactions on, vol. 48, pp. 930-936, 2001; [2] V. A. Pedroni, "Error-compensated analog cells for vector multiplication and vector quantization," Circuits and Systems Il: Analog and Digital Signal [3] Processing, IEEE Transactions on, vol. 48, pp. 25 511-519, 2001; and [3] T. Y. Lin and A. J. Payne, "Programmable analogue vectormatrix multiplier," Electronic Letters, vol. 38 pp. 1-2, 2002.

In the implementation described in [1], while the charge-mode multiply operation is performed in the analogue domain, the digital representation is 30 embedded within the architecture, where inputs are presented in bitserial fashion and matrix elements are stored locally in bit-parallel form. In this approach, the multiplication is performed through a series of Boolean AND operations implicit in the charge transfer operation. A more 'analogue'

approach is undertaken in [2], where the inputs, weights and outputs are represented by continuous analogue variables, and multiplication is achieved by exploiting the square-law characteristic of MOS transistors in saturation.

[3] takes a different approach, where the inputs and weights modulate the 5 phases of the inputs and weights current respectively. A translinear multiplier coupled with low-pass filtering is used to obtain the output.

In these prior art 'analogue' approaches, the topology of the systems are fixed

at design-time and the systems lack the reconfigurability referred to above.

10 For such approaches, programmability (i.e. definition of an array of discretely weighted coefficients) may be obtained by the integer scaling of a modulating parameter, such as the area of a capacitor or resistor, and the coefficient is given by the ratio of that parameter value to the unit value.

15 In general, digital approaches are superior to analogue approaches in terms of noise and precision. The two performance metrics are interrelated as the precision of the system dictates the upper-bounds of the signal-to-noise ratio for a given dynamic range. In digital approaches, the precision of the system is determined by the "width" of the bus. In analogue approaches where the 20 weights are programmed digitally, the precision of the system may be limited by noise and errors, such as those due to matching.

As already noted, a component of a vector matrix multiplier operating in the mixed analogue-digital signal domain is likely to be a digital to analogue 25 converter (DAC). DACs play a fundamental and necessary role in bridging the divide between the quantised data manipulated in digital space and the continuous signals that the real world interacts with. However, for mobile and portable devices necessitating low power consumption and small chip area, DACs consume a substantial part of the power budget. As the precision 30 required by an application increases, physical problems such as matching, power supply sensitivity and other issues become more critical, placing a lower limit on the minimum quantisation step size. Constraints on chip area and power consumption then place an upper limit on the resolution (i.e.

number of input bits) of the device. Hence, for a given minimum quantisation step, a lower resolution DAC consumes less power since it has a correspondingly lower full scale swing.

5 A precise, low power, programmable and reconfigurable method of performing VMM for signal processing and computation is needed to meet the growing demand for autonomous, body-worn, lifestyle and sensor interface products.

In any such method, optimization of DAC performance is likely to be key.

10 According to a first aspect of the present invention there is provided apparatus for converting an M-bit digital signal into an analogue signal, the apparatus comprising: means for mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or 15 approximates the value of the Mbit digital signal; first and second digital to analogue converters, the first digital to analogue converter having an input for receiving said first digital value and the second digital to analogue converter having an input for receiving said second digital value; and 20 circuit means coupled to the analogue outputs of the digital to analogue converters for dividing one of the analogue outputs by the other, and for providing the result to an output.

The bit length of the first and second digital values is less than that of the M 25 bit digital signal. Preferably, the bit length N of the first digital value is the same as that of the second digital value, although this need not be the case.

The bit precision which can be achieved by combining two linear digital to analogue converters according to the present invention is greater than that 30 which can be achieved by using one of these converters alone. Furthermore, the power consumed by the two linear (N-bit) converters is generally less than that which would be consumed by a single digital to analogue converter having (2N-1) bits. Another advantage of embodiments of the present

invention is that the quantisation steps are smaller for small signal levels than they are for high signal levels. Signal to (quantisation) noise ratios are therefore improved for small signal levels.

5 Preferably, said means for mapping comprises a memory storing a look-up table, the look-up table containing fractional values and respective first and second value pairs, such that the ratio of a first and second value is equal to the corresponding fractional value. The means for mapping further comprises means for looking-up the table to find the closest fractional approximation to 10 the M-bit digital signal, and for identifying the corresponding first and second values. In certain embodiments of the invention, the apparatus comprises means for compressing said M-bit digital signal by some factor A. The compressed M- bit 15 digital signal is passed to the means for mapping. Said circuit means comprises means for scaling the result of said division by the factor A. As the signal to noise ratio is higher for small signal levels, the signal to noise ratio across the whole dynamic range is improved.

20 Preferably, said circuit means is a translinear multiplier.

According to a second aspect of the present invention there is provided a method of converting an M-bit digital signal into an analogue signal, the method comprising: 25 mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or approximates the value of the M-bit digital signal; applying said first and second digital values to inputs of the first and second digital to analogue converters respectively; and 30 dividing the analogue output of one of the digital to analogue converters by the other, and providing the result to an output.

According to a third aspect of the present invention there is provided a vector dot product multiplier comprising: a plurality of multiplication elements, each element having a first input for receiving an analogue input signal, a second input, and an output; 5 control means for generating a digital weight for one or more of said multiplication elements, and having output means for applying generated digital weights to the second inputs of respective multiplication elements; output means having a plurality of inputs coupled to outputs of respective multiplication elements to receive multiplication products therefrom, 10 a plurality of outputs selectively coupled to respective inputs, and means for selectively coupling inputs or outputs together, the control means being coupled to the output means for effecting the selective coupling.

Embodiments of the present invention provide a vector dot product multiplier 15 which can be reconfigured both in terms of the weights applied to the multiplication elements and in terms of the combination of elements used to perform a given multiplication operation. For example, by appropriately selecting the connections formed in the output means, the multiplier may be configured to perform two or more multiplication operations in parallel, each 20 operation using a subset of the plurality of multiplication elements.

Preferably, said control means is a microprocessor or microcontroller capable of periodically reprogramming one or more said digital weights.

25 Preferably, each multiplication element comprises a digital to analogue converter (DAC) having its digital input coupled to the second input of the element so as to receive a digital weight from the control means. More preferably, the DAC receives at a control input thereof said analogue input signal, the output of the DAC being coupled to the output of the multiplication 30 element to provide at the output the multiplication product.

Preferably, the output means comprises a first plurality of switches for selectively coupling neighbouring inputs of the output means together, and a

second plurality of switches coupling inputs of the output means to respective outputs. For a better understanding of the present invention and in order to show how 5 the same may be carried into effect reference will now be made, by way of example, to the accompanying drawings, in which: Figure 1 illustrates schematically a vector matrix multiplier; Figure 2 illustrates a multiplier cell of the multiplier of Figure 1; Figure 3 illustrates a reconfiguration bridge of the vector matrix multiplier of 10 Figure 1; Figure 4 illustrates in more detail the reconfiguration bridge of Figure 3; Figure 5 illustrates schematically, a simplified digital to analogue conversion system; Figure 6 illustrates in more detail the system of Figure 5; 15 Figure 7 illustrates an alternative digital to analogue conversion system; Figure 8 illustrates another alternative digital to analogue conversion system; Figure 9 shows the possible quanta for digital to analogue conversion system having a base precision of 4-bits; Figure 10 is a set of plots comparing the performance of the system of Figure 20 5 with that of a conventional linear digital to analogue converter; and Figure 11 illustrates a multiplying digital to analogue conversion system obviating the need for a separate multiplier; and Figure 12 is a set of plots comparing the performance of the system of Figure 10 with that of a conventional linear digital to analogue converter.

The vector dot product and VMM system which will now be described comprises an array of analogue input ports that feed an array of multiplier cells that are configurable by a microprocessor. The outputs of the multiplier cells are applied to inputs of a reconfiguration bridge (R-BRIDGE) which is 30 also configurable by the microprocessor. It will be appreciated that whilst the system may be implemented using discrete components or may be integrated into a chip operating as a standalone component, the preferred implementation is within an integrated system designed to perform some

predefined or programmable function(s) making use of vector dot product or vector matrix multiplication.

Referring to Figure 1, a VMM system is illustrated which comprises an array of 5 analogue input ports 1 which feed a one-dimensional array of "analogue" multiplier cells 2 with respective analogue signals Xk. Digital weights wk are applied to weighting inputs 3 of respective multiplier cells 2 by a microprocessor 4. Each cell 2 comprises a digital to analogue converter (DAC) coupled to the cell input 3. The DAC may be a conventional, linear 10 current-output DAC such as a current-steering DAC, or a "rational" DAC such as is described in detail below.

The multiplication functionality of the cells 3 may be implemented by any circuit means which produces an output which is proportional to the 15 multiplication of its two input signals. One example of such an analogue multiplier is the current-mode translinear multiplier formed by transistors M1 to M4 shown in Figure 2. The output current signal (OUT) is proportional to the multiplication of the current signals applied at the IN and WEIGHT (following digital to analogue conversion) terminals.

In an alternative embodiment, the multiplier cell 3 may be a conventional, linear multiplying DAC with reprogrammable weights that are digitally programmed by the microprocessor having a precision and an analogue input signal that scales the output. In another alternative embodiment, a 'rational' 25 multiplying DAC implements both the digital to analogue converter as well as the multiplier cell 3. The M-bit digital inputs of the rational DAC are mapped to two N-bit digital values that comprise the numerator and denominator of the fraction that approximates most closely the digital signal. The two fractional parts are applied to the inputs of two linear conventional N-bit DACs and a 30 multiplier circuit provides the division of the outputs, as well as any required scaling of the analogue input signal, thereby performing both multiplication and division simultaneously. In both alternative embodiments, multiplication is performed by the DAC circuit, obviating the need for a separate multiplier

circuit. The precision of the conversion of the M-bit digital weight is proportional to the magnitude of the weights, and its precision may be scaled by first compressing the digital signal at the input to the rational DAC by a compression factor and scaling the analogue input signal by an equivalent 5 scaling factor. This tuning of precision may be performed dynamically. With appropriate tuning of the compression and scaling factors, a precision that is greater than that achieved by a linear conventional DAC of (2N-1) bit precision is achieved. Such a means for variable precision digital to analogue conversion is known as a rational DAC scheme, and is described in more 10 detail below.

With reference again to Figure 1, the outputs of the multiplier cells 3 are applied to respective inputs 5 of a reconfiguration bridge (R-BRIDGE) 6. The R-BRIDGE 6 is illustrated in more detail in Figure 3 (Figure 4 illustrates the R 15 BRIDGE in still more detail), and consists of a network of switches controlled by the microprocessor 4. A first set of SELECT switches 7 selectively couple the inputs of the it-Bridge 6 to respective outputs 8 of the R-BRIDGE, whilst a second set of SUM switches 9 selectively couple neighbouring inputs/outputs of the R-BRIDGE together. If the sets of SELECT and SUM switches is 20 enumerated within their respective sets, then the state of a SELECT switch is the inverse of the state of the correspondingly indexed SUM switch (i.e. when SELECTk is high, SUMk is low). The switch network may be controlled by a single reconfiguration vector, r(t), in a manner such that the state of a 'sum' switch is the inverse of the 'select' switch.

The functionality of the array of multiplier cells 3 may be described mathematically as an element-by-element multiplication of two vectors having the same dimensions, which is otherwise known as a Haddamard multiply (denoted by "a"). The R-BRIDGE 6 then operates on the Haddamard product 30 to give n dot product outputs, Y'...n. Vector matrix multiplication results are obtained from sequential outputs in time. Mathematically, ye) = (X() o We)) 5() =[xl().wl() x2().w2()... xn().wn() ] (3) = [ Yet Y2 An]

where X(t)=[Xl(t) X2(t)... X,(t)]t (4) w(t)=[wl(t) w2(t)... wn(t)] (5) and x'..n(t) and w..n(t) are the n inputs and weights respectively, such that the length of xn is equal to the length of wn and the sum of the lengths of the n 5 input (weights) vectors is equal to the lengths of x(t) (w(t)). If the bit stream to programme the reconfiguration bridge is a vector of bits, r(t), r(t)=[rl(t) r2(t) rN,(t) t] (6) then the reconfiguration matrix s(0 is given by 511 51n s(t)=,,, (7) _SNI SNn_ i-l 10 where,s'=,ZrI! += j,whererO =0 j = 1 N, and j = 1 n O, otherwise (8) In (3), the reconfiguration matrix, s(t), serves to isolate different groups of the Haddamard product, as well as to cumulate the outputs within the group, 15 affording the system a high degree of flexibility and reconfigurability. The reconfiguration bridge implements the necessary mapping of r(t) to s(t) in (3) and (7).

By operating appropriate switches using a single reconfiguration vector, r(t), 20 of bits, which is a single digital word, it is possible to connect together the outputs of all or a subset of the multiplier cells, and to couple the resulting sum of products (Kirchhoff's current law) to a selected output. In (3), the reconfiguration matrix, s(t), serves to isolate different groups of the Haddamard product, as well as to cumulate the outputs within the group, 25 affording the system with a high degree of flexibility and reconfigurability. The reconfiguration bridge implements the necessary mapping of r(t) to s(t) in (3) and (7).

Thus for example, the outputs of the top three multiplier cells 3 in the 30 arrangement of Figure 3 could be coupled together, and the result output on

the upper output of the R-BRIDGE 6. In addition, the outputs of the lower three multiplier cells 3 could be coupled together, and the result output on the lower output of the R-BRIDGE 6. The two sum of product operations are isolated and performed in parallel.

s As an example, a 6-dimensional network may be configured to implement a 2X2, a 3x3 VMM and a scalar product, where r(t) = (010011)b. On the other hand, if r(t) = (000001)b, then a 6X6 VMM operation is implemented.

10 In very many applications requiring vector dot product or VMM, power consumption is a critical factor. This is especially so in the case of portable devices. Digital to analogue converters have traditionally contributed significantly to the power consumption of vector dot product or VMM operations. Figure 5 illustrates schematically a digital to analogue conversion system suitable for use in a multiplier cell 3 of the VMM of Figure 1. The system is referred to here as a "rational" DAC and comprises an input 11 for receiving an M-bit digital input signal. This digital input signal would be a weight wk 20 generated by the microcontroller 4. The input signal is applied to a mapping function G(wk) 12 which uses a look-up table 13 to determine the closest approximation of the value of the digital signal to one of a number of fractions stored within the look-up table. The mapping function then identifies an N-bit numerator and an N-bit denominator which results in the determined fraction.

25 In practice, it is likely that the mapping function G(wk) will be implemented using a software routine executed by the microprocessor 4, and will not form a physical part of the multiplier cell 3.

The system further comprises two (conventional, linear) N-bit DACs 14,15, to 30 the respective inputs of which are applied the identified N-bit numerator and denominator. The converted analogue outputs appear at analogue outputs of the DACs, and are applied to inputs of a translinear multiplier 16. The translinear multiplier 16 is illustrated in more detail in Figure 6 and comprises

four weakly inverted MOS or bipolar junction transistors M1 to M4 having exponential l-V characteristics. The transistors exploit the translinear principle to provide one quadrant multiplication. The multiplier 16 provides at an output a signal Q(.) which is proportional to the ratio of the analogue outputs of the 5 DACs 14,15. A further input of the multiplier 16 receives a control input comprising a current signal /B which is applied to scale the output signal.

Considering in more detail the translinear multiplier 16, the product of the left hand currents is equal to the product of the right-hand currents, if the 10 transistors are BJTs or MOSFETs operated in the subthreshold region, and exhibit an exponential characteristic. Hence, the output current of the system having an input x may be expressed as: JOr'T = QR(Wk) = (Q ()) IB (9) where /B IS a bias or scaling current and /(.) and /2() are the currents due to 15 the uniformly quantised current DACs, Qua) and Qu2(.) respectively. The mapping function G(.), which is implemented within the DSP, chooses Qu'(.) and Qu2(.) by finding the closest match in the lookup table.

Two alternative rational DAC current- and voltage-mode implementations are 20 shown in Figures 7 and 8. In all implementations, two low resolution standard linear DACs are employed to provide the necessary ratios.

The operation of the system of Figure 5 is best illustrated by way of example.

Assume that M equals 4, and that the mapping function is capable of 25 generating a numerator u and a denominator v each of 2-bits. Each of these components can have four possible values, i.e. 00, 01, 10, and 11, meaning that u/v has eleven possible values, 1/4, 1/3, 1/2, 213, 314, 1, 413, 11/2, 2, 3, and 4. These values are illustrated in Table 1 below. The two DAC system therefore results in a greater number of quantisation states than would be 30 achieved by a single 3-bit linear DAC (having eight possible states), receiving a 3-bit weight wkfrom the microprocessor 4.

The quantisation states in the rational DAC scheme proposed here are proportional to the ratios of the quantisation states of two similar linearly quantised DACs, or mathematically: Bloc Qu2 (10) Qu, 5 where QR are the possible quantisation steps of a rational scheme and QU] and QU2 are those of a uniformly quantised system. QU] and QU2 have the same precision, which shall be defined as the "base precision" of QR. With this scheme, two N-bit DACs may be tuned in tandem to obtain more than (2N-1) quantisation states. A look-up table of the numerator, denominator and 10 the corresponding ratios may be used to match the input to the pair of integer values, which would give the closest approximation. The number of unique quanta, and hence, the size of the look up table for rational DACs having a base precision up to 8-bits is tabulated in Table 2 below.

15 The quantisation steps produced by a rational DAC scheme are not uniformly sized but rather increase with signal magnitude. For example, Figure 9 shows the possible quanta of a rational DAC with a base precision of 4-bits. As the quantisation step is large for small inputs and small for large inputs, the output from a rational DAC suffers substantially less distortion at low input signal 20 values as compared to a purely uniform DAC.

The rational DAC scheme offers the possibility of lower power by reducing full scale currents. The power, Pu, of an N-bit current steering DACis: Nl PU(N) = VPPI I,2 + (11)

= 2'q VP,,I,, = V,PI,,OC 25 where VPP jS the potential difference across the supplies, flu is the current at the minimum step size and /max is the full scale current, given as ImaX = 2NIU. It can be seen that for a given /max, the power consumption is independent of precision, or alternatively that for a given lu, ImaX and Pu are dependent on the precision. Since the rational DAC achieves a higher resolution through low 30 precision uniform DACs, it has the possibility of lower power consumption,

while still meeting the physical constraints placed on device sizing, power supply rejection ratio and other parameters.

The performance of a rational DAC has been compared to that of a uniform 5 DAC using MATLAB_. The figures of merit are relative power consumption and percentage distortion error at each quantum.

Power consumption The input power, PR, of the rational DAC in Figure 6 is 10 PR(Wk)=2Pu(N)+7pp(QR(wk)+l) (12) where Pu (N) is the input power of an N-bit uniform DAC. A comparison was made between an 8-bit uniform DAC having 256 quantisation levels and a rational DAC with base precision of 4-bits having 159 quantisation levels. The input wk is a uniformly monotonic vector with 104 elements to approximate a 15 continuous signal increasing linearly from 0 to 1. The increasing size of the quantisation steps used with a rational DACis clearly shown in Figure 10a, which shows the plots of normalised power consumption for both schemes at all quantisation levels. For ease of comparison, the probability of each quantisation step is assumed to be equal and the mean power consumption is 20 indicated by dotted lines for both the uniform and rational DAC schemes, as shown in Figure 10b. As expected, the mean power consumption of the rational DACis significantly less than that of the uniform DAC. On average, an ideal uniform DAC consumed 6 times the power required for a rational DAC. Percentage distortion error The percentage distortion error Ed at a given quantisation level is defined as the ratio of the difference between the quantised and actual value, to the actual value as a percentage, or mathematically: 30 = wk-Q(Wk) Bloom (13) wk For a uniform DAC, the error is attenuating in an inverse manner, as the error remains within a constant band for increasing Wk. The error for the rational scheme is more complex, comprising increasingly wide bands that are

attenuating, due to increasing numerator values, within the bands. This is illustrated in Figure 10c. The initial error at the start of each band increases with x due to decreasing denominator values. The bands overlap for small Wk. but become more distinct as wk increases. Consequently, the output of 5 the rational DAC was significantly less distorted for small values of wk than that of a linear DAC. However, this was true for less than 24% of the time; for large values of Wk. the distortion due to the rational DAC was much worse than that due to the uniform DAC. 10 The poor performance of the rational DAC for large values of wk may be

attributed to the skewed distribution of quanta, which is bottom heavy and sparse at the top. For a 4-bit rational DAC, only 8 quanta account for values of wk from 0.5 to 1, leaving 151 steps for smaller values. By discarding the larger quanta at the top, the overall precision of the rational DAC system may 15 be increased.

Scalable precision rational DACs Although the performance of the rational scheme is deficient to that of a linear scheme (having the same total input bit precision), its power consumption is 20 significantly less. By trading power consumption for bit precision, the SNR of the rational DAC may be improved. This can be achieved by compressing Wk by a scale factor A so as to "ignore" the quanta at the upper end of the dynamic range. Consequently, the reduced signal is quantised by the finer quanta at the lower end of the quantisation "ladder" to obtain an increase in 25 precision. To obtain the same full scale analogue output signal, the bias current needs to be increased by an equivalent factor of A. Power consumption increases proportionally to SNR. The output current, QR(-), of the system having an input, Wk. may be expressed as IOUT = AQR(Wk) = ( ()) A/B (14).

30 Consequently, if A is tuned at run-time, a feasible scheme for scaling the effective precision of the DAC may be achieved, enabling better power management of a device.

The architecture in Figure 6 is modified as shown in Figure 11 to implement the function of scaling precision. The input to the block G(.) is reduced by A within the DSP, while /BIS increased by an equivalent factor. Thus, the 5 expression for the power of a scalable rational DACIS then PR(Wk) = PUl(Wk) + PU2(Wk) + A(IB + OR (Wk))7pp À (15) The performance of a scalable precision rational DAC with base precision of 5bits was compared MATLAB_ to that of a uniform DAC with precision from 10 5 to 8 bits at different scale factors. As with the above analysis, two figures of merit are tabulated and compared: relative power in percent and relative percentage distortion error. Relative power in percent is calculated as: Rel. Power (o/O) = mean(rational power) TO (1 6) mean(uniform power) Relative percentage distortion error (PDE)IS the relative measure of the 15 percentage distortion error between rational and uniform DAC, and is calculated as the sum of elements that are described by the greater than, less than or equal operators. For example, (PDER,pDEu)(O/O)= C unt f(úd>eU) (17) no. of mput elements 20 The simulation results bear out the analysis that higher precision may be obtained by compressing the inputs such that the signal is quantised within a smaller but denser range and then expanding it to obtain the same full scale range, at the cost of increasing power consumption. However, due to the possibility of a smaller full scale range, the power consumption levels are still 25 significantly less than that which is required for a uniform DAC. For example, the results shown in Table 3 below and plotted in Figure 12 show that at 35% of the input power of an 8-bit uniform DAC, the rational DAC scaled at A=10 had a lower percentage distortion error than the uniform DAC for 46.8% of the time and had similar errors for 17.8% of the time.

In general, the effective precision of the quantisation (PDER < PDEU) increases with A. This is matched by a comparable increase in power

consumption. Hence, it may be observed that A has a direct effect on both the precision and power consumption of the DAC. By designing the system so that A is readily tuneable, a rational DAC capable of scaling precision at run-time may be implemented. it may be noted that certain values of A result 5 in sub-optimal performance, in which a uniform DAC outperforms a rational DAC either in terms of precision of power consumption, or both. Such configurations are denoted with an asterisk "*" in Table 3.

The cost of added software or digital complexity in requiring a look-up table 10 and processing for matching the input to the appropriate index in the LUT has not been addressed in the preceding discussion. While this cost is not insignificant when taken alone, within the context of a mixedsignal processing environment whereby an intimate mix of digital and analogue computation exists, requiring numerous low-power, local DACs of reasonable performance, 15 the cost of digital complexity may be shared by all the DACs. Thus, with a large number of local DACs, the cost of this added digital complexity becomes very low. This is true in the VMM described above.

Rational DACs implement a non-linear quantisation scheme, and it is 20 appropriate to compare it with a logarithmic scheme with quantisation steps, QOG(.) given as: Q (W) = rbo2 +b2 +...+bN_,2 (18) If k = bo2 + b, 2' +... + bN,2N-, then the maximum distortion error occurs midway between two adjacent quantisation steps, and is given as 25 Ed =,'+' ' 1+r (19) It is clear that the maximum distortion error is independent of k and hence, is constant for all input values (it may also be noted that maximum distortion error is independent of the number of bits used). Thus, with such a scheme, the technique of companding as described above may not be used to 30 effectively scale the SNR of the DAC.

To improve SNR performance, r must be set closer to unity, imposing stricter limits during fabrication. An increase in r is matched by a corresponding

reduction in the dynamic range, L, of the DAC, since s=r-2'. Therefore, to improve SNR without loss of dynamic range, stricter constraints on r as well as a need for more bits are required. In contrast, the SNR of the proposed rational DAC scheme may be readily tuned at run-time. Furthermore, the 5 rational DAC has a wide dynamic range, OUR, which is defined as the largest to the smallest number represented, and is given as SR=2N/-N=22NfOr a rational DAC with base precision of N-bits.

Word Value Ratio 0000 0 OFF

0001 1/16 00/1 1

0010 1/8 00/01, 01/1 1

0011 3/16 10/11

0100 1/4 00/00, 01 /01, 10/10,

11/11 0101 5/16 11/10

0110 3/8 10/01

011 1 7/16 10/01

1000 1/2 01/00,1 1/01

1 001 9/16 01 /00,1 1/01

1010 5/8 01/00, 1 1/01

1011 11/16 10/00

1 100 12/16 10/00

1101 13/16 10/00

1110 7/8 11/00

1111 15/16 11/00

Table 1

Base No. of Equivalent precision of quanta no. of quanta QR(.) in bits 1 3 >1

2 11 >3

3 43 >5

4 159 >7

5 647 >9

6 2,519 >11

7 10,043 >13

8 39,895 >15

Table 2

- Precision, Scale, Relative PDER PDER PDER N A power < = > PDEu PDEU PDEU 5 1 * 245.5 35.7 64.3 O

6 1 * 124.6 24.4 50.6 25.0

7 1 62.8 19.1 32.6 48.4

2 63.6 30.0 27.2 42.8

3 64.3 32.6 35.7 31.7

4 65.1 44.6 22.1 33.3

5 65.9 45.8 27.8 26.4

1* 31.5 15.0 19.9 65.1

2* 31.9 23.4 17.4 59.2

3* 32.3 25.4 24.5 50.1

4* 32.7 34.2 15.5 50.4

5 33.1 34.7 21.4 43.9

6 33.5 37.7 20.7 41.7

7 33.9 41.4 18.9 39.7

8 34.2 46.0 12.7 41.3

9 34.6 43.0 21.9 35.1

10 35.0 46.8 17.8 35.5

Table 3

Claims

1. Apparatus for converting an M-bit digital signal into an analogue signal, 5 the apparatus comprising: means for mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or approximates the value of the M-bit digital signal; first and second digital to analogue converters, the first digital to 10 analogue converter having an input for receiving said first digital value and the second digital to analogue converter having an input for receiving said second digital value; and circuit means coupled to the analogue outputs of the digital to analogue converters for dividing one of the analogue outputs by the other, and for 15 providing the result to an output.

2. A method according to claim 1, wherein the bit length N of the first digital value is the same as that of the second digital value.

20 3. A method according to claim 1 or 2, wherein said means for mapping comprises a memory storing a look-up table, the look-up table containing fractional values and respective first and second value pairs, such that the ratio of a first and second value is equal to the corresponding fractional value, the means for mapping further comprising means for looking up the table to 25 find the closest fractional approximation to the M-bit digital signal, and for identifying the corresponding first and second values.

4. A method according to any one of the preceding claims, wherein the means for mapping comprises means for compressing said M-bit digital signal 30 by a factor A, said circuit means comprising means for scaling the result of said division by the same factor A.

5. A method of converting an M-bit digital signal into an analogue signal, the method comprising: mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or approximates 5 the value of the M-bit digital signal; applying said first and second digital values to inputs of the first and second digital to analogue converters respectively; and dividing the analogue output of one of the digital to analogue converters by the other, and providing the result to an output.

6. A vector dot product multiplier comprising: a plurality of multiplication elements, each element having a first input for receiving an analogue input signal, a second input, and an output; control means for generating a digital weight for one or more of said 15 multiplication elements, and having output means for applying generated digital weights to the second inputs of respective multiplication elements; output means having a plurality of inputs coupled to outputs of respective multiplication elements to receive multiplication products therefrom, a plurality of outputs selectively coupled to respective inputs, and means for 20 selectively coupling inputs or outputs together, the control means being coupled to the output means for effecting the selective coupling.

7. A vector dot product multiplier according to claim 6, wherein said control means is a microprocessor or microcontroller capable of periodically 25 reprogramming one or more said digital weights.

8. A vector dot product multiplier according to claim 6 or 7, wherein each multiplication element comprises digital to analogue conversion means having its digital input coupled to the second input of the element so as to receive a 30 digital weight from the control means.

9. A vector dot product multiplier according to claim 8, wherein said digital to analogue conversion means comprises apparatus according to any one of

l, claims 1 to 5, and the applied digital weight corresponds to the M-bit digital signal. 10. A vector dot product multiplier according to claim 9, wherein said circuit 5 means is a translinear multiplier having an input for receiving the corresponding analogue input signal, the output of the translinear multiplier being proportional to the product of the ratio of the first to the second digital value, and the analogue input signal.

10 11. A vector dot product multiplier according to any one of claims 6 to 11, the output means comprising a first plurality of switches for selectively coupling neighbouring inputs of the output means together, and a second plurality of switches coupling inputs of the output means to respective outputs.

Claims

À. À A: À-. 't: ;.. À. I::

Amended claims have been filled as follows Claims 1. Apparatus for converting an M-bit digital signal into an analogue signal, 5 the apparatus comprising: means for mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or approximates the value of the M-bit digital signal; first and second digital to analogue converters, the first digital to 10 analogue converter having an input for receiving said first digital value and the second digital to analogue converter having an input for receiving said second digital value; and circuit means coupled to the analogue outputs of the digital to analogue converters for dividing one of the analogue outputs by the other, and for 15 providing the result to an output.
2. A method according to claim 1, wherein the bit length N of the first digital value is the same as that of the second digital value.

20
3. A method according to claim 1 or 2, wherein said means for mapping comprises a memory storing a look-up table, the look-up table containing fractional values and respective first and second value pairs, such that the ratio of a first and second value is equal to the corresponding fractional value, the means for mapping further comprising means for looking up the table to 25 find the closest fractional approximation to the M-bit digital signal, and for identifying the corresponding first and second values.
4. A method according to any one of the preceding claims, wherein the means for mapping comprises means for compressing said M-bit digital signal 30 by a factor A, said circuit means comprising means for scaling the result of said division by the same factor A.

À. t r; IS
5. A method of converting an M-bit digital signal into an analogue signal, the method comprising: mapping the M-bit digital signal to first and second digital values, so that the ratio of the first to the second digital value is equal to or approximates 5 the value of the M-bit digital signal; applying said first and second digital values to inputs of the first and second digital to analogue converters respectively; and dividing the anaiogue output of one of the digital to anaiogue converters by the other, and providing the result to an output.
6. A vector dot product multiplier comprising: a plurality of multiplication elements, each element having a first input for receiving an analogue input signal, a second input, and an output; control means for generating a digital weight for one or more of said 15 multiplication elements, and having output means for applying generated digital weights to the second inputs of respective multiplication elements; output means having a plurality of inputs coupled to outputs of respective multiplication elements to receive multiplication products therefrom, a plurality of outputs selectively coupled to respective inputs, and means for 20 selectively coupling inputs or outputs together, the control means being coupled to the output means for effecting the selective coupling, wherein each multiplication element comprises digital to analogue conversion means having its digital input coupled to the second input of the element so as to receive the digital weight from the control means, said digital 25 to analogue conversion means comprising apparatus according to any one of claims 1 to 5, and the applied digital weight being the M-bit digital signal.
7. A vector dot product multiplier according to claim 6, wherein said control means is a microprocessor or microcontroller capable of periodically 30 reprogramming one or more said digital weights.

: '-e it: À 7. A vector dot product multiplier according to claim 6, wherein said circuit 5 means is a translinear multiplier having an input for receiving the corresponding analogue input signal, the output of the translinear multiplier being proportional to the product of the ratio of the first to the second digital value, and the analogue input signal.

10
8. A vector dot product multiplier according to claim 6 or 7, the output means comprising a first plurality of switches for selectively coupling neighbouring inputs of the output means together, and a second plurality of switches coupling inputs of the output means to respective outputs.