DE10393686T5 - Configurable functional implementation system and digital / analog converter - Google Patents

Abstract

Apparatus for converting an M-bit digital signal into an analog signal, the apparatus comprising:
means for mapping the M-bit digital signal to first and second digital values such that the ratio of the first digital value to the second digital value equals or approximates the value of the M-bit digital signal;
a first and a second digital-to-analog converter, the first digital-to-analog converter having an input for receiving said first digital value and the second digital-to-analog converter having an input for receiving said second digital value; and
a switching means coupled to the analog outputs of the digital-to-analog converter for dividing one of the analog outputs by the other and providing the result to an output.

Description

The The present invention relates to configurable functional implementation systems such as scalar product multipliers of vectors and to digital to analogue converters. The digital / analog converter of the present invention are particularly, but not necessarily, applicable for use in dot product multipliers of vectors.

angegeben, wobei w_k und x_k das k-te Element der Gewichtungen bzw. des Eingangsvektors sind, y die Ausgabe ist und K die Größe des Eingangsvektors ist.The scalar product multiplication of vectors is a basic operation in discrete-time signal processing and is mathematical as:

where w _k and x _{k are} the k th element of the weights and the input vector respectively, y is the output and K is the magnitude of the input vector.

wobei der Ausgangsvektor y_n gemäß der periodischen Änderung der Gewichtung w_k,n sequentiell in der Zeit erhalten wird. Das Skalarprodukt von Vektoren und die VMM sind der Kern zahlreicher Anwendungen wie etwa jener, die Filter mit endlicher Impulsantwort, diskrete Fourier-Transformationen und die diskreten Cosinustransformationen ausführen.By allowing for a discrete-time dimension, denoted by the subscript n in the output and in the weighting, equation (1) can be reformulated for matrix multiplication operations of vectors (VMM operations):

wherein the output vector y _{n is obtained} sequentially in time according to the periodic change of the weight w _{k, n} . The scalar product of vectors and the VMM are at the core of many applications, such as those that execute finite impulse response filters, discrete Fourier transforms, and the discrete cosine transforms.

With respect to system implementations of scalar product operations of vectors and VMM operations, the following properties may be relevant:
Programmability - refers to the ability to change the coefficients of the individual weighting elements at runtime to change the functionality of the device.

• a) der Genauigkeit – bezieht sich auf die Fähigkeit, die SNR-Charakteristik des Systems zur Laufzeit zu ändern;
• b) der Komplexität – bezieht sich auf die Fähigkeit, die Größe der Operation zur Laufzeit zu ändern. Rekonfigurierbarkeit – bezieht sich auf die Fähigkeit, die Anzahl der Operationen, die in einem gegebenen Netz parallel ausgeführt werden, zur Laufzeit zu ändern, so dass die Rekonfigurierbarkeit die Definition der Skalierbarkeit der Komplexität verkörpert und erweitert.

scalability

• a) accuracy - refers to the ability to change the SNR characteristic of the system at runtime;
• b) complexity - refers to the ability to change the size of the operation at runtime. Reconfigurability - refers to the ability to change the number of operations performed in parallel on a given network at run time so that reconfigurability embodies and extends the definition of complexity scalability.

In purely digital systems are used to implement scalar product operations of vectors and VMM operations typically digital signal processors (DSPs). Because of the big one Number of multiplications involved are these implementations but often Power hungry and inefficient. A multiplication operation is done bitwise in a DSP and is multi-step what Clock frequencies requires several times higher than the signal frequency are.

• [1] R. Genov and G. Cauwenberghs, "Charge-Mode Parallel Architecture for Vector Matrix Multiplication", Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, Bd. 48, S. 930–936, 2001,
• [2] V. A. Pedroni, "Error-compensated analog cells for vector multiplication and vector quantization", Circuits and Systems II: Analog and Digital Signal [3] Processing, IEEE Transactions on, Bd. 48, S. 511–519, 2001 und
• [3] T. Y. Lin and A. J. Payne, "Programmable analogue vector-matrix multiplier," Electronic Letters, Bd. 38, S. 1–2, 2002.

Scalar product operations of vectors and VMM operations are not limited to the digital domain, and there are examples of analog scalar product and mixed signal scalar product of vectors and of analog and mixed-signal VMM cells. Such operations are for. As described in:

• [1] R. Genov and G. Cauwenberghs, "Charge-Mode Parallel Architecture for Vector Matrix Multiplication," Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, Vol. 48, pp. 930-936, 2001,
• [2] VA Pedroni, "Error-compensated analog cells for vector multiplication and vector quantization", Circuits and Systems II: Analog and Digital Signal [3] Processing, IEEE Transactions on, Vol. 48, pp. 511-519, 2001 and
• [3] TY Lin and AJ Payne, "Programmable Analogue Vector-Matrix Multiplier," Electronic Letters, Vol. 38, pp. 1-2, 2002.

Although the charge mode multiplication operation is performed in the analog domain in the implementation described in [1], the digital representation is in bit-serial inputs and matrix elements are stored locally in bit-parallel form embedded in the architecture. In this approach, the multiplication is implicitly performed in the charge transfer operation by a series of Boolean AND operations. A more 'analog' access is made in [2], where the inputs, weights and outputs are represented by continuous analog variables and the multiplication is achieved using the square-law characteristics of MOS transistors in saturation. [3] selects another approach in which the inputs and weights modulate the phases of the input current and the weighting current, respectively. To obtain the output, a translinear multiplier coupled to low pass filtering is used.

In these 'analog' accesses of the The prior art becomes the topology of the system at design time The systems do not have the above-mentioned reconfigurability. For this Additions can the programmability (that is, the definition of a matrix discrete weighted coefficient) by the integer scaling of a Modulation parameters such as the area of a capacitor or Resistance can be obtained, the coefficient by the ratio of this Parameter value is given to the unit value.

in the Generally, digital accesses analog accesses superior in terms of noise and accuracy. Because the accuracy of the system the lower limits of the signal to noise ratio for one prescribes given dynamic range, the two performance metrics depend together. In digital access is the accuracy of the system is determined by the "width" of the bus. In analog access, in where the weights are programmed digitally, the accuracy can be of the system due to noise and errors such as due to the adjustment be limited.

As has already been noted is a component of a matrix multiplier vectors used in the mixed analogue / digital signal domain, probably a digital to analogue converter (DAC). DACs play one fundamental and necessary role in bridging the separation between the quantized data manipulated in digital space, and the continuous signals that the real world uses interacts. However, DACs consume for mobile and portable devices that require low power consumption and a small chip area require a substantial part of the benefit budget. While the Increased accuracy required by an application becomes physical Problems such as the adaptation, the power supply sensitivity and other problems more critical, giving a lower limit to the Minimum size of the quantization step provides. restrictions the chip area and power consumption then set an upper limit the resolution (i.e., the number of input bits) of the device. Thus consumed a low-resolution DAC for one given minimum quantization step less power, since he has one accordingly has lower Vollausschlaghub.

It becomes an accurate, low-power, programmable and reconfigurable Method of execution vector operations such as scalar products of vectors and VMM and operations of scalars such as polynomial functions for the function approximation, for the Signal processing and for the calculation needs to meet the growing demand for independent, on the body worn lifestyle and sensor interface products. In any such method is optimizing the performance of the DAC probably the solution.

According to a first aspect of the present invention, there is provided an apparatus for converting an M-bit digital signal into an analog signal, the apparatus comprising:
means for mapping the M-bit digital signal to first and second digital values such that the ratio of the first digital value to the second digital value equals or approximates the value of the M-bit digital signal;
a first and a second digital-to-analog converter, the first digital-to-analog converter having an input for receiving said first digital value and the second digital-to-analog converter having an input for receiving said second digital value; and
a switching means coupled to the analog outputs of the digital-to-analog converter for dividing one of the analog outputs by the other and providing the result to an output.

The bit length of the first and second digital values is smaller than that of the M-bit digital signal. Although this is not the case, the bit length is N of first digital value preferably equal to that of the second digital one Value.

The bit accuracy that can be achieved by combining two linear digital-to-analog converters according to the present invention is greater than that achieved using one of these converters alone can be achieved. In addition, the power consumed by the two linear (N-bit) converters is generally smaller than that consumed by a single digital-to-analog converter with (2N-1) bits. Another advantage of embodiments of the present invention is that the quantization steps are smaller for small signal levels than for high signal levels. Thus, the (quantization) signal to noise ratios are improved for small signal levels.

Preferably said means for mapping comprises a memory comprising a Lookup table stores, where the lookup table is broken Values and first or second value pairs contains, so that the ratio of a first and a second value equal to the corresponding fractional Is worth. The means for imaging further comprises a means for Look up in the table for the most accurate fractional approximation to determine the M-bit digital signal and the corresponding first one and to identify the second value.

In certain embodiments According to the invention, the device comprises a means for compressing the M-bit digital signal by a factor of A. The compressed M-bit digital signal is passed to the means for mapping. The said circuit means comprises means for scaling the Result of said division by the factor A. Since the signal to noise ratio for little ones Signal level higher is, the signal to noise ratio is over improved the overall dynamic range.

Preferably said switching means is a translinear multiplier.

According to a second aspect of the present invention, there is provided a method of converting an M-bit digital signal to an analog signal, the method comprising:
Mapping the M-bit digital signal to first and second digital values such that the ratio of the first digital value to the second digital value equals or approximates the value of the M-bit digital signal;
Applying said first digital value and said second digital value to the inputs of the first and second digital-to-analog converters, respectively; and
Dividing the analog output of one of the digital-to-analog converters by the other and providing the result to an output.

According to a third aspect of the present invention there is provided an apparatus configurable to evaluate a function, the apparatus comprising:
a plurality of scaling elements, each scaling element having a first input for receiving an analog input signal, a second input, and an output;
a control means for generating a digital weight for one or more of said scaling elements with an output means for applying the generated weights to the second inputs of the respective scaling elements;
output means having a plurality of inputs coupled to outputs of respective scaling elements for receiving scaling products therefrom, having a plurality of outputs selectively coupled to respective inputs, and means for selectively coupling inputs to outputs; wherein the control means is coupled to the output means to perform the selective coupling.

The can be mentioned scaling elements Multiplication elements, division elements or elements that contribute to To run either a multiplication or a division configurable are, be.

The Scaling elements can be purely analog devices, in which case a digital / analog conversion means is provided to the digital weights in analog weights implement. Alternatively you can the scaling elements mixed digital and analog devices be, with the digital weights in this case directly on the scaling elements can be applied.

In an embodiment According to the invention, the device is configurable to be used as a a dot product multiplier of vectors works.

Embodiments of the present invention provide a scalar product multiplier of vectors that can be reconfigured with respect to both the weights applied to the scaling elements and the combination of the elements used to perform a given scaling operation. For example, by appropriate selection of the connections formed in the output means, the device may be configured to parallel two or more multiplication operations where each operation uses a subset of the multiple scaling elements.

Preferably said control means is a microprocessor or a microcontroller, the one or more of said digital weights periodically can reprogram.

Preferably each scaling element comprises a digital to analogue converter (DAC), whose digital input is coupled to the second input of the element is to receive a digital weight from the control means. Preferred receives the DAC at a control input thereof said analogue input signal, while the output of the DAC is coupled to the output of the scaling element is to deliver the multiplication product to the output.

Preferably the output means comprises a first plurality of switches for optionally coupling adjacent inputs of the output means to each other and a second plurality of switches that control the inputs of the Coupling output with respective outputs.

Around a feedback to deliver the scaling elements, the outputs of the Output means are optionally coupled. For example, for each Scaling element summing means may be provided to an initial weighting with a value present at one of these outputs, the result being a digital weighting to the second input of the scaling element is created. The selection of outputs for feedback is preferably controlled by said control means.

According to a fourth aspect of the present invention, there is provided a method of evaluating a polynomial function using the apparatus according to the above third aspect of the present invention, the method comprising:
Factoring in the polynomial function to bring it into a form containing nested multiplication and accumulation terms;
Applying a function variable to the first inputs of at least some of the scaling units and applying function constants as weights to second inputs of at least certain scaling units; and
Configuring the device such that the components of each multiplication and accumulation term are evaluated by the respective scaling elements and summed by the output mean, each sub-sum being passed to a scaling element that evaluates a component of the next-order multiplication and accumulation term.

For a better one understanding of the present invention and to show how this is realized will now be exemplified in the accompanying drawings Reference is made in which:

1 schematically illustrates an MSRMAC system;

2 a multiplier cell of the system 1 illustrated;

3 a reconfiguration bridge of the system 1 illustrated;

4 schematically illustrates a simplified digital / analog conversion system;

5 the system off 4 illustrated in more detail;

6 an alternative digital / analog conversion system is illustrated;

7 illustrates another alternative digital-to-analog conversion system;

8th shows the possible quanta for a digital / analog conversion system with a basic accuracy of 4 bits;

9 a set of graphical representations is the system's performance 5 compare with that of a conventional linear digital-to-analog converter; and

10 illustrates a multiplying digital-to-analog conversion system that eliminates the need for a separate multiplier;

11 a set of graphical representations is the system's performance 9 compare with that of a conventional linear digital-to-analog converter;

12 schematically illustrates an apparatus for evaluating a polynomial function;

13 schematically illustrates an apparatus for evaluating a third order polynomial function; and

14 Switch off a reconfiguration bridge of the device 13 illustrated.

The now described reconfigurable mixed signal multiplication and accumulation system (MSRMAC system) comprises a matrix of analogous Input terminals, which feed a matrix of multiplier cells by a Microprocessor are configurable. The outputs of the multiplier cells are at entrances a reconfiguration bridge (R-BRIDGE), which can also be configured by the microprocessor is. Although the system uses discrete components implemented or in a chip acting as a single component works, can be integrated, it is clear that the preferred Implementation within an integrated system is that way It is constructed that it is one / some predefined or programmable Functions), the vector operations, such as dot product or matrix multiplication operations of vectors or operations of scalars such as in generation of polynomial functions for the function approximation or use it differently.

In 1 is an MSRMAC system that illustrates a matrix of analog input ports 1 includes a one-dimensional array of "analog" multiplier cells 2 feed with respective analogue signals x _k . To the weightings 3 the respective multiplier cells 2 be through a microprocessor 4 digital weights w _k applied. Every cell 2 includes a digital to analog converter (DAC) connected to the cell input 3 is coupled. The DAC may be a conventional linear current output DAC such as a current steering DAC or a "rational" DAC as described in more detail below.

The multiplication functionality of the cells 2 can be implemented by any circuit means which generates an output which is proportional to the multiplication of its two input signals. An example of such an analog multiplier is the emitter-coupled translinear multiplier represented by the in 2 shown transistors M1 to M4 is formed. The output current signal (OUT) is proportional to the multiplication of the current signals applied (after digital / analog conversion) to the ON and WEIGHT terminals.

In an alternative embodiment, the multiplier cell 2 be a conventional linear multiplying DAC with reprogrammable weights that are digitally programmed by the microprocessor with precision and with an analog input signal that scales the output. In another alternative embodiment, a 'rational' multiplying DAC implements both the digital-to-analog converter and the multiplier cell 2 , The rational DAC M-bit digital inputs are mapped to two N-bit digital values, which include the numerator and denominator of the fraction that most closely approximates the digital signal. The two fractions are applied to the inputs of two linear conventional N-bit DACs, with a multiplier circuit generating the division of the outputs as well as any required scaling of the analog input signal, thereby performing both the multiplication and the division simultaneously. In both alternative embodiments, the multiplication is performed by the DAC circuit, eliminating the need for a separate multiplier circuit. The accuracy of implementing the M-bit digital weighting is proportional to the magnitude of the weights, and their accuracy can be scaled by first compressing the digital signal at the input into the rational DAC by a compression factor and the analog input signal by an equivalent scaling factor is scaled. This tuning of accuracy can be done dynamically. With proper tuning of the compression and scaling factors, a higher accuracy is achieved than by a linear conventional DAC with an accuracy of (2N-1) bits. Such variable-precision digital-to-analog conversion means is known as a rational DAC scheme and will be described in more detail below.

ausgedrückt werden, wo das Symbol → eine Umleitung zur Akkumulation bezeichnet und der Rekonfigurierungsvektor r den Zustand des Schalters definiert, wobei r = [r1 r2 ...rN]und der Wert von r_i 0 ist, wenn die Akkumulation der i-ten Ausgabe mit der (i+1)-ten Ausgabe erwünscht ist, oder 1 ist, wenn die i-te Ausgabe als eine Systemausgabe ausgedrückt werden soll, oder 2 ist, wenn die Akkumulation der i-ten Ausgabe mit der (i+1)-ten Gewichtungseingabe erwünscht ist.Again, based on 1 are the outputs of the multiplier cells 2 to respective inputs 5 a reconfiguration bridge (R-BRIDGE) 6 to control a matrix of N multipliers, which is the physical map of a reconfiguration function that performs the redirection of the output of each of the multipliers to either the system output or the subsequent weight input or multiplier output accumulation. Mathematically, the reconfiguration function R (.) Can be used as

where the symbol → denotes a diversion to accumulation and the reconfiguration vector r defines the state of the switch, where r = [r 1 r 2 ... r N ] and the value of r _{i is} 0 if the accumulation of the i-th output with the (i + 1) th output is desired, or 1 if the ith output is to be expressed as a system output, or 2 if the accumulation of the i-th output with the (i + 1) th weight input is desired.

The R-BRIDGE 6 is in 3 shown in more detail and consists of a network of switches through the microprocessor 4 to be controlled. A first set of SELECT switches 7 couples the inputs of the R-Bridge 6 optionally with respective outputs 8th the R-BRIDGE or with the respective weighting entries 10 of the adjacent multiplier, while a second set of SUM switches 9 optionally adjacent inputs / outputs of the R-BRIDGE coupled together. The switch network can be controlled by a single reconfiguration vector r (t).

wobei x_1..n(t) und w_1..n(t) die n Eingaben bzw. Gewichtungsvektoren sind, so dass die Länge von x_n gleich der Länge von w_n ist und die Summe der Längen der n Eingabevektoren (Gewichtungsvektoren) gleich den Längen von x(t) (w(t)) ist. Falls der Bitstrom zum Programmieren der Rekonfigurierungsbrücke ein Vektor r(t) ist, r(t) = m[r1(t) r2(t) ... rN-1(t) 1]T (6)ist die Rekonfigurierungsmatrix s(t) durch

gegeben.The functionality of the matrix of N multiplier cells 3 can be described mathematically as an element-wise multiplication of two vectors of the same dimensions, otherwise known as a Hadamard multiplication (denoted by "o"). In the case of matrix multiplication of vectors then the R-BRIDGE works 6 the Hadamard product to give n scalar product _outputs y _1..n . The results of matrix multiplication of vectors are obtained from sequential outputs over time. Mathematically

where x _1..n (t) and w _1..n (t) are the n inputs and weighting _vectors, respectively, such that the length of x _{n is} equal to the length of w _n and the sum of the lengths of the n input vectors (weighting vectors ) is equal to the lengths of x (t) (w (t)). If the bitstream for programming the reconfiguration bridge is a vector r (t), r (t) = m [r 1 (t) r 2 (t) ... r N-1 (t) 1] T (6) is the reconfiguration matrix s (t) through

given.

The reconfiguration matrix s (t) in (3) serves to separate different groups of the Hadamard product and cumulate the outputs within the group, allowing for a high degree of flexibility and reconfigurability for the system. The reconfiguration bridge implements the necessary Map from r (t) to s (t) in (3) and (7).

By Actuate appropriate switch using a single reconfiguration vector r (t), which is a single digital word, can be the output of all or a subset of the multiplier cells are interconnected and can the resulting sum of products (Kirchhoff's Electricity Act) with a selected one Output can be coupled. The reconfiguration matrix s (t) is used in (3) for separating different groups of the Hadamard product as well as to cumulate the expenses within the group, what a high degree of flexibility and reconfigurability for the system allows. The reconfiguration bridge implements the necessary mapping of r (t) into (3) and (7) s (t).

Thus z. B. the outputs of the top three multiplier cells 3 in the arrangement 3 coupled to each other, the result being at the upper output of the R-BRIDGE 6 can be issued. In addition, the outputs of the lower three multiplier cells 3 coupled to each other, the result being at the lower output of the R-BRIDGE 6 can be issued. The two operations of a sum of products are separated and executed in parallel.

As an example, a 6-dimensional network may be configured to implement a 2 x 2 VMM, a 3 x 3 VMM, and a dot product, where r (t) = (010011) _b . On the other hand, a 6x6 VMM operation is implemented if r (t) = (000001) _b .

In many applications that require multiplication operations, such as the scalar product of vectors or the VMM is the power consumption a decisive factor. This concerns in particular the case portable Devices. Another significant power consumer in An electronic system is often the digital / analog converter.

4 schematically illustrates a digital to analog conversion system suitable for use in a multiplier cell 2 the VMM 1 suitable is. The system is referred to herein as a "rational" DAC and includes an input 11 for receiving an M-bit digital input signal. This digital input signal is one through the microcontroller 4 generated weight w _k . The input signal is sent to an imaging function G (w _k ) 12 created, which is a lookup table 13 used to determine the most accurate approximation of the value of the digital signal to one of a number of fractions stored in the look-up table. The mapping function then identifies an N-bit counter and an N-bit denominator, resulting in the particular fraction. In practice, the mapping function G (w _k ) will likely be using one by the microprocessor 4 executed software routine implements and forms no physical part of the multiplier cell 2 ,

Further, the system includes two (conventional, linear) N-bit DACs 14 . 15 to the respective inputs to which the identified N-bit counter and N-bit denominator are applied. The converted analog outputs appear at analog outputs of the DACs and are applied to the inputs of a translinear multiplier 16 created. The translinear multiplier 16 is more detailed in 5 and comprises four low-inverted MOS transistors or bipolar junction transistors M1 to M4 with exponential IU characteristics. The transistors use the translinear principle to provide quadrant multiplication. The multiplier 16 provides at one output a signal Q (.) which is proportional to the ratio of the analog outputs of the DACs 14 . 15 is. Another input of the multiplier 16 receives a control input comprising a current signal I _B which is applied to scale the output signal.

ausgedrückt werden, wobei I_B ein Vorstrom oder Skalierungsstrom ist und I₁(.) und I₂(.) die Ströme wegen der DACs mit gleichförmig quantisierten Strömen Q_U1(.) bzw. Q_U2(.) sind. Die innerhalb des DSP implementierte Abbildungsfunktion G(.) wählt Q_U1(.) und Q_U2(.) durch Ermitteln der nächsten Übereinstimmung in der Nachschlagetabelle.On closer inspection of the translinear multiplier 16 For example, the product of the left currents is equal to the product of the right currents if the transistors are BJTs or MOSFETs operating in the region below the threshold and exhibit an exponential characteristic. Thus, the output current of the system can be given with an input x as:

where I _{B is} a bias current or scaling current and I ₁ (.) and I ₂ (.) are the currents because of the DACs with uniformly quantized currents Q _U1 (.) and Q _U2 (.), respectively. The mapping function G (.) Implemented within the DSP selects Q _U1 (.) And Q _U2 (.) By determining the closest match in the look-up table.

In the 6 and 7 are two alternative implementations of the current and voltage operation shown with rational DACs. To deliver the required ratios, two standard low-resolution linear DACs are used in all implementations.

Operation of the system off 4 is best exemplified. It is assumed that M is equal to 4 and that the mapping function can generate a counter u and a denominator v of 2 bits each. Each of these components can have four possible values, ie 00, 01, 10 and 11, ie u / v can have eleven possible values 1/4, 1/3, 1/2, 2/3, 3/4, 1, 4 / 3, 11/2, 2, 3 and 4 have. These values are illustrated in Table 1 below. Thus, the two-DAC system results in a larger number of quantization states than by a single linear 3-bit DAC (with eight possible states) provided by the microprocessor 4 a 3-bit weight w _k is received could be achieved.

wobei Q_R die möglichen Quantisierungsschritte eines rationalen Schemas und Q_U1 und Q_U2 jene eines gleichförmig quantisierten Systems sind. Q_U1 und Q_U2 besitzen die gleiche Genauigkeit, die hier als die "Grundgenauigkeit" von Q_R definiert wird. Mit diesem Schema können zwei N-Bit-DACs zusammen abgestimmt werden, um mehr als 2 zur (2N-1)-ten Potenz erhobene Quantisierungszustände zu erhalten. Zur Anpassung der Eingabe an dasjenige Paar ganzzahliger Werte, das die genaueste Näherung ergibt, kann eine Nachschlagetabelle des Zählers, des Nenners und der entsprechenden Verhältnisse verwendet werden. Die Anzahl eindeutiger Quanten und somit die Größe der Nachschlagetabelle für rationale DACs mit einer Grundgenauigkeit von bis zu 8 Bits sind in der unten stehenden Tabelle 2 tabelliert.The quantization states in the rational DAC scheme proposed here are proportional to the ratios of the quantization states of two similar linearly quantized DACs or mathematically:

where Q _{R are} the possible quantization steps of a rational scheme and Q _U1 and Q _{U2 are} those of a uniformly quantized system. Q _U1 and Q _U2 have the same accuracy, which is defined here as the "basic accuracy" of Q _R. With this scheme, two N-bit DACs can be tuned together to obtain more than 2 (2N-1) th power quantization states. To match the input to the one pair of integer values that gives the most accurate approximation, a look-up table of the numerator, denominator, and corresponding ratios can be used. The number of unique quanta and thus the size of the lookup table for rational DACs with a basic accuracy of up to 8 bits are tabulated in Table 2 below.

The quantization steps generated by a rational DAC scheme are not uniformly sized, but increase with signal magnitude. 8th shows z. For example, consider the possible 159 unique quanta of a rational DAC with a basic precision of 4 bits. Since the quantization step is small for small inputs and large for large inputs, the output from a rational DAC will suffer significantly less distortion at low input signal values compared to a purely uniform DAC.

wobei V_pp die Potentialdifferenz über die Versorgungen, I_u der Strom bei der Mindestschrittweite und I_max der als I_max = 2^NI_u gegebene Vollausschlagstrom ist. Offensichtlich ist der Leistungsverbrauch für gegebenes I_max unabhängig von der Genauigkeit oder sind alternativ I_max und P_U für ein gegebenes I_u abhängig von der Genauigkeit. Da der rationale DAC durch gleichförmige DACs mit niedrigerer Genauigkeit eine höhere Auflösung erzielt, besitzt er die Möglichkeit eines niedrigeren Leistungsverbrauchs, während er die an die Vorrichtungsbemessung, an das Netzunterdrückungsfaktorverhältnis und an andere Parameter gestellten physikalischen Anforderungen weiter erfüllt sind.The rational DAC scheme offers the possibility of lower performance by reducing the full swing currents. The power P _{U of} an N-bit current steering DAC is:

where V _{pp is} the potential difference across the supplies, I _{u is} the current at the minimum step size, and I _{max is} the full deflection current given as I _max = 2 ^N I _u . Obviously, the power consumption for a given I _max is independent of the accuracy or alternatively I _max and P _U for a given I _u dependent on the accuracy. As the rational DAC achieves higher resolution through lower accuracy uniform DACs, it has the potential for lower power consumption while still meeting the physical requirements imposed on device rating, network rejection factor ratio, and other parameters.

The performance of a rational DAC has been compared to that of a uniform DAC using MATLAB ^™ . The features are the relative power consumption and the percentage of distortion error for each quant.

power consumption

The input power P _{R of} the rational DAC in 5 is P R (w k ) = 2P U (N) + V pp (Q R (w k ) + I B (12) where P _U (N) is the input power of a uniform N-bit DAC. A comparison was made between a uniform 8-bit DAC with 256 quantization levels and a rational DAC with a basic precision of 4 bits with 159 quantization levels. The input w _k is a uniformly monotonic 104 element vector for approximating a continuous signal that increases linearly from 0 to 1. The increasing size of quantization steps used in a rational DAC is evident in 10a showing the graphs of normalized power consumption for both schemes in all quantization levels. For ease of comparison, it is assumed that the probability of each quantization step is the same, and the mean power comparison for both the uniform DAC scheme and the rational DAC scheme as in 10b indicated by dashed lines. As expected, the average power consumption of the rational DAC is significantly lower than that of the uniform DAC. On average, an ideal uniform DAC consumed 6 times the power required for a rational DAC.

percentage distortion errors

definiert. Da der Fehler für einen gleichförmigen DAC für zunehmendes w_k innerhalb eines konstanten Bands bleibt, wird der Fehler invers reduziert. Der Fehler für das rationale Schema ist komplizierter, da er wegen der zunehmenden Zählerwerte innerhalb der Bänder zunehmend breite Bänder umfasst, die reduziert werden. Dies ist in 10c veranschaulicht. Der Anfangsfehler am Start jedes Bands nimmt wegen abnehmender Nennerwerte mit x zu. Die Bänder überlappen sich für kleines w_k, werden aber für zunehmendes w_k verschiedener. Folglich war die Ausgabe des rationalen DAC für kleine Werte von w_k erheblich weniger gestört als die eines linearen DAC. Allerdings war dies für weniger als 24 % der Zeit wahr; für große Werte von w_k war die Verzerrung wegen des rationalen DAC viel schlechter als die wegen des gleichförmigen DAC.The percent distortion error ε _d for a given quantization level is expressed as the ratio of the difference between the quantized and the actual value to the actual value as a percentage or mathematically by:

Are defined. Since the error for a uniform DAC for increasing w _k remains within a constant band, the error is inversely reduced. The error for the rational scheme is more complicated because it involves increasingly broad bands being reduced because of the increasing counts within the bands. This is in 10c illustrated. The initial error at the start of each band increases with x due to decreasing denominator values. The bands overlap for small w _k , but become more different for increasing w _k . Consequently, the issue of the rational DAC for small values of w was less disturbed _k significantly than that of a linear DAC. However, this was true for less than 24% of the time; for large values of w _k , the distortion due to the rational DAC was much worse than that due to the uniform DAC.

The poor performance of the rational DAC for large values of w _k can be attributed to an oblique distribution of quanta, which is dense at the bottom and thin at the top. For a rational 4-bit DAC, only 8 quanta accounts for values of w _k of 0.5 to 1, leaving 151 steps for smaller values. Discarding the larger quanta above can increase the overall accuracy of the rational DAC system.

rationale DACs with scalable accuracy

ausgedrückt werden. Falls A zur Laufzeit abgestimmt wird, kann folglich ein mögliches Schema zur Skalierung der effektiven Genauigkeit des DAC erzielt werden, das ein besseres Leistungsmanagement einer Vorrichtung ermöglicht.Although the performance of the rational scheme is poorer than that of a linear scheme (with the same overall input bit accuracy), its power consumption is significantly lower. By balancing power consumption versus bit accuracy, the rational DAC SNR can be improved. This can be achieved by compressing w _k by a scale factor A to "ignore" the quanta at the high end of the dynamic range. Consequently, the reduced signal is quantized by the finer quanta at the bottom of the quantization "conductors" to obtain an increase in accuracy. In order to obtain the same full scale analogue output signal, the bias current must be increased by an equivalent factor A. The power consumption increases in proportion to the SNR. The output current Q _R (.) Of the system with an input w _k may be referred to as

be expressed. Thus, if A is tuned at run time, a possible scheme for scaling the effective accuracy of the DAC can be achieved, allowing for better power management of a device.

In order to implement the function of scaling accuracy, the architecture in 5 as in 9 shown modified. The input to block G (.) Is reduced by A within the DSP while I _{B is} increased by an equivalent factor. Thus, the expression for the performance of a scalable rational DAC is then P R (w k ) P U1 (w k ) + P U2 (w k ) + A (I B + Q R (w k )) V pp (15)

The performance of a rational DAC with scalable accuracy with the basic accuracy of 5 bits was compared in MATLAB ^™ at different scale factors with that of a uniform DAC with an accuracy of 5 to 8 bits. As in the above analysis, two features were tabulated and compared: percent relative power and relative percent distortion error. The relative power in percent is calculated as:

The relative percent distortion error (PDE) is the relative measure of the percent distortion error between a rational and a uniform DAC and is calculated as the sum of the elements described by the operators greater than, less than or equal to. For example

The simulation results confirm the analysis that by compressing the inputs so that the signal is quantized within a smaller but denser range and subsequently expanding to obtain the same full scale range, higher accuracy is obtained at the expense of increasing power consumption can. However, because of the possibility of a smaller full scale range, the power consumption levels are still significantly less than those required for a uniform DAC. For example, those shown in Table 3 below and in FIG 11 graphically presented results that the rational DAC scaled at A = 10 at 35% of the input power of a uniform 8-bit DAC for 46.8% of the time has a lower percent distortion error than the uniform DAC and similar errors for 17.8% of the time Has.

In general, the effective accuracy of the quantization (PDE _R <PDE _U ) increases with A. This is consistent with a comparable increase in power consumption. Thus, it can be observed that A has a direct effect on both the accuracy and power consumption of the DAC. By designing the system so that A is easily tunable, a rational DAC can be implemented that can scale the accuracy at run time. It is noted that certain values of A result in suboptimal performance where the performance of a uniform DAC exceeds that of a rational DAC in terms of accuracy and / or power consumption. Such configurations are indicated in Table 3 with an asterisk "*".

Of the Additional effort Software or digital complexity, which is a lookup table and the processing for adapting the input to the appropriate one Require index in the LUT are in the discussion above not treated. Although the effort taken by itself not insignificant the complexity of digital complexity in the context of a mixed signal processing environment, through the intimate mix of digital and analog computation The numerous local low-power DACs with acceptable capacity requires to be shared by all DACs. Thus, the Overhead of this extra digital complexity at a big one Number of local DACs very low. This is in the above True VMM.

gegeben sind. Für k = b₀2⁰ + b₁2¹ + ... + b_N-12^N-1 tritt der maximale Verzerrungsfehler in der Mitte zwischen zwei benachbarten Quantisierungsschritten auf, wobei er als

gegeben ist. Es ist klar, dass der maximale Verzerrungsfehler unabhängig von k und somit für alle Eingabewerte konstant ist (wobei außerdem angemerkt wird, dass der maximale Verzerrungsfehler von der Anzahl der verwendeten Bits unabhängig ist). Somit kann mit einem solchen Schema die wie oben beschriebene Technik der Kompandierung nicht verwendet werden, um das SNR des DAC wirksam zu skalieren.Rational DACs implement a nonlinear quantization scheme which is reasonably compared to a logarithmic scheme with quantization steps Q _LOG (

given are. For k = b ₀ 2 ⁰ + b ₁ 2 ¹ + ... + b _N-1 2 ^N-1 , the maximum distortion error occurs in the middle between two adjacent quantization steps, using as

given is. It will be appreciated that the maximum distortion error is constant regardless of k and thus for all input values (also note that the maximum distortion error is independent of the number of bits used). Thus, with such a scheme, the technique of companding as described above can not be used to effectively scale the SNR of the DAC.

entspricht einer Zunahme von r eine entsprechende Verringerung des Dynamikbereichs δ_L des DAC. Um das SNR ohne Verlust des Dynamikbereichs zu verbessern, sind somit strengere Nebenbedingungen an r sowie ein Bedarf an mehr Bits erforderlich. Demgegenüber kann das SNR des vorgeschlagenen rationalen DAC-Schemas leicht zur Laufzeit abgestimmt werden. Außerdem besitzt der rationale DAC einen weiten Dynamikbereich δ_R, der als die größte zur kleinsten dargestellten Zahl definiert ist und für einen rationalen DAC mit der Grundgenauigkeit von N Bits als δ_R = 2^N/2^-N = 2^2N gegeben ist.To improve SNR performance, r must be set closer to one, imposing stricter limits during manufacturing. Because of

corresponds to an increase of r a corresponding reduction of the dynamic range δ _{L of} the DAC. Thus, to improve the SNR without loss of dynamic range, more stringent constraints on r and a need for more bits are required. In contrast, the SNR of the proposed rational DAC scheme can be easily tuned at runtime. In addition, the rational DAC has a wide dynamic range δ _R , which is defined as the largest number represented to the smallest and given for a rational DAC with the basic precision of N bits as δ _R = 2 ^N / 2 ^-N = 2 ^2N .

Based on 1 A scalar product multiplier of vectors has been described above. A modified arrangement of this architecture for use in evaluating polynomial functions will now be described.

Polynomial functions constitute an important class of multiplication and accumulation functions, their usefulness being evident from the various applications in which they are found, such as power series for solving differential equations and approximating analytic functions. Polynomial functions can be defined as follows:

Multiplikationen erforderlich sind. Allerdings kann die Gleichung unter Verwendung des Horner-Schemas (J.-M. Muller, "Algorithms and Architectures", in Elementary Functions, Boston: Birkhäuser, 1997, S. 43) in:
(23)
faktorisiert werden, was nur N-1 Multiplikationen und Additionen erfordert, da die Polynomfunktion als Reihe verschachtelter linearer Gleichungen ausgedrückt wird.A naive analysis of this equation could lead to the conclusion that to calculate the output

Multiplications are required. However, the equation can be calculated using the Horner scheme (J.Muller, "Algorithms and Architectures", Elementary Functions, Boston: Birkhäuser, 1997, p.
(23)
which requires only N-1 multiplications and additions since the polynomial function is expressed as a series of nested linear equations.

By integrating "feedforward" between the outputs of the reconfiguration bridge 6 and the summation elements (not shown, but present at the transitions between the weight input lines and the feedback lines), the structure can be determined on the basis of 12 to be configured not only to do scalar product multiplication of vectors, but also to evaluate polynomial functions. In 12 All lines shown transmit analogue signals and all the processing is carried out in the analogue area. The digital-to-analog conversion of the digital weights is performed by respective DACs not shown in the figure. However, it is clear that multiplication DACs (including rational DACs) can be used, with both the digital weights and the analog feedback signals being supplied to the multiplication DACs. This requires a modification to the multiplication DACs as described above.

wobei M = floor(N/2) ist.In 12 For example, the outputs of adjacent multiplier pairs used to represent the linear equations y = ax + b are applied to the subsequent weighting input of the next pair, resulting in an interlaced representation of a polynomial function factored using the Horner scheme. The resulting expression in terms of network variables is:

where M = floor (N / 2).

Now consider the specific example of a third-order polynomial:

To map this to the proposed network, the inputs would have to be such that the signal input matrix would be off 12 has the following values: x = [x 1 x 1 x 1] and the (digital) weights have the following values: w = [a ₁ a ₂ 0 a ₃ 0 an]. This is in 13 illustrated. If the multiplier elements are labeled MUX1-6, Table 4 below shows the respective inputs and outputs, from which it can be seen that the multiplication and accumulation terms (MAC terms), ie, a sum of a linear component and a constant, are evaluated in the first place, and the results are coupled forward to allow evaluation of higher-order terms.

zu den Ausgängen OUT1 oder OUT2 gelenkt. Wenn TG hoch ist, wird der Multipliziererausgang mit Ausnahme des letzten Multipliziererausgangs y_N, der für alle Fälle zum Ausgang o_N kurzgeschlossen wird, zum nächsten Multipliziererausgang kurzgeschlossen, d. h. y_i → y_i+1. Ein Kurzschluss zwischen dem Multipliziererausgang y_i und dem Ausgang o_i tritt auch dann auf, wenn TG tief ist.The reconfiguration function R (.) As described above becomes using a network of switches within the reconfiguration bridge 6 realized with the aim of separating or cumulating (summing) outputs of the multiplier matrix according to the required reconfiguration. As in 14a 2, each multiplier output in the matrix may be connected to a toggle switch to implement the reconfiguration function. The input current I _IN is depending on the potential of TG with

directed to the outputs OUT1 or OUT2. When TG is high, the multiplier output, except for the last multiplier output y _N , which is shorted to the output o _{N in} all cases, is shorted to the next multiplier output, ie, y _i → y _{i + 1} . A short circuit between the multiplier output y _i and the output o _{i also} occurs when TG is low.

In the above reconfiguration function R (.), A changeover switch is required for all even outputs, while for each of the odd index multiplier outputs as in 14b shown with the exception of the last multiplier output shorted to the output, a three way switch is required. The three-way switch comprises two alternating switches connected in series. The output OUT2 of the changeover switch is supplied to the input of another changeover switch to realize a three-way switch. In both the toggle switch and the three-way switch, current flow to the outputs requires a potential gradient between the inputs and the outputs.

In the 14 For simplicity, such switches may be implemented in the manner of pass transistors using NMOS and PMOS transistors, although such a realization in practice results in the need for the potential difference across the drain and source of the transistor to be greater than that Threshold voltage of this device would be to see a loss of "high level of voltage" at each cascade. In a practical implementation, transfer gates may be used to overcome this limitation.

For the expert It will be understood in the art that changes are made to the embodiments described above can be made without departing from the scope of the present invention.

Tabelle 1

Table 1

Tabelle 2

Table 2

Tabelle 3

Table 3

Tabelle 4

Table 4

Summary

Device for converting an M-bit digital signal into an analog signal. The device comprises a means ( 12 . 13 ) for mapping the M-bit digital signal into first and second digital values such that the ratio of the first digital value to the second digital value equals or approximates the value of the M-bit digital signal. There are a first and a second digital / analog converter ( 14 . 15 ), wherein the first digital / analog converter ( 14 ) an input for receiving the first digital value and the second digital / analog converter ( 15 ) has an input for receiving the second digital value. With the analogue outputs of the digital / analog converters ( 14 . 15 ) is a circuit means ( 16 ) to divide one of the analog outputs by the other and provide the result to an output.

Claims (17)

Apparatus for converting an M-bit digital signal to an analog signal, wherein the apparatus is um comprising: means for mapping the M-bit digital signal to first and second digital values such that the ratio of the first digital value to the second digital value equals or approximates the value of the M-bit digital signal; a first and a second digital-to-analog converter, the first digital-to-analog converter having an input for receiving said first digital value and the second digital-to-analog converter having an input for receiving said second digital value; and switching means coupled to the analog outputs of the digital to analog converter for dividing one of the analog outputs by the other and providing the result to an output. Method according to Claim 1, in which the bit length N of the first digital value the same as that of the second digital one Value is. A method according to claim 1 or 2, wherein said Means for mapping a memory comprising a lookup table stores, where the lookup table is broken values and first contains second value pairs, so the ratio a first and a second value equal to the corresponding fractional value Value, the means for mapping further being a means for looking up in the table includes, to the most exact broken approximation to determine the M-bit digital signal and the corresponding first one and to identify the second value. Method according to one of the preceding claims, wherein the means for imaging comprises means for compressing said M-bit digital signal by a factor A, wherein said Circuit means means for scaling the result of said Division by the same factor A includes. Method for converting an M-bit digital signal in an analog signal, the method comprising: Depict of the M-bit digital signal on a first and on a second digital value, so the ratio of first digital value equal to the second digital value Value of the M-bit digital signal approaches or approximates; Creating the mentioned first digital value and said second digital value to the inputs of the first and second digital / analog converter; and To divide the analog output of one of the digital / analog converters by the others and delivering the result to an exit. Device configurable to evaluate a function is, wherein the device comprises: a variety of scaling elements, wherein each scaling element has a first input for receiving an analog input signal, a second input and a Output owns; a control means for generating a digital Weighting for one or more of said scaling elements with an output means for applying the generated weights to the second inputs of the respective ones Scaling elements; an output device with a plurality of inputs those with outputs respective scaling elements are coupled to scaling products receive from it, with a variety of outputs that can be used with either inputs and means for selectively coupling inputs or outputs with each other, wherein the control means coupled to the output means is to carry out the optional coupling. Apparatus according to claim 6, wherein said Scaling elements Multiplication elements, division elements or Elements to execute either a multiplication or a division configurable are, are. Apparatus according to claim 7, wherein said Scaling elements are multiplying digital / analog converters. Device according to one of claims 6 to 8, wherein the device is configurable to be a scalar product multiplier works of vectors. Apparatus according to claim 6, wherein each scaling element a digital / analog converter whose digital input with the second input of the element is coupled to the control means a receive digital weighting. Apparatus according to claim 10, wherein each digital to analog converter at a control input thereof, said analog input signal receives the output of each digital-to-analog converter being connected to the output of the scaling element is coupled to the output of the multiplication product to deliver. Device according to one of the preceding claims, wherein the dispensing means selectively selects a first plurality of switches Coupling of adjacent entrances the dispensing means with each other and a second plurality of switches, the entrances coupling the output means to respective outputs. Apparatus according to claim 6, wherein the outputs of the Output means are optionally coupled to feedforward for the Create scaling elements. Apparatus according to claim 13, for each Scaling element summing means for summing an initial weighting with one at one of the exits the output means existing value, the result as the weight to the second input of the scaling element is created. Method for evaluating a polynomial function under Use of the device according to claim 6, wherein the method Includes: Factorize the polynomial function to them into a form, the nested multiplication and Contains accumulation terms; Invest a function variable to the first inputs at least certain of Scaling units and applying function constants as weights to second inputs at least certain scaling units; and Configure the device in such a way that the components of each multiplication and accumulation terms by the respective scaling elements evaluated and summed by the output means, each one Subtotal is passed to a scaling element, the a component of the multiplication and accumulation term of next Order evaluates. The method of claim 15, comprising coupling those inputs the output means which deliver components to be summed together, and coupling the coupled inputs to either one output the output means or with a second input of another Scaling element comprises. The method of claim 15, wherein the coupled ones inputs in the output means over a summing point that also receives a weight that represents a functional constant, with a scaling element coupled, wherein the output of the summing point with a second Input of the scaling element is coupled.