GB2357355A - A synchronous SRAM - Google Patents

Abstract

A synchronous SRAM for performing burst mode operation comprises a sense amplifier 26 for sensing and amplifying data of memory cells 25, an output data path/data storing circuit 27 for storing output signals of the sense amplifier, and simultaneously setting output paths of the output signals in response to switch control signals, an output circuit 28 for providing output signals of the output data path/data storing circuit, an input circuit 30 for inputting signals, an input data path/data storing circuit 31 for storing the signals from the input circuit and simultaneously setting input paths of the input signals in response to the switch control signals, a write driving circuit 32 for simultaneously writing the output signals of the input data path/data storing circuit in the memory cells, and a path switch controller 24 for generating the switch control signals in response to address bits, and control signals.

Description

2357355 A SYNCHRONOUS SRAM S The present invention relates to a

semiconductor memory device, and more particularly, to a switch signal generator and a high-speed synchronous SRAM using the same.

Among semiconductor memory devices, a high-speed SRAM is used mainly as a cache memory of a system, and as the difference in speeds of a CPU and a DRAM widens as the performance of systems improves, the need for a cache memory increase. In addition, though different high-speed SRAMs are required according to the clock frequencaes of CPUs, standard asynchronous SRAMs of 10-20ns are typically being used in systems operating at speeds of 100Mhz or less, and the need for high-speed synchronous SRAMs of 100-220Mhz are increasing according to an increase in the clock frequencies of CPUs. Hence, synchronous SRA.Ms have been used as cache SRAMs in low-end personal computers as well as products such as high-end workstations and servers.

As for synchronous SRAMs, there is a synchronous pipeline type and a synchronous burst type. The former is used as a cache SRAM for reduced instruction set computer (RISC) series chips, whereas the latter is used as a cache SRAM for complex instruction set computer (CISC) -MPUs of Intel and Motorola. The present invention pertains to the 1 synchronous burst SRAM.

FIG. 1 is a schematic block diagram of a conventional synchronous SRAM, centered around a tursz control scheme.

Here, a read/write control path is not shown.

Referring to FIG. 1, the conventional synchronous SRAM has an address bufferinq portion 1, a burst controlling portion 2, a clock generating portion 3, and a burst counting portion.4. In addition, the conventional synchronous SRAM further include a memory cell array 5, a sense amplifying portion 6, an output data path/data storing portion 7, an output buffer 8, and an input/output pin 9.

The conventional synchronous SRA-M also include an input buffering portion 10 externally, an input data path/data storing portion 11, and a write driving portion 12.

In the conventional synchronous SRAN of FIG. 1, the transmission sequences of output data and input data are determined by controlling the sense amplifying portion 6 and the write driving portion 12, or a word line or column selection line of the memory cell array 5 by means of the burst address BSTAD which is the output signal of the burst counting portion 4.

FIG. 2 is a diagram for illustrating the burst read operation of the conventional synchronous SRAM shown in FIG.

1.

Referring to FIG. 2, when a burst read operation is performed in the conventional synchronous SRAM of FIG 1, the burst address (BSTAD) is generated in the burst- counting portion 4. the data of a memory cell is sensed in the sense 2 amplifying portion 6, and the sensed data is latched in the output data path/data storing portion 7, during each of the other cycles T2, T3, and T4 except for the first and fifth cycles T1, T5. That is, the processes of sensing, latching, and outputting data are influenced by the burst counting portion 4 during every cycle of the system clock signal CLK.

Thus, when an ultra high-speed burst read operation is intended in the conventional synchronous SRAM, that is, when the frequency of the system clock signal CLK increases and thus the periods of the cycles decrease, the processes of generating burst addresses and sensing, latching, and outputting data should be performed during a short cycle, thus possibly causing malfunction. When the frequency of the system clock signal CLK increases and the periods of the cycles decrease as well, during the burst write operation, malfunctions may occur as during the above burst read operation. Furthe-tmore, it is difficult to read or write data in pairs during a single cycle, that is, to implement a double data rate function in the conventional synchronous SRAM of FIG. 1.

An object of the present invention is to provide a switch signal generator which can simultaneously set input data paths in order to realize a synchronous SRAM for performing an ultra high-speed burst operation.

Another object of the present invention is to provide a synchronous SRAM for performing an ultra high-speed burst operation.

Still another object of the present invention is to 3 provide a synchronous SR-B.Pi for easy reading or writing of data in pairs during a single cycle, that is, for easily implementing a double data rate function.

According to a first aspect of the present invention, a switch signal generator comprises first logic means for receiving first and second control signals and a plurality of input signals, performing logic operations on the received signals, and generating a first switch signal, and second logic means for receiving the first switch signal and the first control signal, sequentially generating the other switch signals, and sequentially enabling the other switch signals when the first switch signal is enabled.

The first logic means comprises NOR means for receiving the first and second control signals and NOR-operating the received signals, and AND means for receiving the output signal of the NOR means and the plurality of input signals, AND-operating the received signals, and generating the first switch signal. The second logic means comprises a plurality of sequentially connected unit logic means, and the unit logic means each include inverting means for inverting a switch signal output from the previous unit logic means, and NOR means for receiving the output signal of the inverting means and the first control signal, NOR-operating the received signals, and generating a switch signal.

According to a second aspect of the present invention, a synchronous SRAM comprises an output data path/data storing portion for storing output signals of a sense amplifying portion, and simultaneously setting output paths 4 of the output signals in response to switch control signals, an in)ut data path/data storing portion for Storing signals buffered in an input buffering portion, and simultaneously setting input paths of the buffered signals in response to the switch control signals, and a path switch controlling portion for generating the switch control signals in response to predetermined address bits and predetermined first and second control signals.

The synchronous SRAM of the present invention further comprises a sense amplifying portion, an output buffering portion, an input buffering portion, and a write driving portion.

The sense amplifying portion senses and amplifies data of memory cells and outputs the amplified data to the output data path/data storing portion. The output buffering portion buffers output signals of the output data path/data storing portion in response to an internal clock signal and outputs the buffered signals. The input buffering portion buffers externally input signals in response to the internal clock signal and outputs the buffered signals to the input data path/data storing portion. The write driving portion writes output signals of the input data path/data storing portion in memory cells.

The address bits are generated by an address externally received during a burst mode operation. The first control signal indicates the end or stop of the burst mode operation. The second control signal enables the path switch controlling portion, and selects either a linear burst mode or an interleave burst mode.

The output data path/data storing portion comprises a read data register block for storing output signals of the sense amplifying portion, a plurality of output data path lines, a path switch block for connecting the output terminals of the read data register block to the respective output data path lines in response to the switch control signals, and an output data register block for storing signals transmitted through the respective data path lines and outputting the stored signals to the output buffering portion.

The input data path/data storing portion comprises a write data register block for storing signals input to the input terminals thereof and outputting the stored signals to the write driving portion, a plurality of input data path lines, a path switch block for connecting the input terminals to the respective input data path lines in response to the switch control signals, and an input data register block for storing signals buffered in the input buffering portion and outputting the buffered signals through the respective input data path lines.

The path switch controlling portion comprises first switch signal generating means for generating a first group of switch signals in response to the first and second control signals, the address bits, and inverted address bits of the address bits, second switch signal generating means for generating a second group of switch signals in response to the first control signal, an inverted signal of the 6 second control signal, and the address bits, and the inverted address bits, and logic means having a plurality of OR means for OR-operating one of the first group of switch signals and one of the second group of switch signals and generating the respective switch control signals. Here, the first switch signal generating means includes a plurality of unit switch signal generators for generating some of the firs't group of switch signals as output signals in response to bits selected from the address bits and the inverted address bits, and the first and second control signals, and sequentially enabling the other output signals when a first output signal among the output signals is enabled. The second switch signal generating means includes a plurality of unit switch signal generators for generating some of the second group of switch signals as output signals in response to the bits selected from the address bits and the inverted address bits, and the first signal, and the inverted signal of the second control signal, and sequentially enabling the other output signals when a first output signal among the output signals is enabled.

Examples of the present invention will now be described in detail with reference to the accompanying drawings, in which:

FIG. 1 is a schematic block diagram of a conventional synchronous SRA-M; FIG. 2 is a diagram for illustrating a burst read operation of the conventional synchronous SRAM shown in FIG.

1; - 7 FIG. 3 is a circuit diagram of a switch signal generator according to an embodiment of the present invention; FIG. 4 is a schematic block diagram of a synchronous SRAM according to an embodiment of the present invention; FIG. 5 is a diagram for illustrating a burst read operation of the synchronous SRAM shown in FIG. 4; FIG. 6 is a detailed block diagram of a data path portion of the synchronous SRAM shown in FIG. 4; FIG. 7 is a detailed diagram of the path switch controlling portion in the synchronous SRAM of FIG. 6; and FIG. 8 illustrates address tables for a linear burst mode and an interleave burst mode in a synchronous SRAM.

FIG. 3 is a circuit diagram of a switch signal generator according to an embodiment of the present invention.

Referring to FIG. 3, the switch signal generator includes a first logic means 3c for receiving first and second control signals from both control ports CNT1 and CNT2, and input signals from both input ports IN1 and IN2, performing logic operations on the signals, and generating a first switch signal to an output port SW1, a line latch 3a for latching the first switch signal. The switch signal generator further includes a second logic means 3b for receiving the first switch signal and the f irst control signal, sequentially generating second through fourth switch signals to respective output ports SW2, SW3, and SW4, and sequentially enabling the second through fourth switch 8 signals when the first switch signal is enabled.

The first logic means 3c includes a NOR gate NR1 for NOR-operating the first and second control signals received from both the control ports CNT1 and CNT2, and an AND gate AND1 for AND-operating an output signal of the NOR gate NR1 and the signals received from both the input ports IN1 and IN2, and generating the first switch signal to the output part SW1. The linelatch 3a includes an inverter 15 having an input terminal connected to an output terminal of the AND gate AND1, and an inverter 16 having an input terminal connected to the output terminal of the inverter 15 and an output terminal connected to the output terminal of the AND gate AND1. In addition, the second logic means 3b includes three sequentially connected unit logic means 3bl, 3b2, and 3b3. The unit logic means 3bl, 3b2, and 3b3 include respective inverters 12, 13, and 14 for inverting switch signals of their previous unit logic means and respective NOR gates NR2, NR3, and NR4 for NOR-operating signals received from the inverters 12, 13, and 14 and the first control signal, and generating switch signals.

The switch signal generator operates as follows. When either of the first and second control signals received respectively from both the control ports CNT1 and CNT2 is logic high, all the switch signals output to the output ports SW1-SW4 become logic low. When both the f irst and second control signals received from the control ports CNT1 and CNT2 are logic low, the states of the output ports SW1 SW4 are determined by the signals received from the input 9 ports IN1 and IN2. That is, when bot'- the signals received from the input ports IN1 and!N2 are logic low, or either of the signals is logic low, all the switch signals output to the output ports SW1-SW4 become logic low. When both the signals received from the input ports IN1 and IN2 are logic high, the output signal of the AND gate AND1 is logic high.

Thus, the first switch signal output to the output port SW1 is enabled logic high, and the second through fourth switch signals output to the output ports SW2-SW4 are sequentially enabled logic high.

FIG. 4 is a schematic block diagram of a synchronous SRAM using the switch signal generator of FIG. 3. Since a burst control scheme is mainly illustrated in the block diagram of FIG. 4, basic read/writt -e control paths are not shown.

is Referring to FIG. 4, the synchronous SRAM includes an address buffering portion 21 for receiving an externally applied address, a burst controlling portion 22 for controlling a read/write operation and a burst mode setting, a clock generating portion 23 for generating an internal clock signal ICLK which is synchronized with an externally input system clock signal, and a -Qath switch controlling portion 24 for generating a switch control signal SWCONi in response to the output signals of the address buffering portion 21 and the burst controlling portion 22. In order to read data from a memory cell array 25, the synchronous SRAM is further provided with a sense amplifying portion 26 for sensing and amplifying data transmitted from the memory cell array 25, an output data path/data storing portion 27 for storing an output signal of the sense amplifying portion 26, and simultaneously setting output paths of the stored output signal in response to the switch control signal SWCONi, and an output buffering portion 28 for buffering an output signal of the output data path/data storing portion 27 in response to the internal clock signal ICLK and outputting the buffered signal through an input/output pin 29. To write externally input data in the memory cell array 2S during a burst write operation, the synchronous SRAM of the present invention also includes an input buffering portion 30 for buffering a signal externally received through the input/output pin 29 in response to the internal clock signal ICLK, an input data path/data storing portion 31 for simultaneously setting input paths of the input is signal buffered in the input buffer 30 and storing the input signal, and a write driving portion 32 for writing an output signal of the input data path/data storing portion 31 in the memory cell array 2S.

The above-described synchronous SRAM of FIG. 4 is different from the conventional synchronous SRAM of FIG. 1 in that the burst counting portion of the conventional synchronous SRAM is replaced by the path switch controlling portion 24, and the switch control signal SWCONi being the output signal of the path switch controlling portion 24 2S controls the output data path/data storing portion 27 and the input data path/data storing portion 31. The path switch controlling portion 24 is constituted of switch signal generators shown in FIG. 3, and its detailed description will be given later. Here, the synchronous SRAM may be constituted such that the switch control signal SWCON_J controls the sense amplifying portion 26 and the write driving portion 32, or a word line or column selection line of the memory cell array 25.

Thus, in the synchionous SRAM of FIG. 4, all burst orders and all data paths of the output data path/data storing portion 27 and the input data path/data storing portion 31 are set by the switch control signal SWCONi, simultaneously when a burst operation starts. The subsequent operation, that is, a data outputting process is not influenced by the control of the burst operation. This will be described in detail later referring to FIGs. 6 and 7.

FIG. 5 is a diagram for illustrating a burst read operation of the synchronous SRAM shown in FIG. 4.

Referring to FIG. 5, the burst read operation of the synchronous SRAM shown in FIG. 4 will be described. Here, a burst length is 4 data units and a register-register mode is given.

During a first cycle T1 of the system clock signal CLK, a burst mode is set by the burst controlling portion 22 in the synchronous SRAM of FIG. 4. Then, the burst operation starts, the sense amplifying portion 26 simultaneously senses and amplifies four data, that is, first through fourth data, transmitted from the memory cell array 25 upon external input of a first address, and the output: data 12 path/data storing portion 27 latches the sensed and amplified first through fourth data in response to the switch control signal SWCONi. Then, the latched first data is, output through the input/output pin 29 by way of the output buffering portion 28 during a second cycle T2 of the system clock signal CLK,.the latched second data is output during a third cycle T3, and the latched third data is output during a fourth cycle T4. During a fifth cycle TS, the latched fourth data is output, the first cycle Ti resumes if the read operation continues, and otherwise, the burst operation ends.

A burst write operation is performed in a path reverse to that for the above-described burst read operation, that is, through input data paths, and a detailed operation thereof is omitted here.

is FIG. 6 is a detailed diagram of a data path portion of the synchronous SRAM shown in FIG. 4. Like reference numerals denote the same components as those of FIG. 4.

Referring to FIG. 6, the synchronous SRAM includes the memory cell array 25, the sense amplifying portion 26, the output data path/data storing portion 27, a time demultiplexer 33, the output buffering portion 28, the input/output pin 29, the input buffering portion 30, a time multiplexer 34, the input data path/data storing portion 31, the write driving portion 32, and the path switch controlling portion 24.

The sense amplifying portion 26 includes first through fourth sense amplifiers 26a-26d for sensing and amplifying 13 data received from memory cells selected from the memory cell array 25, respectively. The output data path/data storing portion 27 includes a read data register block 27R, a path switch block 27S, output data path lines ODP1-ODP4, and an output data register block 270. The read data register block 27R is provided with first through fourth read data registers 27Ra-27Rd for storing the output signals of the sense amplifiers 26a-26d, respectively. The path switch block 27S is connected between the output terminals of the read data registers 27Ra-27Rd and the output data path lines ODP1-ODP4, and includes a plurality of path switches S1-S16 which are simultaneously controlled by switch control signals SWCON11-SWCON44. In addition, the output data register block 270 includes first through fourth output data registers 270a-270d for storing signals transmitted through the out-put data path lines ODP1-ODP4, respectively. The output signals of the output data registers 270a-270d are demultiplexed in the time demultiplexer 33 and sequentially output to the outside by way of the output buffering portion 28 and the input/output pin 29.

The input data path/data storing portion 31 includes a write data register block 31R, a path switch block 31S, input data path lines IDP1-IDP4, and an input data register block 311. The input data register block 311 is provided with first through fourth data registers 31Ia-31Id for storing signals sequentially received externally by way of the input/output pin 29, the input buffering portion 30, and 14 the time multiplexer 34, and outputting the respective input signals to the input data path lines!DP1-IDP4- The write data register block 31R includes first through fourth write data registers 31Ra-31Rd for storing signals input to their input terminals. The path switch block 31S is connected between the input terminals of the write data registers 31Ra-31Rd and the input data path lines IDP1-IDP4, and includes a plurality of path switches S17-S32 which are simultaneously controlled by the switch control signals SWCON11-SWCON44. In addition, the write driving portion 32 includes first through fourth write drivers 32a-32d for receiving the output signals of the write data registers 31Ra-31Rd and writing the received signals in memory cells selected from the memory cell array 25.

The path switch controlling portion 24 receives first and second control signals RESET and DSENB, a plurality of address bits AO and Al, and a plurality of inverted address bits AOB and AlB, the address bits and the inverted address bits being applied at the start of the burst operation, and generates the switch control signals SWCON11-SWCON44. The first control signal RESET is sent in conjunction with the end or stop of the burst operation, and the second control signal DSENB enables the path switch controlling portion 24 and is sent in conjunction with read/write operations and a burst mode (a linear burst mode and an interleave burst mode). Each of the read data registers 27Ra-27Rd is connected to one of the output data path lines ODP1-ODP4 by activating one of the four path switches, which are connected to the output terminals of the read data registers, by means of one of the switch control signals SWCON11-SWCON44. In addition, each of the write data registers 31Ra-31Rd is connected to one of the input data path lines IDPl-IDP4 by activating one of the four path switches, which are connected to the input terminals of the write data registers, by means of one of the switch control signals SWCON11-SWCON44.

FIG. 7 is a detailed diagram of the path switch controlling portion in the synchronous SRAM of FIG. 6.

Referring to FIG. 7, the path switch controlling portion is provided with a first switch signal generating portion 24a, a second switch signal generating portion 24b, and a logic means 24c.

The first switch signal generating portion 24a serves to set all burst orders at a linear burst mode, and generates a first group of 16 switch signals LSWCON11 LSWCON44 in response to the first and second control signals RESET and DSENB, the plurality of address bits AO and Al, and the plurality of inverted address bits AOB and A1B. The first switch signal generating portion 24a is activated at the linear burst mode, that is, when the second control signal DSENS is logic low, and includes four unit switch signal generators 24al-24a4. The unit switch signal generators 24al-24a4 each have the same circuitry as that of the switch signal generator shown in FIG. 3.

The unit switch signal generator 24al outputs switch signals LSWCON11, LSWCON22, LSWCON33, and LSWCON44 16 corresponding to burst orders of case 1 at the linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to A05, A1B, RESET, DSENB respectively input to both the input ports IN1 and IN2 and both the control ports CNT1 and CNT2. The unit switch signal generator 24a2 outputs switch signals MWCON21, LSWCON32, LSWCON43, and LSWCON14 corresponding to burst orders of case 2 at the linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to AO, A1B, RESET, DSENB respectively input to both the input ports IN1 and!N2 and both the control ports CNT1 and CNT2. The unit switch signal generator 24a3 outputs switch signals LSWCON31, LSWCON42, LSWCON13, and LSWCON24 corresponding to burst orders of case 3 at the linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to AOB, Al, RESET, DSENB respecti vely input to both the input ports INI and IN2 and both the control ports CNT1 and CNT2. The unit switch signal generator 24a4 outputs switch signals LSWCON41, LSWCON12, LSWCON23, and LSWCON34 corresponding to burst orders of case 4 at the linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to AO, Al, RESET, DSENB respectively input to both the input ports IN1 and IN2 and both the control ports CNT1 and CNT2.

The second switch signal generating portion 24b serves to set all burst orders at an interleave burst mode, and generates a second group of 16 switch signals ISWCON11- 17 ISWCON44 in response to the first control signal RESET, the inverted signal DSENBB of the second control signal DSENB, inverted in the inverter Il, the plurality of address bits AO and Al, and the plurality of inverted address bits AOB and A1B. The second switch signal generating portion 24b is activated at the interleave burst mode, that is, when the second control signal DSENB is logic high, and includes first through fourth unit switch signal generators 24bl 24b4. The unit switch signal generators 24bl-24b4 each have the same circuitry as that of the switch signal generator shown in FIG. 3.

Here, the unit switch signal generator 24bl outputs switch signals ISWCON11, ISWCON22, ISWCON33, and ISWCON44 corresponding to burst orders of case 1 at an interleave linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to AOB, A1B, RESET, DSENBB respectively input to both the input ports IN! and IN2 and both the control ports CNT1 and CNT2. The unit switch signal generator 24b2 outputs switch signals ISWCON21, ISWCON12, ISWCON43, and ISWCON 34 corresponding to burst orders of case 2 at the interleave linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to AO, A13, RESET, DSENBB respectively input to both the input ports IN1 and IN2 and both the control ports CNT1 and CNT2. The unit switch signal generator 24b3 outputs switch signals ISWCON31, ISWCON42, ISWCON13, and ISWCON24 corresponding to burst orders of case 3 at the interleave linear burst mode shown 18 in FIG. 8 to the output port s Sq'l, SW2, SW3, and SW4, respectively, in response to A,0B, Al, RESET, DSENBB respectively input to both the input ports IN1 and IN2 and both the control ports CNT1 and CNT2. In addition, the unit switch signal generator 24b4 outputs switch signals ISWCON41, ISWCON32, ISWCON23, and ISWCON14 corresponding to burst orders of case 4 at the interleave linear burst mode shown in FIG. 8 to the output ports SW1, SW2, SW3, and SW4, respectively, in response to AO, Al, RESET, DSENBB respectively input to both the input ports IN1 and IN2 and both the control ports CNT1 and CNT2.

The logic means 24c includes 16 OR-gates each for OR- operating one of the first group of switch signals LSWCON11 LSWCON44 and one of the second group of switch signals ISCON11-ISCON44, and generating a corresponding switch control signal among the switch control signals SWCON11 SWCON44.

A burst control scheme and a data path control scheme of a synchronous SRAM will now be described referring to FIGs. 6 and 7.

When the burst operation starts and a first burst address is externallyapplied, the states of the first and second control signals RESET and DSENB, the plurality of address bits AO and Al, and the plurality of inverted address bits AOB and A13 are determined. For example, when both the first and second control signals RESET and DSENB are logic low, that is, a linear burst mode is set, and both AO and A1 are logic high, only the unit switch signal 19 generator 24a4 of the first switch signal generating portion 24a shown in FIG. 7 is activated. That is, four switch signals LSWCON41, LSWCON12, LSWCON23, and LSWCON34 being the output signals of the unit switch signal generator 24a4 among the first group of 16 switch signals LSWCON11-LSWCON44 and the second group of 16 switch signals ISCON ll-ISCON44 is enabled logic high, and the others are disabled logic low. Thus, only four switch signals SWCON41, SWCON12, SWCON23, and SWCON34 among the 16 switch signals SWCON11 SWCON44 being the output signals of the logic means 24c are enabled logic high, and the others are logic low.

Therefore, by turning on path switches S2, S7, S12, and S13 of the path switch block 27S shown in FIG. 6, the output terminal of the first read data register 27a is connected to the input terminal of the output data register 270b, the output terminal of the second read data register 27Rb is connected to the input terminal of the third output data register 270c, and the output terminal of the third read data register 27Rc is connected to the input terminal of the fourth output data register 270d. In addition, by turning on path switches S18, S23, S28, and S29 of the path switch block 31S, the output terminal of the first input data register 3lIa is connected to the input terminal of the fourth write data register 31Rd, the output terminal of the second input data register 31Ib is connected to the input terminal of the first write data register 31Ra, and the output terminal of the third input data register 31Ic is connected to the input terminal of the second write data register 31Rb, and the fourth input data register 31Id is connected to the input terminal of the third write data register 31Rc.

As described above, in the synchronous SRAM of the present invention, all burst orders are set in the path switch controlling portion 24, simultaneously when the burst operation starts, and all input and output data paths are simultaneously set by the switch control signals SWCON11 SWCON44 being the output signals of the path switch controlling portion 24.

Consequently, by applying the switch signal generator of the present invention to a synchronous SRAM, all input and output data paths are simultaneously set. In addition, in the synchronous SRAM using the switch signal generator, since all input and output data paths are simultaneously 1S set, a subsequent operation, that is, a data outputting or inputting process is not influenced by the control of the burst operation. Thus, in the synchronous SRAM of the present invention, an ultra high-speed burst operation can be performed, and it is easy to read or write data in pairs in a single cycle, that is, to implement a double data rate function.

21

Claims (46)

0 CLAIMS

1 A synchronous SP-kM f or performing a burst mode operation, comprising:

a sense amplifying portion for sensing and amplifying data of memory cells; an output data path/data storing portion for storing output signals of the sense amplifying portion, and simultaneously setting output paths O-L the output signals in response to switch control signals; an output buffering portion for buffering output signals of the output data path/data storing portion in response to an internal clock signal, an input buffering portion for buffering eternally input signals in response to the internal clock signal; is an input data path/data storing portion for storing the signals buffered in the input buffering portion and simultaneously setting input paths of the buffered signals in response to the switch control signals; a write driving portion for simultaneously writing the output signals of the input data path/data storing portion in memory cells; and a path switch controlling portion for generating the switch control signals in response to address bits, and the first and second control signals.

2. The device of claim 1, wherein the internal clock signal is synchronized with an externally input system clock 22 0 signal and generated internally.

3. The device of claim 1, wherein the address bits are generated by an address externally applied during the burst mode operation.

4. The device of claim 1, wherein the first control signal indicates the end or stop of the burst mode operation.

5. The device of claim 1, wherein the second control signal enables the path switch controlling portion and selects one of a linear burst mode and an 1nterleave burst mode.

6. The device of claim 1, wherein the output data path/data storing portion comprises a read data register block for storing the output signals of the sense amplifying portion, a plurality of output data path lines, a path is switch block for connecting the output terminals of the read data register block to the respective output data path lines, and an output data register block for storing signals transmitted through the respective output data path lines and outputLing the stored signals to the output buffering portion.

7. The device of claim 6, wherein the path switch block comprises a plurality of path switches which are 23 0 connected between the output terminals of the plurality ofL read data registers in the read data register block and the respective output data path lines, and controlled by the switch control signals.

a. The device of claim 1, wherein the input data path/data storing portion comprises a write data register block for storing, signals received through the input terminals thereof and outputting the stored signals to the write driving portion, a plurality of input data path lines, a path switch block for connecting the input terminals of the write data register block to the respective input data path lines in response to the switch control signals, and an input data register block for storing the signals buffered in the input buffering portion and outputting the stored signals to the respective input data path lines.

9. The device of claim 8, wherein the path switch block comprises a plurality of path switches which are connected between the input terminals of the plurality of write data registers in the write data register block and the respective input data path lines, and controlled by the switch control signals.

10. The device of claim 1, wherein the path switch controlling portion comprises:

first switch signal generating means for generating a group of switch signals in response to the first and second 24 0 control signals, the address bits, and the inverted address bits of the address bits; second switch signal generating means for generating a second group of switch signals in response to the f irst control signal, the inverted signal of the second control signal, the address bits, and the inverted address bits; and logic means having a plurality of OR means for OR operating one of the first group of switch signals and one of the second group of switch signals and outputting the switch control signals.

11. The device of claim 10, wherein the first switch signal generating means is activated when the second control signal is logic low.

12. The device of claim 10, wherein the second switch signal generating means is activated when the second control signal is logic high.

13. The device of claim 10, wherein the first switch signal generating means comprises a plurality of unit switch signal generators for generating some of the first group of switch signals as output signals in response to bits selected from the address bits and the inverted address bits, and the first and second control signals, and sequentially enabling the other output signals when a first output signal is enabled.

0

14. The device of claim 13, wherein the unit switch signal generators each comprise first logic means for receiving the first and second control signals and the selected bits, performing a logic operation on the received bits and signals, and generating the first output signal, and second logic means for receiving the first output signal and the first control signal and sequentially generating the other output signals.

15. The device of claim 14, wherein the first locic means comprises NOR means for receiving the first and second control signals and NOR-operating the received signals, and AND means for receiving the output signal of the NOR means and the selected bits, And-operating the received signals, and generating the first switch signal.

16. The device of claim 13, wherein the second logic means comprises a plurality of sequentially connected unit logic means, each unit logic means including inverting means for inverting a signal output from the previous unit logic means, and NOR means for receiving the output signal of the inverting means and the first control signal and generating an output signal.

17. The device of claim 13, wherein when one of the first and second control signals is logic high, all the output signals of the unit switch signal generators are disabled logic low.

26 0

18. The device of claim 13, wherein when both the first and second control signals are logic high, all the output signals of the unit switch signal generators are disabled logic low.

19. The device of claim 13, wherein when both the first and control signals are logic low and all the selected bits are logic high, all the output signals are enabled logic high.

20. The device of claim 10, wherein the second switch signal generating means comprises a plurality of unit switch signal generators for generating some of the second group of switch signals as output signals in response to bits selected from the address bits and the inverted address bits, the first control signal, and the inverted signal of the second control signal, and sequentially enabling the is other output signals when a first output signal is enabled.

21. The device of claim 20, wherein the unit switch signal generators each comprise first logic means for receiving the first and second control signals and the selected bits, performing a logic operation on the received signals and bits, and generating the first output signal, and second logic means for receiving the first output signal and the first control signal and sequentially generating the other output signals.

27 0

22. The device of claim 21, wherein the first logic means comprises NOR means for receiving the first and second control signals and NOR-operating the received signals, and AND means for receiving the output signal of the NOR means and the selected bits, AND-operating the received signals, S and generating the first switch signal.

23. The device of claim 21, wherein the second logic means comprises a plurality of sequentially connected unit logic means, each unit logic means including inverting means for inverting a signal output from the previous logic means, and NOR means for receiving the output signal of the inverting means and the first control signal, NOR-operating the received signals, and generating an output signal.

24. The device of claim 20, wherein when one of the first control signal and the inverted signal of the second control signal is logic high, all the output signals of the unit switch signal generators are disabled logic low.

25. The device of claim 20, wherein when both the inverted signals of the first and second control signals are logic high, all the output signals of the unit switch signal generators are logic low.

26. The device of claim 20, wherein when both the inverted signals of the first and second control signals are logic low, and all the selected bits are logic high, all the 28 0 output signals are enabled logic high.

27. A synchronous SRAM for performing a burst mode operation, comprising:

a plurality of sense amplifiers for sensing and amplifying data of memory cells; a plurality of read data registers for storing data output from each of.the sense amplifiers; a plurality of output data path lines; a plurality of path switches which are connected between the output terminals of the respective read data registers and the respective output data path lines, and simultaneously controlled by switch control signals; a plurality of output data registers for storing data transmitted through the respective output data path lines; a plurality of input data path lines; a plurality of input data registers for storing sequentially input data and outputting the stored data to the respective input data path lines; a plurality of write data registers for storing data input to the respective input terminals thereof; a plurality of path switches which are connected between the input terminals of the respective write data registers and the respective input data path lines and simultaneously controlled by the switch control signals; a plurality of write drivers for writing the output data of the respective write data registers in memory cells; and 29 0 a path switch controller for generating the switch control signals in response to address bits, and the first and second control signals.

28. The device of claim 27, wherein the address bits are generated by an address externally input during the burst mode operation.

29. The device of claim 27, wherein the first control signal indicates the end or stop of the burst mode operation.

30. The device of claim 27, wherein the second control signal enables the path switch controller and selects one of a linear burst mode and an interleave burst mode.

31. The device of claim 27, wherein the path switch controller comprises:

firs'. switch signal generating means for generating a group of switch signals in response to the first and second control signals, the address bits, and the inverted bits of the address bits; second switch signal generating means for generating a second group of switch signals in response to the first control signal, an inverted signal of the second control signal, the address bits, and the inverted address bits; and logic means having a plurality of OR means for OR operating one of the first group of switch signals and one 0 of the second group of switch signals, and generating the respective switch signals.

32. The device of claim 31, wherein the first switch signal generating means is activated when the second control signal is logic low.

33. The device of claim 31, wherein the second switch signal generating means is activated when the second control signal is logic high.

34. The device of claim 31, wherein the first switch signal generating means comprises a plurality of unit switch signal generators for generating some of the first group of switch signals as output signals in response to bits selected from the address bits and the inverted address bits, and the first and second control signals, and sequentially enabling the other output signals when a first is output signal is enabled.

35. The device of claim 34, wherein the unit switch signal generators each comprise first logic means for receiving the first and second control signals and the selected bits, performing a logic operation on the received signals and bits, and generating the first output signal, and second logic means for receiving the first output signal and the first control signal and sequentially generating the other output signals.

31 0

36. The device of claim 35, wherein the first logic means comprises NOR means for receiving the first and second control signals and NOR-operating the received signals, and AND means for receiving the output signal of the NOR means and selected bits, AND-operating the received signals, and generating the first switch signal.

37. The device of claim 35, wherein the second logic means comprises a plurality of sequentially connected unit logic means, each unit logic means including inverting means for inverting a signal output from the previous unit logic means, and NOR means for receiving the output signal of the inverting means and the first control signal, NOR-operating the received signals, and generating an output signal.

38. ' The device of claim 34, wherein when one of the first and second control signals is logic high, all the is output signals of the unit switch signal generators are disabled logic low.

39. The device of claim 34, wherein when both the first and second control signals are logic high, all the output signals of the unit switch signal generators are disabled logic low.

40. The device of claim 34, wherein when both the first and second control signals are logic low and all the selected bits are logic high, all the output signals are 32 0 enabled logic high.

41. The device of claim 31, wherein the second switch signal generating means comprJ ses a plurality of unit switch signal generators for generating some of the second group of switch signals as output signals in response to bits selected from the address bits and the inverted address bits, the first control signal, and the inverted signal of the second control signal, and sequentially enabling the other output signals when a first output signal is enabled.

42. The device of claim 41, wherein the unit switch signal generators each comprise NOR means for receiving the first and second control signals and NOR-operating the received signals, AND means for receiving the output signal of the NOR means and the selected bits, AND-operating the received signals, and generating the first output signal, and logic means for receiving the first output signals and the first control signal, and sequentially generating the other output signals.

43. The device of claim 42, wherein the logic means comprises a plurality of sequentially connected unit logic means, each unit logic means including inverting means for inverting a signal output from the previous unit logic means, and NOR means for receiving the output signal of the inverting means and the first control signal, NOR-operating the received signals, and generating an output signal.

33 0

44. The device of claim 41, wherein when one of the first and second control signals is logic high, all the output signals of the unit switch signal generators are disabled logic low.

45. The device of claim 41, wherein when both the first and second control signals are logic high, all the output signals of the unit switch signal generators are disabled logic low.

46. The device of claim 41, wherein when both the first and second control signals are logic low and all the selected signals are logic high, all the output signals are enabled logic high.

34