GB2357355B - A synchronous sram - Google Patents

A synchronous sram

Info

Publication number
GB2357355B
GB2357355B GB0105232A GB0105232A GB2357355B GB 2357355 B GB2357355 B GB 2357355B GB 0105232 A GB0105232 A GB 0105232A GB 0105232 A GB0105232 A GB 0105232A GB 2357355 B GB2357355 B GB 2357355B
Authority
GB
United Kingdom
Prior art keywords
synchronous sram
sram
synchronous
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
GB0105232A
Other versions
GB2357355A (en
GB0105232D0 (en
Inventor
Hak-Soo Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019970002676A external-priority patent/KR100247923B1/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of GB0105232D0 publication Critical patent/GB0105232D0/en
Publication of GB2357355A publication Critical patent/GB2357355A/en
Application granted granted Critical
Publication of GB2357355B publication Critical patent/GB2357355B/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
GB0105232A 1997-01-29 1997-08-22 A synchronous sram Expired - Lifetime GB2357355B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019970002676A KR100247923B1 (en) 1997-01-29 1997-01-29 Switch signal generator and high speed synchronous SRAM using thereof
GB9717917A GB2321739B (en) 1997-01-29 1997-08-22 A switch signal generator for simultaneously setting every input/output data path

Publications (3)

Publication Number Publication Date
GB0105232D0 GB0105232D0 (en) 2001-04-18
GB2357355A GB2357355A (en) 2001-06-20
GB2357355B true GB2357355B (en) 2001-08-01

Family

ID=26312118

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0105232A Expired - Lifetime GB2357355B (en) 1997-01-29 1997-08-22 A synchronous sram

Country Status (1)

Country Link
GB (1) GB2357355B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5416740A (en) * 1991-12-12 1995-05-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including redundant memory cell array for repairing defect
GB2320779A (en) * 1996-12-27 1998-07-01 Fujitsu Ltd Synchronous semiconductor memory device
US5949697A (en) * 1996-12-10 1999-09-07 Samsung Electronics, Co., Ltd. Semiconductor memory device having hierarchical input/output line structure and method for arranging the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5416740A (en) * 1991-12-12 1995-05-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device including redundant memory cell array for repairing defect
US5949697A (en) * 1996-12-10 1999-09-07 Samsung Electronics, Co., Ltd. Semiconductor memory device having hierarchical input/output line structure and method for arranging the same
GB2320779A (en) * 1996-12-27 1998-07-01 Fujitsu Ltd Synchronous semiconductor memory device

Also Published As

Publication number Publication date
GB2357355A (en) 2001-06-20
GB0105232D0 (en) 2001-04-18

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Legal Events

Date Code Title Description
PE20 Patent expired after termination of 20 years

Expiry date: 20170821