GB2352380A

GB2352380A - Random access video memory control

Info

Publication number: GB2352380A
Application number: GB9904674A
Authority: GB
Inventors: Rabin Ezra
Original assignee: Canon Inc
Current assignee: Canon Inc
Priority date: 1999-03-01
Filing date: 1999-03-01
Publication date: 2001-01-24
Anticipated expiration: 2019-03-01
Also published as: GB9904674D0; GB2352380B

Abstract

A graphics controller manages a pixel buffer 200 and a Z buffer 202 in memory. Memory can be considered as a series of rows each containing a plurality of storage locations. A memory controller is provided to manage the allocation of memory to the two buffers, such that each row of the memory on which a portion of the pixel buffer 200 is stored also has a portion of the Z buffer 202 stored thereon.

Description

2352380 RANDOM ACCESS MEMORY CONTROL The present invention is concerned

with the control of random access memory, and has particular application in

the field of computer graphics, especially threedimensional computer graphics.

In order to display scenes consisting of objects existing in three dimensions, it is necessary to convert data defining those objects in three-dimensions into rasterised data which can be displayed on a VDU. Therefore, it is necessary to establish which objects or parts thereof are visible from a given viewpoint. Some objects may at least partially obscure other objects within the volume being viewed. Many different methods of determining which objects within a scene are visible from a viewpoint have been proposed. These are collectively known as visible surface algorithms.

one simple visible surface algorithm is called the Z buffer algorithm. The Z buffer algorithm requires that two buffers be defined. A first frame or pixel buffer is defined for storage of colour values per pixel, and a second Z buffer is defined to hold information concerning the depth of a pixel from the viewpoint. When scanning an object into the frame buffer, each pixel thereof is mapped to an entry in the Z buffer, and the 2 depth of the pixel on the object in question is compared with that entry. If the pixel on the object is found to be nearer the viewpoint than the entry in the Z buffer, then the pixel is entered into the frame buffer and the entry in the Z buffer is adjusted accordingly.

In computer games consoles, and personal computers, the f rame buf f er and the Z buf f er are commonly def ined in dynamic random access memory (DRAM). DRAM is conveniently conceptualised in the form of an array of rows and columns or addresses. A typical DRAM assigned with a frame buffer and a Z buffer is illustrated in Figure 1. In that figure, a DRAM 10 is illustrated schematically, having rows R and column C. In practice, the DRAM should have substantially the same number of rows as columns.

A region 20 positioned at the top of the DRAM is configured to contain a frame buffer. A corresponding region 22 at the bottom of the DRAM 10 is configured to contain a correspondingly sized Z buffer. In practice, when converting an object into the frame buffer, a pixel is selected for consideration. Firstly, a row reference must be made to the appropriate place in the Z buf f er corresponding to the pixel in question. Then, the Z value held on the Z buffer is compared with the Z value corresponding to the pixel on the object in question.

3 If the pixel is to be written to the frame buffer, a second row reference must then be made to the appropriate place in the frame buffer 20.

Performing two row references per pixel can become laborious and time consuming. Although the procedure could be accelerated somewhat by considering groups of pixels at a time, the act of rasterising objects into the frame buffer involves a large number of row references.

It is an object of the present invention to provide improvements to problems outlined above.

Specific embodiments of the invention will now be described by way of example only with reference to the accompanying drawings in which:

Figure 1 is a schematic diagram of dynamic random access memory allocated in accordance with prior art described above; Figure 2 is a schematic diagram of a personal computer to be configured in accordance with a first specific embodiment of the present invention; Figure 3 is a schematic diagram of a video controller of the personal computer illustrated in Figure 2; 4 Figure 4 is a schematic diagram of a graphics controller of the video controller illustrated in Figure 3; Figure 5 is a schematic diagram of an interconnection 5 within the graphics controller of Figure 4; Figures 6a and 6b illustrate the reallocation of dynamic random access memory in accordance with the first specific embodiment; Figure 7 is a f low diagram of a method of controlling memory in accordance with a second embodiment of the invention; Figure 8 is a f low diagram of a subprocedure of the method illustrated in Figure 7; Figure 9 is a schematic diagram of a computer games console configured in accordance with a second embodiment of the invention; Figures 10a and 10b illustrate the reallocation of memory within a second f orm of dynamic random access memory allocated in accordance with either the f irst or the second specific embodiments of the invention; Figure 11 is a schematic diagram, similar to Figure 5, I corresponding to the reallocation of memory illustrated in Figures 10a and 10b; Figure 12 is a schematic diagram showing intermediate 5 allocation of memory in accordance with the reallocation of Figures 10a and 10b; Figure 13 is a schematic diagram of a portion of a drawing engine showing apparatus for performing pre- processing of reallocation in accordance with Figures 10a and 10b; and Figure 14 is a schematic diagram of details of the apparatus illustrated in Figure 13.

As illustrated in Figure 2, a first specific embodiment of the invention comprises a personal computer 100. The personal computer 100 comprises a central processing unit (CPU) which operates via a basic input output system (BIOS) 104 and with reference to system ROM 106 and system RAM 108. The BIOS 104 operates under the instruction of the CPU 102. The personal computer 100 further comprises a drive controller 110 operable under instructions sent by the BIOS 104 to control drives connected to the personal computer 100, such as those illustrated, namely a CD ROM drive 112 for receiving a CD ROM 114, a floppy disk drive 116 for receiving a 6 floppy disk 118 and a hard disk drive 120 housing a hard disk. The BIOS 104 is capable of retrieving data from each of these devices via the drive controller 110.

The personal computer 100 further comprises a video controller 122 and a serial port 124. Each of these devices is conveniently supplied in the form of a circuit card which can be connected into the personal computer 100. The video controller 122 is connected with a VDU 126 for the display of graphical images, and the serial port 124 is connected with a modem 128 by which the personal computer can be connected to a network such as an Intranet or the Internet.

The personal computer 100 is further connected with a keyboard 130 and a mouse 132 for input of instructions by a user. Other input devices such as a tracker ball or a microphone could also be connected in addition or in the alternative.

Communication between the BIOS 104 and the various devices connected therewith, such as the video controller 122, the serial port 124 and the drive controller 110 can be conducted by means of a local bus such as a peripheral component interconnect (PCI) local bus. This is a convenient technology which allows plug and play, i.e. devices can be added or removed from the personal 7 computer without need for complicated manual configuration procedures.

Figure 3 illustrates in further detail the internal structure of the video controller of the first specific embodiment of the video controller 122. The video controller 122 comprises an interface controller 150 which includes a connector for connection with the PCI local bus previously described. A graphics controller 152 interprets commands received by the interface controller 150, for the composition of a graphical image to be presented on the VDU 126. A memory 154 is provided on the video controller 122, specifically to allow for the arrangement of a frame buffer (or pixel buffer) and a corresponding Z buffer. A raster output unit 156 refers to the pixel buffer stored in the memory 154 by means of address lines and data lines, and outputs serialised data to a digital-to-analog converter (DAC) 158, for the generation of a video signal for output to the VDU 126.

The graphics controller 152 is typically constructed of a single integrated circuit. However, it can be considered to consist of a drawing engine 180 and a memory controller 182. This arrangement is illustrated in Figure 4. It will be understood that these two components could alternatively be provided as separate 8 integrated circuits within the video controller 122.

The drawing engine 180 is operative to carry out a drawing application, such as receiving data describing graphical primitives, processing that data and sending data f or storage in the pixel buf f er and the Z buf f er defined in the memory 154. That data can then be converted into a serialised output for conversion into a video signal 160.

The memory controller 182 is provided to intercede between the drawing engine 180 and the memory 154. This is because the memory 154 may not have been designed specifically for the particular drawing engine 180 provided in the video controller 122. For example, the memory 154 could be static RAM or dynamic RAM. The memory controller 182 is provided to allow the design of the drawing engine 180 to be independent of other hardware provided in the video controller 122. The drawing engine 180 may be configurable by instructions in software, which may be designed for contiguous memory. The memory manager allows the software application implemented on the drawing engine 180 to be unaware of the existence of dynamic 'RAM which can be viewed more easily in terms of an array.

An interconnection between the drawing engine 180 and the I 9 memory controller 182 is provided and is referenced as 184 in Figure 4. This interconnection is shown with a cross linkage which will be described with further detail with reference to Figures 5 and 6. Figure 6a illustrates a conventional arrangement of a pixel buffer and a Z buffer in dynamic RAM. A drawing application implemented on the drawing engine 180 stores data in a pixel buffer 200 at the top of the DRAM and a corresponding Z buffer 202 offset below the pixel buffer 200. For the convenience of this explanation, the Z buffer is shown to have an offset of 1k rows below the pixel buffer 200. However, other offsets could equally be envisaged.

The DRAM has 2k rows and 2k columns. In that way, each entry in the DRAM can be addressed by a 22 bit word.

Conveniently, the DRAM is provided with 11 address pins, and the row and column parts of that 22 bit word are input into the DRAM device sequentially.

Figure 6b illustrates the actual allocation of memory within the memory 154, once the memory controller has transformed the memory allocation made by the drawing engine 180. In the present example, a relatively straightforward cross connection in the wiring between the drawing engine.180 and the memory controller 182 can be implemented. The most significant bit of the row address output by the drawing engine is crossed to the most significant bit of the column part of the address received by the memory controller 182. The remainder of the row address output by the drawing engine, together with the most significant bit of the column part of the address output by the drawing engine are shifted left by one. This is illustrated in Figure 5.

The act of shifting all but the most significant bit of the row part of the address by one is to place all of the rows occupied by the pixel buffer into even numbered rows. Then, moving the most significant bits of the column part of the address into the least significant bit of the row part of the address shifts the second half of each row of the pixel buffer into the first half of each of the odd numbered rows left unoccupied by the previous step. The effect on the Z buffer is similar. Shifting the row part of the address left by one means that the most significant bit of the row address (set to one for the Z buffer) is discarded. This immediately sends the rows of the Z buffer towards the top of the memory. The most significant bit of the row part of the address (set to one) is moved to the now unoccupied most significant bit of the column address. This shifts all of the half rows into the second half of each of the rows created in the memory arrangement illustrated in Figure 6b.

It will be appreciated that this arrangement is specific 11 to an offset of lk rows, where it can be identified with ease that an address called by the drawing engine 180 refers to the pixel buffer or the Z buffer. However, the offset between the pixel buffer and the Z buffer does not need to be a round number such as 1k. Other offsets could be identified, isolated and used in conversion of addresses with the use of logic gates.

Although the interconnection 184 shown in Figure 4 is shown as a hard wired arrangement between the drawing engine 180 and the memory controller 182, this arrangement may or may not be integrated within an integrated circuit combining the two units within an overall graphics controller 152. In that way, it will be appreciated that the interconnection could be considered to be a part of the memory controller 182 itself. Alternatively, in a second specific embodiment of the invention, the procedure illustrated in Figures 7 and 8 could be implemented in the memory controller 182, without the need for hard -wired- cross -connection.

Figure 7 illustrates a procedure for reorganising memory without external devices having to be made aware of the reorganisation. In step S2, an address to be accessed by the memory controller is received from the drawing engine 180. In step S4, the address received by the memory controller is transformed. In step S6, the address transformed by the memory controller 182 is 12 accessed in the memory. The procedure then returns. The step S4 illustrated in Figure 7 is described in further detail with reference to Figure 8. Firstly, in step S10, a check is made as to whether the address to be 5 transformed is greater than or equal to a predetermined Z buffer offset. If so, this Z buffer offset is then subtracted from the address in step S12. A Z flag is then set in step S14. If this is not so, then a Z flag is cleared in step S15.

Thereafter, or if the inquiry made in step S10 is negative, the row part of the address is shifted left by one, in step S16. In step S18, the most significant bit of the column part of the address is moved to the least significant bit of the row part of the address. Then, the Z f lag (which may have been set by step S14) is placed in the most significant bit of the column address in step S20.

Figure 9 illustrates, in a third specific embodiment of the invention, a computer graphics console 200 as is commonly connected with a television 210 for recreational use. The console 200 is illustrated in Figure 9 connected with input devices 212, which can include joysticks, pointing devices and hand held devices including buttons and/or rocker switches. A read only memory device 214 is connected with the console 200, I comprising a cartridge, CD ROM or the like. This read only memory device can contain data relating to the performance of the game to be played on the console. A removable mass storage device 216 could also be provided, for instance in the form of a plug in cartridge, in order to allow for the storage of data relating to for instance game position, highest scores etc.

The console comprises a central processing unit 220 combined with a memory controller. The CPU 220 is coupled with a random access memory (RAM) 222, used for system processing. A combined graphics control ler/raster output/DAC unit 224 is also provided and coupled with the CPU 220. A video memory 226 is coupled with the combined unit 224.

In this case, the memory controller is embedded within the graphics controller 224. This is particularly common in the f ield of computer games consoles, where it is important to integrate the processing circuitry as far as possible to reduce weight and manufacturing costs.

However, embedded within the memory controller is an arrangement as illustrated in Figure 5, which provides for the conversion of addresses of the video memory 226 by the graphics controller 224 for itself and, if required, the CPU 220, to organise the pixel buffer and video buffer therein in accordance with Figure 6b.

14 In the two embodiments described above, it will be appreciated that the raster output unit (which reads from the video memory 154, 226) is also designed to read pixel addresses from the arrangement illustrated in Figure 6b. 5 For any given pixel, both the entry in the pixel buffer and the entry in the Z buffer will be placed on the same row in the arrangement illustrated in Figure 6b. This reduces the number of row accesses required to be made by the memory controller in accordance with a request for a reading and writing to the pixel and Z buffers. Previously, it had been necessary to read from a first row in the pixel buffer and then make a second reading from a row in the Z buffer in order to retrieve all of the information about a pixel. In the present arrangement, it is possible to read an entire row of a dynamic RAM and obtain combined information about a series of pixels.

In the event that the pixel buffer is larger than the Z buffer, for instance if the pixel buffer includes information concerning more accurate colour, then it may be necessary to change the arrangement illustrated in Figure 6b. For example, in Figure 10a, a DRAM is shown with an allocation consisting of a pixel buffer 200, and a Z buffer 2021, the pixel buffer 200, being three times the size of the Z buffer 2021. The Z buffer is offset 11i K rows below the pixel buffer 200f. Therefore, if the DRAM has 2 K rows, the pixel buffer can be allocated to the first 131 K rows and the Z buffer can be allocated the remaining: K rows. It will be appreciated that the 5 number of pixels for which information is stored in the DRAM illustrated in Figure 10a is lower than the number of pixels for which information is stored in the DRAM of Figure 6a.

In accordance with the invention, it would be desirable to place the Z buffer information relating to a series of pixels on the same row of memory as the corresponding pixel inf ormation. Therefore, an arrangement can be devised which places the Z buffer in the highest quarter of the columns of each row, as illustrated in Figure 10b. This can be identified by the two most significant bits of the column address being 1, which, for instance, can be implemented by the cross connection, from a drawing engine 180, to a memory controller 1821, illustrated in Figure 11. In this arrangement, the two most significant bits of the row part of the address are crossed down to the two most significant bits of the column part of the address, while the remaining bits of the row part of the address and the two most significant bits of the column address are shifted left by two. As illustrated in Figure 10, the pixel buffer 200' is three times the width of the Z buffer 202, in view of the extended colour 16 information contained within the pixel buffer.

In fact, the cross connection illustrated in Figure 11 will not on its own lead to the rearrangement of memory from the allocation shown in Figure 10a to the allocation in shown in Figure 10b. Instead, the DRAM will be divided into first, second, third and fourth sets of rows, the fourth of which contains the Z buffer. These rows are then transposed into four columns of equal widths, as illustrated in Figure 12. Clearly, this is undesirable, since it rearranges the pixel buffer so that pixel information existing on a particular row no longer corresponds to contiguous series of pixels. Moreover, pixel information and Z buffer information has become confused. Therefore, the drawing engine 180, must include further modules to achieve the allocation illustrated in Figure 10b. Such modules are illustrated in Figure 13 and Figure 14. Figure 13 shows a detail of the drawing engine 180, illustrated in Figure 11. The components of the drawing engine 180' that are illustrated in Figure 13 are those which are concerned with the addressing of memory; all other components are omitted for clarity. The drawing engine 180, includes a preconverter 220, and a tristate buffer 2221. A controller 224, enables one or other of the preconverter 220' and the tristate buffer 222' according to signals received from the address line. The structure of the 17 preconverter 220, is illustrated in further detail in Figure 14. The preconverter 2201 receives the 22 address lines (11 row address lines and 11 column address lines), which address lines have a cross connection applied to them which is the exact opposite of the cross connection later implemented between the drawing engine 1801 and the memory controller 1821. In contrast, the tristate buffer 222, includes no cross connection, and transmits the address lines therethrough without operating thereon.

In use, the controller 224, identifies whether an address receives along the address line is for an address of the pixel buffer or of the Z buffer. If the address is of the pixel buffer, then the preconverter 220, is enabled.

In that way, the address is preconverted before transmission to the memory controller 1821, so that the two cross connections can see each other out. In that way, it is possible to avoid the pixel buffer becoming fragmented and columnar in form. In contrast, when the controller 224, identifies that an address refers to a position in the Z buffer, the tristate buffer 222, is enabled. In that way, the actual address is transferred straight through to the memory controller 1821, for conversion into an address form illustrated in Figure 10b.

It will be appreciated that in some circumstances, the 18 memory map established by the graphics application in use on the computer may place the Z buffer before the pixel buffer in memory, and/or the memory controller may place the Z buffer in the left hand column of the transformed memory. Logic to perform this operation can be devised using cross connections such as those illustrated in Figures 5 and 11, or alternatively by means of software operations on incoming address requests to the memory controller, similar to the operation described in Figures 10 7 and 8.

19

Claims

CLAIMS:

1. A graphics controller, comprising:

memory means including a plurality of rows each including a plurality of storage locations; memory control means for configuring said memory means to store a frame buffer and a corresponding Z buffer; characterised in that:

said memory control means is operable to configure the memory means such that each row of the memory means on which a portion of the frame buffer is stored also has a corresponding portion of the Z buffer stored therein.

2. A graphics controller in accordance with claim 1 wherein said memory control means is operable to configure the memory means such that each said row has first and second contiguous regions defined therein, the portion of the frame buffer being stored in the first region and the portion of the Z buffer being stored in the second region.

3. A graphics controller in accordance with claim 1 or claim 2 further comprising:

address decoding means, operable to receive a request for address to a storage location of the memory means, and to translate said address request to account for the allocation of frame buffer and Z buffer on the same rows in the memory means.

4. A graphics controller in accordance with claim 3 wherein said address decoding means is operable to translate an address for a memory means arranged with first and second contiguous regions for a frame buffer and a Z buffer respectively, into an address for the configuration of the memory means established by the memory control means.

5. A graphics controller in accordance with claim 4 comprising address carriers for carrying signals defining an address, the address decoding means comprising at least one transposition of at least one of said address carriers.

6. In a graphics controller including a memory including a plurality of rows including a plurality of storage locations, a method of configuring the memory comprising the steps of:

defining a frame buffer for the storage of rasterised data; defining a buffer for the storage of data corresponding with the rasterised data; characterised in that: each row of the memory that has a portion of the 21 frame buffer defined therein also has a corresponding portion of the Z buffer defined therein.

7. A method in accordance with claim 6 wherein each said row is configured into first and second contiguous regions, the first region having said portion of the f rame buf f er def ined therein and the second region having said portion of the Z buffer defined therein.

8. A method in accordance with claim 6 or claim 7 and further including the steps of:

receiving a request for an address to a storage location; and translating said request to account for allocation of f rame buf f er and Z buf f er on the same row of the memory.

9. A method in accordance with claim 8 wherein said step of translating includes performing an operation on said address so as to transform an arrangement of memory having separate and contiguous frame and Z buffers into the configuration of the memory established by the memory control means.

10. A storage apparatus for a computer graphics system, the storage apparatus comprising:

a plurality of rows comprising a plurality of 22 storage locations; the storage apparatus having defined therein a frame buffer and a Z buffer; characterised in that:

each row of the storage apparatus that has a storage location assigned to a part of the frame buffer has a further storage location assigned to a corresponding part of the Z buffer.

11. A computer apparatus comprising a processor operable under the control of computer implementable instruction and data storage means for the storage of data representative of a graphical output, wherein the data storage means comprises an array of rows of storage locations, each row being configured for storage of data representative of pixel data, and wherein each row comprises a first part for storage of data representative of pixel information for a plurality of pixels and a second part for storage of data representative of corresponding depth information for said pixels.

11. A storage apparatus in accordance with claim 10 wherein each said row includes first and second contiguous portions, the first portion being assigned to a part of the f rame buf f er and a second portion being assigned to a part of the Z buffer.

12. A storage medium carrying computer implementable instructions operable to configure a computer graphics controller in accordance with any one of claims 1 to 5.

13. A storage medium carrying computer implementable instructions operable to configure a computer graphics controller to perform a method according to any one of claims 6 to 9.

14. A computer apparatus comprising a processor operable under the control of computer impiementable instruction and data storage means for the storage of data 23 representative of a graphical output, wherein the data storage means is configured with a plurality of contiguous portions, each portion being configured for storage of data representative of pixel data for at least one pixel of a graphical output and corresponding data representative of depth for that at least one pixel.

15. A computer apparatus in accordance with claim 14 wherein the data storage means is an array, and each said portion of the data storage means comprises a row of said array.

16. A computer apparatus in accordance with claim 15 wherein each row comprises a first part for storage of data representative of pixel information and A second part for storage of data representative of depth information.

Amendments to the claims have been filed as follows 1. A graphics controller, comprising:

said memory control means is operable to configure the memory means such that each row of the memory means on which a portion of the frame buffer is stored has first and second contiguous regions defined therein, said portion of the frame buffer being stored in the first region and a corresponding portion of the Z buffer being stored in the second region.

2. A graphics controller in accordance with claim 1 further comprising:

address decoding means, operable to receive a request for address to a storage location of the memory zS. means, and to translate said address request to account for the allocation of frame buffer and Z buffer on the same rows in the memory means.

3. A graphics controller in accordance with claim 2 wherein said address decoding means is operable to translate an address for a memory means arranged with first and second contiguous regions for a frame buffer and a Z buffer respectively, into an address for the configuration of the memory means established by the memory control means.

too 0000 4. A graphics controller in accordance with claim 3 a.

too comprising address carriers for carrying signals defining an address, the address decoding means comprising at least one transposition of at least one of said address carriers.

5. In a graphics controller including a memory including a plurality of rows including a plurality of storage locations, a method of configuring the memory comprising the steps of:

defining a frame buffer for the storage of rasterised data; defining a Z buffer for the storage of data corresponding with the rasterised data; characterised by:

configuring each row of the memory that has a portion of the frame buffer defined therein into first and second contiguous regions, the first region having said portion of the frame buffer defined therein and the second region having a corresponding portion of the Z buffer defined therein. 6. A method in accordance with claim 5 and further including the steps of: 15 receiving a request for an address to a storage location; and translating said request to account for allocation of frame buffer and Z buffer on the same row of the memory. 20 7. A method in accordance with claim 6 wherein said step of translating includes performing an operation on said address so as to transform an arrangement of memory having separate frame and Z buffers into the configuration of the memory established by the memory control means. 5 8. A storage apparatus for a computer graphics system, the storage apparatus comprising: a plurality of rows comprising a plurality of storage locations; the storage apparatus having defined therein a frame buffer and a Z buffer; characterised in that: each row of the storage apparatus that has a storage location assigned to a part of the frame buffer includes first and second contiguous portions, the first portion being assigned to a part of the frame buffer and a second portion being assigned to a corresponding part of the Z buffer.

9. A storage medium carrying computer implementable instructions operable to configure a computer graphics controller in accordance with any one of claims 1 to 4.

ZB.

A storage medium carrying computer implementable instructions operable to configure a computer graphics controller to perform a method according to any one of claims 5 to 7.