GB2336714A - Method of fabricating a capacitor for a DRAM - Google Patents
Method of fabricating a capacitor for a DRAM Download PDFInfo
- Publication number
- GB2336714A GB2336714A GB9805951A GB9805951A GB2336714A GB 2336714 A GB2336714 A GB 2336714A GB 9805951 A GB9805951 A GB 9805951A GB 9805951 A GB9805951 A GB 9805951A GB 2336714 A GB2336714 A GB 2336714A
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- Prior art keywords
- layer
- silicon
- oxide layer
- poly
- oxide
- Prior art date
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Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 75
- 239000000758 substrate Substances 0.000 claims abstract description 44
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 42
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 42
- 238000009413 insulation Methods 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 18
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 238000005498 polishing Methods 0.000 claims abstract description 7
- 150000004767 nitrides Chemical class 0.000 claims abstract description 3
- 238000000034 method Methods 0.000 claims description 27
- 239000004065 semiconductor Substances 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims 5
- 238000000059 patterning Methods 0.000 claims 4
- 241000334160 Isatis Species 0.000 claims 1
- NTHWMYGWWRZVTN-UHFFFAOYSA-N sodium silicate Chemical compound [Na+].[Na+].[O-][Si]([O-])=O NTHWMYGWWRZVTN-UHFFFAOYSA-N 0.000 claims 1
- 238000000206 photolithography Methods 0.000 abstract description 8
- 230000004048 modification Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
To form a capacitor for a DRAM using only one photolithography step, an oxide layer 101, a silicon nitride layer 102, a oxide layer 103 ad a polysilicon layer 104 are formed on a silicon substrate 100 having an MOS. An opening 111 is then formed in the layers 103 and 104 by photolithography and etching using the layer 102 as an etching stop. An oxide layer 106 is then deposited and etched to form an opening 112 within the first opening, the second opening being extended down to the substrate using the remaining layers 104, 106 as a mask. A further polysilicon layer 107 is then deposited to cover the polysilicon layer 104 and the walls of the opening 111 and filling the opening 112, followed by another oxide layer (108). After chemical-mechanical polishing, the remainder of the oxide layers 103, (108) are removed by etching, and an insulation film 109 and a further polysilicon layer 110 are deposited to complete the capacitor. In a modification, the opening 111 is formed in the nitride layer 102 and part of the oxide layer 101 as well as the layers 103, 104.
Description
1 9 1 3 2336714 1 METHOD OF FABRICATING CAPACITOR
BACKGROUND OF THE RTNTION
Field of the Invention
The invention relates to a method of fabricating a dynamic random access memory (DRAlvf), and more particularly to a method of fabricating a capacitor in a DR.AM.
Description of the Related Art
Modem semiconductor fabrication technique in an ultra large scale integration (ULSI) highly increases the circuit density on a chip. The increase of circuit density causes the downsizing of devices and the increase of device packing density. Recently, enhanced resolution of photolithography technique, the development of anisotropic plasma etching and other improvements of semiconductor fabrication have all been advantageous to device downsizin. However, in order to develop towards a further 9 higher circuit density, some breakthrough is required for semiconductor fabrication.
DRAM is a device broadly used mi electronic industry for data storage due to the characteristic of increased circuit density in an integrated circuit (IC). The stored information or message is determined by the charges stored in an internal capacitor of a memory cell. The access of data is performed by operating the read/write circuit and the peripheral memory in a chip. A single DRAM memory cell comprises a field effect transistor (FET) and a capacitor as a bit for representing a binary data.
As the number of transistors in a DRAM greatly increases, the dimension of the transistors reduces. Thus, during storing charges, a acceptable signal-to-noise (SIN) 0 1 1 1 2 ratio is difficult to maintain. By decreasing the charges in a capacitor to enhance the SIN ratio, the refresh cycles for storing charges is correspondingly increased.
Being restricted by the limited available surface asea of a capacitor in a memory cell, to supply sufflicient capacitance to the chip without increasing the occupied space on the substrate, a special and efFective capacitor structure is needed to meet the requirement of semiconductor fabrication. As example, a trench capacitor, a cylinder capacitor, and a stack capacitor have been developed and used. However, due to the high complexiry of fabrication, the trench capacitor is not as common as the cylinder capacitor and the stack capacitor. The disadvantages of these structures are the complex process and the io high cost of fabrication.
In Fig. 3 a to Fig. 3 a, a conventional method of fabricating a cylinder capacitor in a DRAM is shown.
Referring to Fig. 3a, on a silicon substrate 300 having a metal-ox:ide semiconductor (MOS) formed thereon, an oxide layer 301 and a silicon nitride layer 302 are formed in sequence. The silicon nitride layer '302 is used as an etch stop in the subsequent etching process.
In Fig. 3b, using photolithography and etching, the silicon nitride layer 302 and the oxide layer 301 are patterned to form an opening 309, so that the silicon substrate 300 is exposed within the opening 309, for example, a doped region in the MOS is exposed.
A poly-silicon layer 303 is formed on silicon nitride layer 302 and fills the opening 309.
In Fig. 3c, the poly-silicon layer 303 is etched back until the surface of the poly silicon layer and the surface of the silicon nitride layer J02 are at a same level.
In Fig. 3d, an oxide layer 304 is formed over the substrate 300. Using photolithography and etching, the oxide layer 3 04 is patterned to form an opening 3 10, so 0 3 that the poly-silicon layer 3 03 within the opening 3 10 and a part of the surface of the silicon nitride layer 302 are exposed. A poly-silicon layer 305 is formed to cover the opening 33 10 and the oxide layer J3 04, and thus, the poly-silicon layer 3 03 and the poly sUicon layer 305 are electrically connected. An oxide layer 306 is formed on the poly silicon 305.
In Fig. 3e, the oxide layer ^106 is etched back with the poly-silicon layer 305 as an etch stop. The poly-silicon layer 305 is etched back with the oxide layer 304 as an etch stop.
In Fig. ^if, the remaining oxide layer 306 and the remaining oxide layer 304 are io removed by wet etching with the sdicon nitride layer 302 as an etch stop.
In Fig. 3g, an insulation layer 307, for example, an oxidelffitrideloxide (ONO) layer, is formed over the substrate 300. A poly-sdicon layer 308 is formed on the insulation layer 307. The fabrication of a conventional cylinder capacitor in a DRAIM is formed.
In the above method, two photolithography and etching processes are used, so that two photo-masks are required. Thus, the possibility of misalignment is increased, the process is more complex, and the cost of fabrication is high.
SUNC4ARY OF THE INVENTION It is therefore an object of the invention to provide a method of fabricating a capacitor. Using the contact window of the electrode node for self- alignment, only one 0 photolithography and etching process is necessary to perform. The process is simplified and the cost of fabrication is reduced.
It is therefore another object of the invention to provide a method of fabricating a 1 4 capacitor in a DRAM. The surface of area is increased by using only one photo-mask.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of fabricating a capacitor. On a semiconductor substrate having a metal oxide-semiconductor, a first oxide layer, a silicon nitride layer, a second oxide layer and a first poly-silicon layer are formed in sequence. The first poly-stlicon layer and the second oxide layer to are patterned form a first opening, so that the silicon nitride layer is exposed within the first opening. A third oxide layer is formed over the substrate. The third oxide layer is etched with the silicon nitride layer as an etch stop. The silicon nitride layer is etched to form a second opening until exposing the first oxide layer by using the remaining third oxide layer and the first poly-silicon layer as masks. The second opening is deepened until the substrate is exposed by etching the first oxide layer.
A second poly-silicon layer is formed to cover the first poly-sillcon layer and the first opening, and to 5.11 the second opening. A fourth oxide layer is formed on the second poly-silicon layer. The fourth oxide layer, the second poly-silicon layer, and the first poly-silicon layer are removed by chemical-mechanical polishing until the second oxide layer is exposed. The remaining fourth oxide layer and the second oxide layer are wet etched with the silicon nitride layer as an etch stop. An insulation layer is formed over the silicon substrate, and a third poly-silicon layer is formed on the insulation layer.
To achieve the above objects and advantages, and in accordance V4ith the purpose of the invention, another method of fabricating a capacitor is proposed. On a semiconductor substrate having a rnetal-oxide-semiconductor, a first oxide layer, a silicon nitride layer, a second oxide layer, and a first poly-silicon layer are formed in sequence.
The first poly-silicon layer, the second oxide layer, and the silicon nitride layer are etched to form a first opening, so that the first oxide layer is exposed within the first opening A third oxide layer is formed over the substrate. The third oxide layer and the first oxide layer are etched until the substrate is exposed. A second poly-silicon layer is formed over the substrate. A fourth oxide layer is formed. The second opening is deepened by etching the first oxide [aver until the substrate is exposed. A second poly-silicon layer is formed to cover the first poly-silicon layer and the Erst opening, and to fill the second opening. A fourth oxide layer is formed on the second poly-sdicon layer. The fourth oxide layer, the second poly-sfllcon layer, and the first poly-silicon layer are removed by chenuical-mechanical pofishing until the second oxide layer is exposed. The remaining io fourth oxide layer and the second oxide layer are wet etched with the silicon nitride layer as an etch stop. An insulation layer is formed over the silicon substrate. A third poly silicon layer is formed on the insulation layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure la to Figure I. are cross sectional views of the process for fabricatig a capacitor in a DRAM in a preferred embodiment according to the invention, Figure 2a to Figure 2f are cross sectional views of the process for fabricating a capacitor in a DRAM in another preferred embodiment according to the invention; Figure 3a to Figure 3)a are cross sectional views of the conventional process for 0 fabricating a cylinder capacitor.
6 DESCRIPTION OF THE PREFERRED E'ilvMODLvENTS
Fig. 1 a to Fig. 1 a show the cross sectional views of the process fabricating a capacitor in a preferred embodiment.
In Fig. la, a first oxide layer 101, a silicon nitride layer 102, a second oxide layer 103-7, and a first poly-silicon layer are 104 formed on a silicon substrate 100 on which an MOS is formed in sequence. A photo-resist layer 105 is formed and patterned on the first poly-silicon layer 104.
Referring Fig. lb, the first poly-silicon layer 104 and the second oxide layer 103 are etched to form a first opening 111 with the silicon nitride layer 102 as an etch stop.
io The photo-resist layer 105 is removed. A third oxide layer 106 is formed over the substrate 100.
Referring to Fig. I c, the third oxide layer 106 is etched to form a second ope ='a 112 within the first opening 111 with the silicon nitride layer 102 as an etch stop.
Referring to Fig. ld, using the etched third oxide layer 106 and the first poly silicon layer 104 as masks, the silicon nitride layer 102 and the first oxide layer 101 are etched to deepen the second opening 112 and to expose the substrate 100, for example, the. exposed doped region of the MOS.
Referring to Fig. le, a second poly-silicon layer 107 is formed over the substrate 100 to cover the first poly-silicon layer 104 and the first opening 111, and fills the second opening 112. A fourth oxide layer 108 is formed on the second poly-silicon layer 107.
Referring to Fig. if, using chemical-mechanical polishing (Ci'VT), the fourth oxide layer 108, the second poly-silicon layer 107, and the first poly-silicon layer 104 are removed to expose the second oxide layer 103.
Referring to Fig. lg, using wet etching, the remaining fourth oxide layer 108 and 7 the remaining second oxide layer 103) are removed with the silicon nitride layer 102 as an etch stop. An insulation layer 109, for example, an ONO layer, is formed over the substrate 100. A third poly-silicon layer 110 is formed on the insulation layer 109 to complete the formation of a capacitor.
Another embodiment of the method of fabricating a capacitor is shown as Figure 2a to Figure 2f Referring to Fig. 2a, a first oxide layer 201, a silicon nitride layer 202, a second oxide layer 203, and a first poly-silicon layer 204 are formed on a silicon substrate 200 on which an MOS is formed in sequence. A photo-resist layer 205 is formed and patterned lo on the first poly- silicon layer 204.
Referring Fig. 2b, the first poly-silicon layer 204, the second oxide layer 203, and the silicon nitride layer 202 are etched to form a first opening 211 with the first siEcon oxide layer 201 as an etch stop. The photo-resist layer 205 is removed. A third oxide layer 206 is formed over the substrate 200 and Efis the opening 211.
Referring to Fig. 2c, the third oxide layer 206 and the first oxide layer 201 are etched to form a second opening 212 within the first opening 211 until exposing the substrate 200, for example, exposing the doped region of the MOS.
Referring to Fig. 2d, forming a second poly-silicon layer 207 over the substrate 200 and the first opening 211, and fills the second opening 212. A fourth oxide layer 208 is formed on the second poly-silicon layer 207.
Referring to F1g. 2e, using CNT, the fourth oxide layer 208, the second polysilicon layer 207, and the first poly-silicon layer 204 are removed until the second oxide layer 203) iS exposed.
Referring to Fig. 2f, using wet etching, the remainincr fourth oxide layer 208 and 1 1 8 the remaining second oxide layer 203 are removed with the silicon nitride layer 202 as an etch stop. An insulation layer 209, for example, an ONO layer, is formed over the substrate 200. A third poly-silicon layer 210 is formed on the Insulation layer to complete the formation of a capacitor.
In the first embodiment, the bottom electrode covers a part of the surface of the s itride layer. Whereas, in the second embodi 11 1 1 fu 1 iment, a part of the silicon nitride layer is removed, and the bottom electrodes further occupies the space which was occupied by the part of the the silicon nitride before being removed. Therefore, the surface area of the bottom electrode of a capacitor is even larger in the second io embodiment.
A capacitor fabricated by a process according to the invention has the fodowing advantages as foflows:
1. The node contact window of a bottom electrode in a capacitor is selfaligned, and only one photolithography process is required. Therefore, the misalignment is eliminated, and the cost is reduced.
2. The surface area of the capacitor is increased, thus, the capacitance of the DRAM is increased.
Other embodiment of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.
9
Claims (1)
- CLAIMS:1. A method of fabricating a capacitor, wherein a semiconductor substrate 0 having a metal-oxide-semicoriductor is provided, comprising:forming a first oxide layer, a silicon nitride layer, a second oxide layer, and a first poly-silicon layer on the substrate in sequence; patterning the first poly-silicon layer and the second oxide layer to form a first opening, so that the silicon nitride layer within the first opening is exposed; forming a third oxide layer over the substrate; etching the third oxide layer with the silicon nitride layer as an etch stop; etching the silicon nitride layer to form a second opidna the first oxide layer is exposed, using the remaining third oxide layer and the first poly-silicon layer as masks; deepening the second opening by etching the first oxide layer until the substrate is exposed; forming a second poly-sificon layer to cover the first poly-silicon layer and the first opening, and to fill the second opening; forming a fourth oxide layer on the second poly-silicon layer; removiner the fourth oxide layer, the second poly-siEcon layer, and the first polysilicon layer until the second oxide layer is exposed, wet etching the remaining fourth oxide layer and the second oxide layer with the silicon nitride layer as an etch stop; forming an insulation layer over the silicon substrate; and forrrin. a third poly-silicon layer on the insulation layer.0 2. The method according to claim 1, wherein the second opening exposes a doped region of the metal-oxide-semiconductor.1 The method according to cl im 1, wherein the insulation layer ' ludes a 1 ai 1 1 inc silicon oxidelsilicon rutridelsilicon oxide layer.4. The method according to claim 1, wherein the fourth oxide layer, the second poly-silicon layer, and the first poly-silicon layer are removed by chemical-mechanical polishing.5. A method of fabricating a capacitor, wherein a semiconductor Substrate having a metal-oxide-semiconductor is provided, comprising- forming a first oxide layer, a silicon nitride layer, a second oxide layer, and a first poly-silicon layer on the substrate in sequence; patterning the first poly-sfficon layer, the second oxide layer, and the silicon 15 nitride layer to form a first opening, so that the first oxide layer within the first opening i is exposed; forming a third oxide layer over the substrate; etching the third oxide layer and the first oxide layer to form a second opening to expose the substrate; forming a second poly-silicon layer over the substrate., formina a fourth oxide layer on the second poly-silicon layer; 0 removing the fourth oxide layer, the second poly-silicon layer, and the first polysilicon layer until the second oxide layer is exposed; wet etching the remaining fourth oxide layer and the second oxide layer with the 1 11 silicon nitride layer as an etch stop; forming an insulation layer over the silicon substrate; and forming a third poly-silicon layer on the insulation layer.6, The method according to claim 5, wherein the second opening exposes a 0 0 doped region of the metal-oxide-semiconductor.7. The method according to claim 5, wherein insulation layer includes a silicon oxidelsilicon aitride/silicon oxide layer.8. The method according to claim 5, wherein the fourth oxide layer, the second poly-silicon layer, and the first poly-silicon layer are removed by chemical-mechanical polishing.9. A method of fabricating a capacitor, substantially as hereinbefore described and/or substantially as illustrated in any one of or any combination of Figs la to 2f of the accompanying drawings.i 111 Amendments to the claims have been fled as follows 1. A method of fabricating a capacitor, wherein a semiconductor substme having a metal-oxide-semiconductor is provided, comprising:forming a Em oxide layer, a silicon nitride layer, a second oxide layer, and a EM 5 poly-silicon layer on the substrare in sequence; patterning the Em poly-sificon layer and the second oxide layer to form a EM opening, so that the silicon nitride layer within the first opening is exposed; forming a third oxide layer over the substraze; etching the third oxide layer wfth the silicon nitride layer as an etch stop; etching the silicon nitride layer to form a second opening until the first oxide layer is exposed, using the remaining third oxide layer and the first poly-silicon lay r as masks, deepening the second opening by etching the first oxide layer until the substrate is exposed; forming a second poty-silicon layer to cover the EM POLY-sicon layer and te15 5= openiM and to fal the second opening forming a fourth oxide layer on the second poly-silican layer, removing the fourth oxide layer, the second poly-silicon layer, and the 5= polysilicon layer until the second oxide layer is exposed, wet etching the remaining fourth oxide layer and the woad oxide layer with the silicon nitride layer as an etch stop; forming an insulation layer over the silicon subs=e; and forming a third poly-silicon layer on the insulation layer.2. The method acccrding to claim 1, wherein the sec6nd openffig oToses a t- doped region of the metal-oxide-semiconductor.3. The method according to claim 1 or 2, wherein the insulation layer includes a silicon oxide/silicon nitride/silicon oxide layer.4. The method according to any preceding claim, wherein the fourth oxide layer, the second poly-silicon layer, and the first poly-silicon layer are removed by chemical-mechanical polishing.5. A method of fabricating a capacitor, wherein a semiconductor substratt; having a metal-oxide-semiconductor is provided, comprising:forming a first oxide layer, a silicon nitride layer, a second oxide layer, and a first poly-sificon layer on the substrate in sequence; patterning the first poly-sifican layer, the second oxide layer, and the silicon nitride layer to form a first opening so that the first oxide layer within the first opening Lis 0) exposed; forming a third oxide layer over the substrate; etching the third oxide layer and the first oxide layer to form a second opening to expose the substrate; forming a second poly-silicon layer over the substrate to cover the first poly- silicon layer and the first opening, and to fill the second opening; t.- forming a fourth oxide layer on the second poly-sificon layer-, removing the fourth oxide layer, the second poly-silicon layer, and the first poly- silicon layer until the second oxide layer is exposed; wet etching the remaining fourth oxide layer and the second oxide layer with the silicon nitride layer as an etch stop; forming an insulation layer over the silicon substrate; and forming a third poly-sificon layer on the insulation layer.0 6. The method according to claim 5, wherein the second opening exposes a 10.doped region of the nietal-odde-semiconductor.7. The method according to claim 5 or 6, wherein insulation layer includes a silicon oxide/silicon nitride/silicon oxide layer.8. The method according to any of claims 5 to 7, wherein the fourth oxide layer, the second poly-silicon layer, and the first poly-silicon layer are removed by chemical-mechanical polishing.C 9. A method of fabricating a capacitor, substantially as hereinbefore described and/or substantially as illustrated in Figs. la to lg or 2a to 2f.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB9805951A GB2336714B (en) | 1997-12-24 | 1998-03-19 | Method of fabricating capacitor |
| NL1008802A NL1008802C2 (en) | 1997-12-24 | 1998-04-03 | Method of manufacturing a capacitor. |
| DE19815158A DE19815158A1 (en) | 1997-12-24 | 1998-04-03 | Production of DRAM capacitor having increased surface area |
| FR9804376A FR2772988B1 (en) | 1997-12-24 | 1998-04-08 | METHOD FOR MANUFACTURING A CAPACITOR IN A DYNAMIC RAM |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW086119673A TW427014B (en) | 1997-12-24 | 1997-12-24 | The manufacturing method of the capacitors of DRAM |
| GB9805951A GB2336714B (en) | 1997-12-24 | 1998-03-19 | Method of fabricating capacitor |
| NL1008802A NL1008802C2 (en) | 1997-12-24 | 1998-04-03 | Method of manufacturing a capacitor. |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9805951D0 GB9805951D0 (en) | 1998-05-20 |
| GB2336714A true GB2336714A (en) | 1999-10-27 |
| GB2336714B GB2336714B (en) | 2000-03-08 |
Family
ID=27269250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9805951A Expired - Fee Related GB2336714B (en) | 1997-12-24 | 1998-03-19 | Method of fabricating capacitor |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE19815158A1 (en) |
| FR (1) | FR2772988B1 (en) |
| GB (1) | GB2336714B (en) |
| NL (1) | NL1008802C2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11330397A (en) * | 1998-05-20 | 1999-11-30 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444653A (en) * | 1993-04-26 | 1995-08-22 | Sanyo Electric Co., Ltd. | Semiconductor memory device with stack type memory cell |
| US5478768A (en) * | 1992-08-03 | 1995-12-26 | Nec Corporation | Method of manufacturing a semiconductor memory device having improved hold characteristic of a storage capacitor |
| US5482886A (en) * | 1993-08-30 | 1996-01-09 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating dynamic random access memory capacitor |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1245495B (en) * | 1990-01-26 | 1994-09-27 | Mitsubishi Electric Corp | DYNAMIC RANDOM ACCESS MEMORY HAVING A STACKED TYPE CAPACITOR AND ITS MANUFACTURING PROCEDURE |
| US5484744A (en) * | 1995-04-14 | 1996-01-16 | United Microelectronics Corporation | Method for fabricating a stacked capacitor for dynamic random access memory cell |
| JPH0964179A (en) * | 1995-08-25 | 1997-03-07 | Mitsubishi Electric Corp | Semiconductor device and its fabrication method |
| KR0186069B1 (en) * | 1995-12-28 | 1999-03-20 | 문정환 | Method of manufacturing capacitor of stacked dram cell |
| US5552334A (en) * | 1996-01-22 | 1996-09-03 | Vanguard International Semiconductor Company | Method for fabricating a Y-shaped capacitor in a DRAM cell |
-
1998
- 1998-03-19 GB GB9805951A patent/GB2336714B/en not_active Expired - Fee Related
- 1998-04-03 NL NL1008802A patent/NL1008802C2/en not_active IP Right Cessation
- 1998-04-03 DE DE19815158A patent/DE19815158A1/en not_active Ceased
- 1998-04-08 FR FR9804376A patent/FR2772988B1/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478768A (en) * | 1992-08-03 | 1995-12-26 | Nec Corporation | Method of manufacturing a semiconductor memory device having improved hold characteristic of a storage capacitor |
| US5444653A (en) * | 1993-04-26 | 1995-08-22 | Sanyo Electric Co., Ltd. | Semiconductor memory device with stack type memory cell |
| US5482886A (en) * | 1993-08-30 | 1996-01-09 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating dynamic random access memory capacitor |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2772988B1 (en) | 2001-05-25 |
| FR2772988A1 (en) | 1999-06-25 |
| GB2336714B (en) | 2000-03-08 |
| GB9805951D0 (en) | 1998-05-20 |
| DE19815158A1 (en) | 1999-07-08 |
| NL1008802C2 (en) | 1999-10-05 |
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| 732E | Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977) | ||
| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 20040319 |