GB2336468A

GB2336468A - Method for fabricating a ferroelectric memory device

Info

Publication number: GB2336468A
Application number: GB9904592A
Authority: GB
Inventors: Soo-Ho Shin; Yoo-Sang Hwang
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1998-04-18
Filing date: 1999-02-26
Publication date: 1999-10-20
Also published as: KR100292942B1; GB9904592D0; KR19990080563A

Abstract

In a method for fabricating a ferroelectric memory device having a capacitor 14 including ferroelectric film 109, to prevent degrading ferroelectric characteristics interlayer dielectric layer 118 of multi-layer structure is formed over the capacitor. The multi-layer structure includes a first layer 116, e.g. of ECR or FECVD oxide, exhibiting low stress characteristics and a second layer 117, e.g. of USG or PSG, exhibiting good step coverage. The layers 116, 117 may be provided in either order. There may also be a titanium dioxide barrier layer 114.

Description

2336468 METHOD FOR FABRICATING A FERROELECTRIC MEMORY DEVICE The present

invention relates to a ferroelectric memory device, and more particularly to a method for fabricating a ferroelectric capacitor which can prevent degrading ferroelectric characteristics.

Modern data processing systems require that a substantial portion of the information stored in its memory be randomly accessible to ensure rapid access to such information. Due to the high speed operation of memories implemented in semiconductor technologies. ferroelectric random access memories(FRAMs) have been developed and FRAMs exhibit significant advantage of being nonvolatile which is achieved by virtue of the fact that a ferroelectric capacitor includes a pair of capacitor plates with a ferroelectric material between them which has two different stable polarization states which can be defined with a hysteresis loop depicted by plotting the polarization against applied voltage.

In ferroelectric memory fabrication, one of the key processes is cover- fl lm(interl ayer dielectric) formation of capacitor without any degradation of ferroelectric characteristics. The interlayer dielectric, basically SiO, layer, is obtained by a variety of techniques. Selecting among theses techniques is very important to accomplish the interlayer dielectric formation process. Well-known problem in dielectric formation process is stress applied to the ferroelectric film of a capacitor which- causes lifting between the ferroelectric film and the capacitor electrodes.

Fig. 1 illustrates a conventional ferroelectric memory device in crosssection. A conventional method for fabricating a fenDelectric memory device will be briefly described with reference to Fig. 1. A device isolation layer 4 is formed on a semiconductor substrate 2 to define active and inactive regions thereon. A gate electrode 6 is formed over the 1 semiconductor substrate 2 disposing a gate oxide layer 5 therebetween. A diffusion laver(i.e.. source/drain region) is formed by a conventional Ion implanting technique. A first insulating]aver 8 is formed over the semiconductor substrate 2 including the gate electrode 6. A ferroelectric capacitor 14 is formed on the second insulating layer 8. The ferroelectric capacitor 14 includes a lower electrode 10, a ferroelectric film 11, and an upper electrode 1.1 The electrodes 10 and 12 are generally formed of platinum(Pt). A reaction barrier layer 16 such as TiO, is formed to cover the capacitor 14. The reaction barrier layer 16 serves to prevent the ferroelectric film 11 from reacting with surrounding materials in subsequent process. 10 An interlayer dielectric 18 is deposited over the entire semiconductor substrate 2. Contact holes 19a and 19b are opened in this interlayer dielectric 18 which reach to the lower electrode 10 and the diffusion layer respectively. Subsequently metal is deposited and patterned to form metal interconnection. As described previously, the deposition of the interlayer dielectric 18 over the 15 capacitor greatly affects the ferroelectric characteristics depending on which kind of oxide layer is deposited. Especially, the stress caused by the interlayer dielectric is applied to underlying capacitor and severely degrading the ferroelectric characteristics. ECR(electron cyclotron resonance) technique is used to minimize the stress applied to the capacitor. because the ECR technique can grow oxide layer at low temperature. However, the oxide 20 layer grows concurrently with a predetermined crystal orientation over the capping]aver and has a poor step coverage as shown in Fig.2, which allow wet etchant chemical to infiltrate into the low temperature ECR-oxide layer and thereby breaking down the ferroelectric film. This eventually reduces remnant polarization and increases current leakage.

The present invention was made in view of the above problem, and it is therefore an object of the invention to provide a method for fabricating a ferroelectric memory device which can prevent degradation of ferroelectric characteristics.

2 It is another object of the invention to provide a method for fabricating a ferroelectric memory device which can prevent wet etchant chemicals from infiltrating into the interlayer dielectric layer.

It is yet another object of the invention to provide a ferroelectric capacitor having a high reliability.

A key feature of the invention is forming multi-layer interlayer dielectric layer over the capacitorby laminating a layer exhibiting low stress characteristics and a layerexhibiting good step coverage in this order. Alternatively, the multi-layer interlayer dielectric layer may be formed by laminating a layer exhibiting good step coverage and a layer exhibiting low stress characteristics. The layer exhibiting low stress to the underlying capacitor may include low temperature ECR-oxide layer and PECV1) oxide layer. The layer exhibiting good step coverage may include USG layer and MG layer.

In accordance with this invention, the method includes the steps of forming a first insulating layer over a semiconductor substrate having a gate electrode structure and a diffusion layer; forming a ferroelectric capacitor composed of a lower electrode. a ferroelectric film, and an upper electrode over the first insulating layer; and forming a second insulating layer of multi-layer structure for interlayer dielectric over the first insulating layer including the capacitor, wherein the multi-layer structure includes a first layer exhibiting low stress characteristics and a second layer exhibiting good step coverage.

In this embodiment, the first layer is made of an oxide layer by ECR oxide layer at low temperature. This ECR oxide layer has an advantage of exhibiting low stress but has poor step coverage. To address this poor step coverage, an additional oxide layer which has a good step coverage such as USG layer orPSG layer is formed on the ECR oxide layer. This USG or MG layer also prevent wet etchant chemical from infiltrating thereby attacking ferroelectric film.

With the use of double structure interlayer dielectric layer by laminating layer exhibiting low stress characteristics and layer exhibiting a good step coverage, degradation of ferroelectric characteristics can be minimized and thus electrical reliability of the 3 ferroelectric film can be provided.

In another embodiment, the layer exhibiting a good step coverage such as USG layer is first deposited and then the layer exhibiting low stress characteristics such as ECR oxide]aver may be deposited thereon.

The invention may be understood and its objects will become apparent to those skilled in the art by reference to the accompanying drawings as follows:

Fig. I is a cross-sectional view of a conventional ferroelectric memory device; Fig.2 is a cross-sectional SEM image of the conventional ferroelectric memory device after dipping in wet etchant; Fig.3A to Fig.3C are flow diagrams showing the process steps of a novel method for fabricating a ferroelectric memory device according to an embodiment of the present invention, and Fig.4 is a cross-sectional SEM image of the ferroelectric memory device according to the present invention after dipping in wet etchant.

A preferred embodiment of the present invention will now be described by way of example with -)o reference to the accompanying drawings. The present invention relates to a method for fabricating a ferroelectric memory device. The process for forming the field oxide layer and the field effect transistor structure as presently practiced in manufacturing DRAM cells are only briefly described in order to better understand the current invention.

Referring to Fig.3A, a device isolation layer 102 is formed at a predetermined region of a semiconductor substrate 100 to define active and inactive regions. This device isolation layer 102 is formed by known method such as LOCOS(LOCal Oxidation of Silicon). There is formed a transistor including a gate oxide layer 103. a gate electrode 104 with insulating capping laver(not shown) and sidewall spacers(not shown), and a source/drain region(not 4 shown). A first insulating layer 106 such as an oxide layer is formed over the semiconductor substrate 100 including the transistor.

Referring to Fig.3B, a ferroelectric capacitor 112 is formed over the first insulating layer 106. The ferroelectric capacitor includes a lower and an upper electrodes 108 and 110 composed of platinum and a ferroelectric film 109 therebetween. The ferroelectric film 109 is made of M, PLZT, or the like.

A capping layer 114 such as TiO, may be formed to cover the ferroelectric capacitor 112. This capping layer 114 serves to prevent the ferroelectric film 109 from reacting with surrounding materials during subsequent process.

The formation of interlayer dielectric over the ferroelectric capacitor is critical process step of the ferroelectric capacitor process since the ferroelectric characteristics varies according to what kine of interlayer dielectric and its deposition condition particularly, deposition temperature. It is preferably required that the interlayer dielectric over the ferroelectric capacitor be a layer of good step coverage as well as low stress. and the ferroelectric film have reduced thermal budget. If the step coverage is poor, subsequent wet etchant readily infiltrate into the interlayer dielectric and eventually breaking down the ferroelectric film. One promising candidate exhibiting low stress at low temperature is ECR(electron cyclotron resonance) oxide layer. However, since this low temperature oxide layer by ECR technique grows with concurrently at a predetermined crystal orientation over the capping layer 114 and has poor step coverage and thereby being subjected to be attacked by wet chemical etchant. Therefore, additional layer is required for good step coverage and thereby preventing wet etchant chemical infiltration. USG(undoped silicate glass) layer or PSG(phosphosilicate glass) layer may be compatible with this additional layer. Therefore the combination ECR oxide layer and USG(or PSG) layer over the ferroelectric capacitor is expected to have a good step coverage, to alleviate the stress, and to prevent infiltration of wet chemical etchant, thereby suppressing degradation of ferroelectric characteristics.

The formation of this interlayer dielectric 118 novel to this invention is next addressed and shown schematically in Fig.3C. As described above, combination of low stress layer and good step coverage layer is formed over the first insulating layer 106 including the capping layer 114. More specifically, first low stress layer 116 such as ECR oxide layer or PECV1) oxide layer is deposited at low temperature. And then another layer 117 of good step coverage such as USG or PSG layer is deposited thereon.

Alternatively, the layer 117 of good step coverage may be deposited first and then the laver of low stress 116. For example, PSG layer is deposited and then followed by ECR oxide layer.

Next, contact holes 11 9a and 1 19b are opened in the interlayer dielectric layer 118 and. the interlayer dielectric layer 118 and the first insulating layer 106 respectively to the lower electrode layer 108 and to the source/drain region. After forming the contact holes 11 9a and 1 19b. dipping process is carried out to remove native oxide on the contact holes usinp- wet etchant chemicals. As mentioned above, good step coverage prevent the etchant chemicals from infiltrating thereinto. Fig.4 illustrates a SEM image of a ferroelectric memory device after dipping in wet etchant chemicals according to the embodiment of the IS present invention. In Fig.4, the interlaver dielectric 118 is double layer of ECR oxide layer and USG layer. Comparing interlaver dielectric of ECR oxide single layer shown in Fig.2. it can be seen that this ECR oxide-USG double layer has a good step coverage.

Subsequently. the desired contact metallurgy is deposited and patterned as is known in the art. Higher levels of metallurgy(not shown) and passivation can be formed over the -)o metal layer to complete the transistor and ferroelectric memory devices. For example, a hiú!her level f metallurgy contact to the top capacitor electrode(not shown) is necessary. The process is continued as understood by those skilled in the art to form the required interconnection metallurgy and passivation to complete the integrated circuit of the invention.

This invention provide a method for fabricating a ferroelectric memory device, more particularly ferroelectric capacitor with reliability of ferroelectric capacitor wherein interlaver dielectric over the capacitor has a double-laver structure formed by combination of low stress layer and good step coverage layer.

6 While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.

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Claims

WHAT IS CLAIMED IS:

A method for fabricating a ferroelectric memory device comprising the steps of:

S -)o forming a first insulating layer over a semiconductor substrate having a gate electrode structure and a diffusion layer; forming a ferroelectric capacitor composed of a lower electrode, a ferroelectric film, and an upper electrode over said first insulating layer.. and forming a second insulating layer of multi-layer structure over said first insulating layer including said capacitor, wherein said multi-layer structure includes a first layer exhibiting low stress characteristics and a second layer exhibiting good step coverage.
"? A method according to claim 1, wherein said first layer of said multilayer structure is made of a low temperature ECR-oxide layer and said second layer of said multilaver structure is made of USG layer or PSG]aver.
A method according to claim 1, wherein said first layer of said multilaver structure is made of PE-CV13 oxide layer and said second layer of said multi-laver structure is made of USG layer.
4. A method according to claim 1, further comprising forming contact holes in said second insulating layer to said diffusion layer and to said lower electrode. and removing native oxide layer through dipping in wet chemical etchant, wherein said second layer of said multi-layer structure prevents said wet chemical etchant from infiltrating into 2-5 said ferroelectric film.
5. A method according to claim 1, further comprising, before forming said second insulating]aver, forming a capping layer to cover said ferroelectric capacitor.

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6. A method according to claim 5, wherein said capping]aver comprises TIO, layer.
7. A method for fabricating a ferroelectric memory device comprising the steps of..

forming a first insulating layer over a semiconductor substrate having a gate electrode structure and a diffusion layer; forming a ferroelectric capacitor composed of a lower electrode, a ferroelectric film, and an upper electrode over said first insulating layer; and forming a second insulating layer of multi-layer structure over said first insulating layer including said capacitor, wherein said multi-layer structure includes a first layer exhibiting good step coverage and a second layer exhibiting low stress characteristics.
8. A method according to claim 7, wherein said first layer of said multilayer structure is made of USG or MG layer and said second layer of said multi- layer structure is made of low temperature ECR-oxide layer.
9. A method according to claim 7, further comprising. before forming said second insulating layer, forming a capping layer to cover said ferroelectric capacitor.
10. A method according to claim 7, wherein said capping layer comprises TiO, layer.
11. A method of fabricating a ferroelectric memory device substantially as hereinbefore described with reference to figures 3A to 4 of the accompanying drawings.

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