GB2327144A

GB2327144A - Method and substrate for wafer interconnection

Info

Publication number: GB2327144A
Application number: GB9714364A
Authority: GB
Inventors: James Wang; Kenneth Kaskoun; Werner Budweiser
Original assignee: Motorola Inc
Current assignee: Motorola Solutions Inc
Priority date: 1997-07-09
Filing date: 1997-07-09
Publication date: 1999-01-13
Also published as: GB9714364D0

Abstract

A substrate wafer is provided for connecting to a product wafer to be tested or burned-in. The substrate wafer has a first series of terminals 135 for coupling the semiconductor wafer to the substrate wafer, such that the wafers overlap when coupled. A further series of terminals 140 are provided for coupling to external equipment, these terminals being formed from a suitably thin flexible material, and being located in a region of the substrate wafer which overlaps with the product wafer. In this way the substrate wafer may be the same size as the semiconductor wafer.

Description

METHOD AND SUBSIRTE FOR WAFER JINTERCONNITION Field of the Invention This invention relates to a method for connecting a product wafer and a substrate wafer, and more particularly but not exclusively to testing and burn-in of a product wafer.

Background of the Invention Semiconductor wafers, such as silicon wafers, are typically produced in large numbers, and each wafer may contain a large number of devices.

The wafer is sliced to separate the devices, which are then individually packaged. The semiconductor devices require testing, and some also require a process known as burn-in, where semiconductor devices are exercised in an environment of elevated temperature. This is to force the weaker devices to fail early so that they do not reach the customer. In the past, devices were tested and burned-in discretely, whereas currently there is a need to achieve wafer level testing and burn-in, i.e. a method of testing and burning-in individual devices while they are still together on the wafer.

Wafers are easier to handle than devices, and a wafer level method is more efficient than discrete device methods.

A known method of wafer level testing and burn-in involves the joining of a substrate to a product wafer. This is typically achieved by standard flip chip bonding processes. The substrate has solder bumps and circuitry to allow the testing and burn in of the product wafer. The substrate is therefore larger than the product wafer, so that connections to testing and burn-in equipment can be provided via probes or pogo pins located on the same side of the wafer as the solder bumps.

A problem with this arrangement is that silicon material of a similar type to the product wafer is typically used for the substrate due to the fact that the thermal coefficient of expansion matches the product wafer. The semiconductor industry is moving to larger and larger wafers. An 8" product wafer would require the substrate to be at least 9". A 12" product wafer would need a 13" substrate. Larger diameter substrates are more costly to produce, and cause handling and processing problems.

This invention seeks to provide a method and substrate for wafer interconnection which mitigate the above mentioned disadvantages.

Summary of the Invention According to a first aspect of the present invention there is provided a method for connecting a substrate wafer and a product wafer, comprising the steps of: providing first and second series of terminals on the substrate wafer, the second series of terminals being coupled to external equipment; and, coupling the semiconductor wafer to the substrate wafer via the first series of terminals, such that the wafers substantially overlap; wherein the second series of terminals are located in a region of the substrate wafer which overlaps with the product wafer, such that the substrate wafer is substantially the same size as the semiconductor wafer.

According to a second aspect of the present invention there is provided a substrate wafer for connecting to a product wafer, the substrate wafer comprising: a first series of terminals for coupling the semiconductor wafer to the substrate wafer, such that the wafers substantially overlap; and, a second series of terminals for coupling to external equipment; wherein the second series of terminals are located in a region of the substrate wafer which overlaps with the product wafer, such that the substrate wafer is substantially the same size as the semiconductor wafer.

Preferably the external equipment includes test equipment. The external equipment preferably includes burn-in equipment.

Preferably the first series of terminals are flip chip solder bumps, and the second series of terminals are provided by flexible substrate material, having a thickness less than the gap between the substrate wafer and the product wafer.

Preferably the second series of terminals are provided by a sheet of flexible substrate material, having an aperture in which the substrate wafer is located, the sheet extending over the edges of the substrate wafer.

Alternatively the second series of terminals are interconnection segments, extending substantially radially from the substrate wafer.

In this way a method and substrate for wafer interconnection is provided, which allows the substrate wafer to be the same size as the product wafer, facilitating ease of manufacture of the substrate wafer.

Brief Description of the Drawmg(s) An exemplary embodiment of the invention will now be described with reference to the drawing in which: FIGS.1 and 2 show prior art wafer interconnection arrangements.

FIG.3 shows a product and substrate wafer interconnected in accordance with a preferred embodiment of the invention.

FIGS.4 and 5 show substrate wafer arrangements forming part of the arrangement of FIG.3.

FIG.6 shows a preferred feature of the arrangement of FIG.5.

Detailed Description of a Preferred Embodiment Referring to FIG.1, there is shown a prior art flip chip bonding arrangement 10 of a product wafer 20 and a substrate 30, which is of the same semiconductor material as the product wafer. Solder bumps 35 and circuitry (not shown) are formed on the top surface of the substrate 30, to allow for testing and burn in of the product wafer 20.

Referring now also to FIG.2, there is shown the arrangement 10 with the product wafer 20 joined to the substrate 30, via the solder bumps 35. In order to connect the circuitry of the substrate to external testing and/or burn-in equipment (not shown) probes or pogo pins 40 are connected to the top surface of the substrate, and protrude vertically therefrom. The substrate 30 must therefore be larger than the product wafer 20, so that the probes 40 can be accommodated.

Referring now to FIG.3 there is shown an arrangement 100 of a product wafer 120 and a substrate wafer 130, which is of the same semiconductor material as the product wafer. Solder bumps 135 and circuitry (not shown) are formed on the top surface of the substrate wafer 130, to allow for testing and burn in of the product wafer 120. The solder bumps 35 give rise to a vertical separation between the product wafer 120 and the substrate wafer 130 which is significantly greater than 501lm (typically 100cut).

In order to connect the circuitry of the substrate wafer 130 to external testing and/or burn-in equipment (not shown), thin connectors 140 are bonded to the top surface of the substrate wafer 130, the connectors being less than 501lm in thickness, and made of a material such as flex material.

Since the thin connectors 140 are less than 5011m in thickness, they can be mounted on a portion of the substrate wafer 130 which underlies the product wafer 120, without interfering physically or electrically with the product wafer 120. This allows the substrate wafer 130 and the product wafer 120 to be the same size. The substrate wafer 130 can thus be produced with the same equipment as the product wafer 120, and in a similar manner. Furthermore, the minimum pitch between adjacent electrical connections on thin connectors is 12011m, compared with a minimum pitch of at least 250m which is used for the prior art probes 40. Therefore more connections are possible.

Referring now also to FIG.4, there is shown a first alternative arrangement of the thin connectors 140, using a sheet of flex material 140', with a ring cut out of it and attached to the substrate wafer 130. The diameter of the ring will be slightly smaller than the diameter of the substrate wafer 130, such that some of the sheet of flex material 140' overlaps the edges of the substrate wafer 130. Slits 150 are provided in the sheet of flex material, in order to allow attachment to the substrate wafer 130 to take place in segments.

Referring now also to FIGS.5 and 6, there is shown a second alternative arrangement of the thin connectors 140, using a number of segments of flex material 140", which extend radially from the substrate wafer 130. A rigid ring 160 is connected to each of the segments of flex material 140", and surrounds the substrate wafer 130, The ring 160 provides increased strength to the arrangement, in addition to facilitating easier handling.

Burn -in requires some active and passive devices, which have hitherto been mounted on the substrate. The rigid ring 160 can be provided with some of these active and passive devices, which simplifies the manufacture of the substrate wafer 130, since it needs only to consist of metal lines extending to an outside edge. This simplifies the substrate wafer 130 and reduces cost. The connection to the burn in test equipment can be made with standard connectors, mounted on the rigid ring.

It will be appreciated that alternative embodiments to the one described above are possible. For example, other physical arrangements of the thin material 140 other than the sheet or segments described above are possible.

Claims

1. A method for connecting a substrate wafer and a product wafer, comprising the steps of: providing first and second series of terminals on the substrate wafer, the second series of terminals being coupled to external equipment; and, coupling the semiconductor wafer to the substrate wafer via the first series of terminals, such that the wafers substantially overlap; wherein the second series of terminals are located in a region of the substrate wafer which overlaps with the product wafer, such that the substrate wafer is substantially the same size as the semiconductor wafer.

2. A substrate wafer for connecting to a product wafer, the substrate wafer comprising: a first series of terminals for coupling the semiconductor wafer to the substrate wafer, such that the wafers substantially overlap; and, a second series of terminals for coupling to external equipment; wherein the second series of terminals are located in a region of the substrate wafer which overlaps with the product wafer, such that the substrate wafer is substantially the same size as the semiconductor wafer.

3. The method or substrate wafer of claim 1 wherein the external equipment includes test equipment.

4. The method or substrate wafer of claim 1 or 2 wherein the external equipment includes burnn equipment.

5. The method or substrate wafer of any preceding claim wherein the first series of terminals are flip-chip solder bumps.

6. The method or substrate wafer of any preceding claim wherein the second series of terminals are provided by flexible substrate material, having a thickness less than the gap between the substrate wafer and the product wafer.

7. The method or substrate wafer of claim 6 wherein the second series of terminals are provided by a sheet of flexible substrate material, having an aperture in which the substrate wafer is located, the sheet extending over the edges of the substrate wafer.

8. The method or substrate wafer of claim 6 wherein the second series of terminals are interconnection segments, extending substantially radially from the substrate wafer.

9. The method or substrate wafer of claim 8 wherein the interconnection segments are further coupled to a ring which surrounds the substrate wafer.

10. The method or substrate wafer of claim 9 wherein the ring includes circuitry for performing burn-in and/or test of the substrate wafer.

11. A method for connecting a substrate wafer and a product wafer substantially as hereinbefore described and with reference to FIGS. 3 to 6 of the drawings.

12. A substrate wafer for connecting to a product wafer substantially as hereinbefore described and with reference to FIGS. 3 to 6 of the drawings.