GB2322247A - Adjustable linearised MOS transconductance amplifier using a source-coupled pair and square-root circuits - Google Patents

Adjustable linearised MOS transconductance amplifier using a source-coupled pair and square-root circuits Download PDF

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GB2322247A
GB2322247A GB9803348A GB9803348A GB2322247A GB 2322247 A GB2322247 A GB 2322247A GB 9803348 A GB9803348 A GB 9803348A GB 9803348 A GB9803348 A GB 9803348A GB 2322247 A GB2322247 A GB 2322247A
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mosfet
source
mosfets
gate
drain
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GB9803348D0 (en
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Katsuji Kimura
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/12—Arrangements for performing computing operations, e.g. operational amplifiers
    • G06G7/20—Arrangements for performing computing operations, e.g. operational amplifiers for evaluating powers, roots, polynomes, mean square values, standard deviation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers

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  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
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  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

The transfer function of a source-coupled transistor pair M1,M2 is linearised by square-root circuits 1a,1b which provide current outputs I+ and I- respectively proportional to the square roots of the transistor drain currents ID1 and ID2. The difference between the output currents I+ and I- is a linear function of the differential input voltage Vi. The gain of the amplifier may be adjusted by varying a reference current supplied to the square-root circuits. Bipolar or MOS square-root circuits may be used. MOS and bipolar squaring circuits are disclosed (figures 14 and 15).

Description

TUNABLE HOS LINEAR TRANSCONDUCTANCE AMPLIFIER HAVING SOURCE-COUPLED PAIR AND SQUARE-ROOT CIRCUITS The present invention relates to a linear transconductance amplifier and more particularly, to a linear trans conductance amplifier having a differential pair of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), which is capable of completely linear operation and transconductance tuning.
In recent years, linear transconductance amplifiers have been recognized as an essential function block in the analog signal applications. Especially, the need of MOS linear transconductance amplifiers and tunable MOS linear trans conductance amplifiers capable of transconductance tuning have been becoming stronger and stronger.
In general, a conventional MOS linear transconductance amplifier has two eguivalent floating transistors formed by using the square-law transfer characteristic of a MOSFET. An output current of this conventional MOS linear transconductance amplifier is given by a difference between two output currents of the two floating transistors.
Linearity of the trans conductance is ensured from the following identity (1) in this conventional MOS linear transconductance amplifier.
ss(Vi + VTH) - ss(Vi - VTH) = 4ssVTH.Vi (1) In the identity (1), Vi is a differential input voltage, VTH is the threshold voltage of a MOSFET, and ss is the transconductance parameter of a MOSFET. The transconductance parameter ss is defined as 8 Cox . W 2 L where is the mobility of a carrier, Cox is the gate-oxide capacitance per unit area, and W and L are a gate width and a gate length of a MOSFET, respectively.
The identity (1) is given on the supposition that (a) all MOSFETs are matched in characteristics, that (b) the channel-length modulation and the body effect can be ignored, and that (c) a drain current ID of a MOSFET varies with its gate-to-source voltage VGS according to the square-law characteristic; i.e., the following equation (2) is established.
ID B (VGS VTH)2 (2) Fig. 1 shows an example of the conventional MOS linear transconductance amplifiers of this sort. This amplifier is disclosed in a paper, IEE Electronics Letters, Vol. 32, No. 18, pp. 1629-1630, 29th August 1996, which is entitled Independent control of transconductance gain and input linear range in a MOS linear transconductance amplifier", and written by J. Mahattanakul and C. Toumazou.
This paper describes a known fact that a current with a square-law characteristic is linearized by a square-root circuit with reference to its Fig. 1, a bipolar square-root circuit and a MOS square-root circuit with reference to its Fig. 2, and a MOS linear transconductance amplifier using a MOS differential pair and Wilson current mirrors with reference to its Fig. 3.
The conventional MOS trans conductance amplifier shown in Fig. 1 has the following configuration.
Two n-channel MOSFETs M101 and M102 constitute a MOS differential pair. Three n-channel MOSFETs M103, M107. and M109 constitute a first Wilson current mirror circuit. Three n-channel MOSFETs M104, M108, and M110 constitute a second Wilson current mirror circuit. Two n-channel MOSFETs M105 and M106 serve as floating transistors.
Sources of the MOSFETs M101 and M102 are coupled together and connected through a constant current sink sinking a constant current Iss to a power supply line applied with a power supply voltage Vss, Gates of the MOSFETs M101 and M102 are applied with first and second input voltages Vinl and V=2, respectively, where Vinl - VLN2 = V1. Drains of the MOSFETs M101 and M102 are connected to sources of the MOSFETs M105 and M106, respectively.
A source the MOSFET M103 is connected to the ground.
A gate of the MOSFET M103 is connected to a gate and a drain of the MOSFET M109. A drain of the MOSFET M103 is connected through a constant current sink sinking a constant current 1o to a power supply line applied with a power supply voltage VDD.
A source of the MOSFET M109 is connected to the ground. The gate and the drain of the MOSPET M109 are coupled together and connected to a source of the MOSPET M107.
A gate of the MOSFET M107 is connected to the drain of the MOSFET M103 and a gate of the MOSFET M105. A drain of the MOSFET M107 is connected to a drain of the MOSFET M106 at a point Y.
A source the MOSFET M104 is connected to the ground.
A gate of the MOSFET M104 is connected to a gate and a drain of the MOSFET M110. A drain of the MOSFET M104 is connected through a constant current sink sinking a constant current 1o to the power supply line applied with the power supply voltage VDD.
A source of the MOSFET M110 is connected to the ground. The gate and the drain of the MOSFET M110 are coupled together and connected to a source of the MOSFET M108.
A gate of the MOSFET M108 is connected to the drain of the MOSFET M104 and a gate of the MOSFET M106. A drain of the MOSFET M108 is connected to a drain of the MOSFET M105 at a point X.
The operation principle of this conventional MOS linear transconductance amplifier will be explained below, which was given through the inventor's analysis Here, it is supposed that all the MOSFETs M101, M102, M103, M104, M105, M106, M107, M108, M109, and M110 are operating in the saturation region. Also, drain currents of the MOSFETs M101 to M110 are defined as ID101, Idiot, ID103. ID104, ID105, ID106, ID107, ID108, ID109, and ID110, respectively.
Then, the following equations (3a) and (3b) are established using the above equation (2).
Because the combination of the MOSFETs M103, M107, and M109 and that of the MOSFETs M104, M108, and M110 constitute the Wilson current mirrors, respectively, the following equation (4) is given.
ID103=ID107=ID109=ID104=ID108=ID110=I0 (4) Therefore, if currents flowing through the points X and Y are defined as I101 - I102, an output current IOUT of the conventional MOS linear transconductance amplifier shown in Fig. 1 is given by the following equation (5).
= I101 - I102 = (ID105 + ID108) - (ID106 + ID107) (5)
The equation (5) is the same as the known differential output current of a simple MOS differential pair.
Therefore, the conventional MOS linear transconductance amplifier shown in Fig. 1 has a problem that it is unable to have a completely linear transfer characteristic.
Also, this conventional amplifier shown in Fig. 1 has another problem that the transconductance value is unable to be adjusted while keeping the amplifier characteristic unchanged.
Embodiments of the present invention aim to provide a MOS linear trans conductance amplifier that realizes a completely-linear transfer characteristic.
Another aim is to provide a MOS linear transconductance amplifier capable of trans conductance tuning while keeping the amplifier characteristic unchanged.
The above objects together with others not specifically mentioned will become clear to those skilled in the art from the following description.
A MOS linear transconductance amplifier according to the present invention has (a) a MOS differential pair of source-coupled first and second MOSFETs, (b) a first constant current source/sink connected to the coupled sources of the first and second MOSFETs and supplying/sinking a first constant current for driving the MOS differential pair, (c) a first square-root circuit connected to a drain of the first MOSFET, and (d) a second square-root circuit connected to a drain of the second MOSFET.
The MOS differential pair is applied with an input voltage at gates of the first and second MOSFETs and differentially outputs first and second output currents at respective drains of the first and second MOSFETs.
The first square-root circuit is applied with the first output current of the MOS differential pair and outputs a third output current with a square-root transfer characteristic with respect to the first output current.
The second square-root circuit is applied with the second output current of the MOS differential pair and outputs a fourth output current with a square-root transfer characteristic with respect to the second output current.
An output current of the MOS linear transconductance amplifier is given by a difference between the third and fourth output currents.
With the MOS linear transconductance amplifier according to the present invention, the first and second output currents of the MOS differential pair, which have a same square transfer characteristic with respect to the input voltage except for the polarity, are applied to the first and second square-root circuits, respectively. on the other hand, the third output current has a square-root transfer characteristic with respect to the first output current, and the fourth output current has a squareroot transfer characteristic with respect to the second output current.
Therefore, the difference between the third and second output currents of the first and second square-root circuits is a completely-linear transfer characteristic. This is ensured by the following identity (6), where a is a parameter and x is a variable.
The left side of the identity (6) represents the differential output current of the MOS linear transconductance amplifier; in other words, the difference between the third and fourth output currents of the first and second square-root circuits. The right side of the identity (6) represents the input voltage.
In a preferred embodiment of the amplifier according to the present invention, each of the first and second square-root circuits has first, second, third, and fourth bipolar transistors, and a second constant current source/sink supplying/sinking a second constant current for driving the first transistor.
A base and an emitter of the second transistor are connected to a collector and a base of the first transistor, respectively. The second transistor is driven by a corresponding one of the first and second output currents of the MOS differential pair.
A base of the third transistor is connected to the base of the second transistor.
A base and a collector of the fourth transistor are connected to the emitter of the third transistor. An emitter of the fourth transistor is connected to the emitter of the first transistor.
A collector current of the third transistor serves as a corresponding one of the third and fourth output currents.
In this case, it is preferred that the second constant current source/sink is designed so that the second constant current is variable. There is an addltional advantage that the transconductance of the MOS linear transconductance amplifier is variable; in other words, the trans conductance is tunable.
In another preferred embodiment of the amplifier according to the present invention, each of the first and second square-root circuits has third, fourth, fifth, and sixth MOSFETs, and a second constant current sourceisink supplying/sinking a second constant current for driving the third MOSFET.
A gate and a source of the fourth MOSFET are connected to a drain and a gate of the third MOSFET, respectively. The fourth MOSFET is driven by a corresponding one of the first and second output currents of the MOS differential pair.
A gate of the fifth MOSFET is connected to the gate of the fourth MOSFET.
A gate and a drain of the sixth MOSFET are connected to the source of the fifth MOSFET. A source of the sixth MOSFET is connected to the source of the third MOSFET.
A drain current of the fifth MOSFET serves as a corresponding one of the third and fourth output currents.
In this case, it is preferred that the second constant current source/sink is designed so that the second constant current is variable. There is an additional advantage that the trans conductance of the MOS linear transconductance amplifier is variable;, in other words, the transconductance is tunable.
In still another preferred embodiment of the amplifier according to the present invention, each of the first and second square-root circuits further has a first set of n serially-connected MOSFETs and a second set of n serially-connected MOSFETs, where n is an integer equal to or greater than unity.
Each of the first set of n serially-connected MOSFETs has a diode connection. A drain and a gate of a first one of the first set of n MOSFETs are connected to the source of the third MOSFET.
Each of the second set of n serially-connected MOSFETs has a diode connection. A drain and a gate of a first one of the second set of n MOSFETs are connected to the source of the sixth MOSFET.
The source of the third MOSFET is connected to the source of the sixth MOSFET through the first set of n MOSFETs and the second set of n MOSPETs.
In a further preferred embodiment of the amplifier according to the present invention, the first square-root circuit has third, fourth, fifth, and sixth MOSFETs, and a second constant current source/sink supplying/sinking a second constant current for driving the third MOSFET, and the second square-root circuit has seventh, eighth, ninth, and tenth MOSFETs, and a third constant current source/sink supplying/ sinking a third constant current for driving the seventh MOSFET.
The third, fourth, seventh, and eighth MOSFETs are diode-connected.
A gate and a drain of the third MOSFET are connected to the second constant current source/sink. A source of the third MOSFET is connected to a gate and a drain of the fourth MOSFET.
A source of the fourth MOSFET is connected to a source of the sixth MOSFET.
A gate of the fifth MOSFET is connected to the gate of the first MOSFET. A drain of the fifth MOSFET serves as an output terminal from which the third output current is derived A source of the fifth MOSFET is connected to a corresponding one of the drains of the first and second MOSFETs.
A gate of the sixth MOSFET is connected to the source of the fifth MOSFET.
A gate and a drain of the seventh MOSFET are connected to the third constant current source/sink. A source of the seventh MOSFET is connected to a gate and a drain of the eighth MOSFET.
A source of the eighth MOSFET is connected to a source of the tenth MOSFET.
A gate of the ninth MOSFET is connected to the gate of the second MOSFET. A drain of the ninth MOSFET serves as an output terminal from which the fourth output current is derived. A source of the ninth MOSFET is connected to a corresponding one of the drains of the first and second MOSFETs.
A gate of the tenth MOSFET is connected to the source of the ninth MOSFET.
A drain of the sixth MOSFET is connected to the drain of the seventh MOSFET. A drain of the tenth MOSFET is connected to the drain of the fifth MOSFET.
In a still further preferred embodiment of the amplifier according to the present invention, the output current of the MOS linear trans conductance amplifier has a linear characteristic with respect to the second constant current.
The invention may be carried into practice in various ways, but embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a circuit diagram of a known MOS linear transconductance amplifier.
Fig. 2 is a circuit diagram showing the basic configuration of a MOS linear transconductance amplifier according to- embodiments of the present invention.
Fig. 3 is a graph showing the transfer characteristic of the MOS linear transconductance amplifier according to embodiments of the present invention Fig. 4 is a circuit diagram of a bipolar square-root circuit used for the MOS linear trans conductance amplifier according to embodiments of the present invention.
Fig. 5 is a circuit diagram of a MOS linear transconductance amplifier according to a first embodiment of the present invention, which includes two bipolar square-root circuits as shown in Fig. 4.
Fig. 6 is a graph showing the measured transfer characteristic of the MOS linear transconductance amplifier according to the first embodiment of the present invention.
Fig. 7 is a circuit diagram of a MOS square-root circuit used for the MOS linear transconductance amplifier according to embodiments of the present invention.
Fig. 8 is a circuit diagram of a MOS linear transconductance,amplifier according to a second embodiment of the present invention, which includes two MOS square-root circuits as shown in Fig. 7.
Fig. 9 is a circuit diagram of a MOS square-root circuit used for a MOS linear trans conductance amplifier according to a third embodiment of the present invention.
Fig. 10 is a circuit diagram of a MOS square-root circuit used for a MOS linear transconductance amplifier according to a fourth embodiment of the present invention.
Fig. 11 is a circuit diagram of a MOS linear transconductance amplifier according to a fifth embodiment of the present invention, which includes two MOS square-root circuits as shown in Fig. 7, where n = 0 and K2 = 4.
Fig. 12 is a circuit diagram of a MOS linear transconductance amplifier according to a sixth embodiment of the present invention.
Fig. 13 is a graph showing the measured transfer characteristic of the MOS linear trans conductance amplifier according to the sixth embodiment of the present invention.
Fig. 14 is a circuit diagram of a bipolar squarer circuit used for a MOS linear transconductance amplifier according to a seventh embodiment of the present invention.
Fig. 15 is a circuit diagram of a MOS squarer circuit used for a MOS linear transconductance amplifier according to an eighth embodiment of the present invention.
A MOS linear trans conductance amplifier according to embodiments of the present invention has a basic configuration as shown in Fig. 2.
In Fig. 2, this MOS linear transconductance amplifier has a MOS differential pair 2 of source-coupled MOSFETs M1 and M2, a first constant current source/slnk 3 connected to the coupled sources of the MOSFETs M1 and M2 and supplying/sinking a constant current Io for driving the MOS differential pair, a first square-root circuit la connected to a drain of the MOSFET M1, and a second square-root circuit lb connected to a drain of the MOSFET M2.
The MOS differential pair 2 is differentially applied with an input voltage Vi at gates of the MOSFETs M1 and M2 and differentially outputs first and second output currents (i.e., drain currents of the MOSFETs M1 and M2) ID1 and 1D2 at respective drains of the MOSFETs M1 and M2.
The first square-root circuit la is applied with the first output current 1D1 of the MOS differential pair 2 and outputs a third output current I+ = (ID1).
The second square-root circuit Ib is applied with the second output current ID2 of the MOS differential pair 2 and outputs a fourth output current I- = (ID2).
An output current Al of this MOS linear transconductance amplifier is given by a difference between the third and fourth output currents I+ and I-; i.e., Al = I+ - I+ = (ID1) - (ID2) With the MOS linear transconductance amplifier according to embodiments of the present invention, the first and second output currents ID1 and ID2 of the MOS differential pair 2, which have a same square-law transfer characteristic except for the polarity, are applied to the first and second squareroot circuits la and ib, respectively.
Therefore, the difference Al between the third and second output currents I' and I+ of the first and second square-root circuits la and ib is a completely-linear transfer characteristic. This is ensured by the above identity (6).
Specifically, if the constant a and the variable x in the identity (6) are substituted with 1 and [Vi/(I0/ )] respectively, the following equation (7) is given.
It is seen from the equation (7) that the differential output current #I (= I+ - I-) of the MOS linear transconductance amplifier according to embodiments of the present invention is a linear function with respect to the differential input voltage Vi. This means that this transconductance amplifier has a completely-linear transfer characteristic.
Fig. 3 shows the transfer characteristics of the third and fourth output currents I' [= ('Di)1,2) and I- [= (ID2)1/2] of the first and second square-root circuits la and ib, and the differential output current Al [= (ID1)] ~ (ID2)] of this amplifier.
It is seen from Fig. 3 that the third output current I+ [= (IDS )1/2] has a square-law characteristic and the fourth output current I- [= (ID2)1/2] has a same square-law characteristic opposite in polarity to the third output current I', resulting in the completely-linear characteristic of the differential output current hI.
FIRST EMBODIMENT Fig. 5 shows a MOS linear transconductance amplifier according to a first embodiment of the present invention, in which the circuit. configuration shown in Fig. 4 is used as each of the first and second square-root circuits la and ib.
Fig. 4 shows an example of the first square-root circuit la. Since the second square-root circuit ib has a same configuration as the first square-root circuit la, the description about the second square-root circuit lb is omitted here.
In Fig. 4, the first square-root circuit la is comprised of four npn-type bipolar transistors Q1, Q2, Q3, and Q4, a second constant current source 10 supplying a second constant current Ib for driving the transistor Q1, and a constant voltage source 4 supplying a constant voltage V.
The transistor Q2 has an emitter area of K times as large as the transistors Q1, Q3, and Q4, where K is a constant equal to or greater than unity (i.e., K 2 1) Emitters of the transistors Q1 and Q4 are coupled together and connected to the ground through the constant voltage source 4. A base of the transistor Q1 is connected to an emitter of the transistor Q2. A collector of the transistor Q1 is connected to a power supply line applied with a power supply voltage Vcc through the constant current source 10. The transistor Q1 is driven by the constant bias current Ib from the second constant current source 10.
A base of the transistor Q2 is connected to the collector of the ;transistor 91 A collector of the transistor Q2 is connected to the power supply line applied with the voltage Vcc. The emitter of the transistor Q2 is connected to the drain of the MOSFET M1 of the MOS differential pair 2.
The transistor Q2 is driven by a current I1 (i.e., the first output current ID1) of the MOS differential pair 2.
A base of the transistor Q3 is connected to the base of the transistor Q2 and the collector of the transistor Q1.
A collector of the transistors Q3 serves as an output terminal from which the third output current I is derived.
A base and a collector of the transistor Q4 are coupled together; in other words, the transistor 04 has a diode connection. The coupled base and collector of the transistor Q4 are connected to the emitter of the transistor Q3.
Next, the operation principle of the bipolar squareroot circuit la shown in Fig. 4 is explained below.
In general, a collector current Ic of a bipolar transistor has an exponential-law characteristic with respect to its base-to-emitter voltage VBE. Therefore, the following equation (8) is established.
In the equation (8), Is is the saturation current of a bipolar transistor and VT is the thermal voltage defined as VT = kT/q, where k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron.
When a bipolar transistor is operating in the normal operation region where the base-to-emitter voltage VBE is approximately 600 mV, the exponential part "exp(VBE/VT) in the equation (8) has a value of approximately e10 - Therefore, the constant part "-1" can be ignored. Thus, the equation (8) can be approximated to the following equation (9).
By applying the Kirchhoff's voltage law to the loop formed by the transistors Ql, Q2, Q3, and Q4, the following equation (10) is established for the first square-root circuit la, where VBE1, VBE2, VBE3, and VBP4 are base-to-emitter voltages of the transistors Q1, 02 Q3, and Q4, respectively.
VBE1 + VBE2 = VBE3 + VBE4 (10) The base-to-emitter voltages VBE1, VBE2, VBE3 and VBE4 are expressed as the following equations (11), (12), and (13).
By solving the equation (13) using the equations (10), (11), and (12), the third output current I+ of the first square-root circuit la is given by the following equation (14a).
This equation (14a) represents that the output current I+ is proportional to the square-root of the applied drain current or the first output current IDi; in other words, the circuit configuration shown in Fig. 4 provides a square-root function with respect to its input signal.
Next, the MOS linear transconductance amplifier according to the first embodiment is explained below.
As shown in Fig. 5, the second square-root circuit ib is comprised of four npn-type bipolar transistors Q5. Q6, Q7, and Q8 and a third constant current source 11 supplying a same constant current Ib for driving the transistor Q5. The constant voltage source 4 is commonly used for the second square-root circuit lb.
Emitters of the transistors Q5 and Q8 are coupled together and connected to the ground through the constant voltage source 4. A base of the transistor Q5 is connected to an emitter of the transistor Q6. A collector of the transistor Q5 is connected to the power supply line applied with the voltage Vcc through the constant current source 11.
The transistor Q5 is driven by the constant bias current Ib from the third constant current source 11.
A base of the transistor Q6 is connected to the collector of the transistor Q5. A collector of the transistor Q6 is connected to the power supply line applied with the voltage Vcc. The emitter of the transistor Q6 is connected to the drain of the MOSFET M2 of the MOS differential pair 2.
The transistor Q6 is driven by a current 12 (i.e., the second output current 1D2) of the MOS differential pair 2.
A base of the transistor Q7 is connected to the base of the transistor Q6 and the collector of the transistor 05.
A collector of the transistors Q7 serves as another output terminal from which the fourth output current I is derived.
A base and a collector of the transistor Q8 are coupled together; in other words, the transistor QE has a diode connection. The coupled base and collector of the transistor QE are connected to the emitter of the transistor Q7.
As explained above, the third output current I of the first square-root circuit la is given by the above equation (14a). In the same way as the first square-root circuit la, the fourth output current I- of the second square-root circuit lb is given by the following equation (14b) similar to the above equation (14a).
I
It is seen from the equation (15) that the differential output current Al of the MOS linear transconductance amplifier according to the first embodiment is proportional to the differential input voltage V1. In other words, the MOS linear transconductance amplifier according to the first embodiment has a completely linear transfer characteristic with respect to the differential input voltage V1.
Further, it is seen from the equation (15) that the trans conductance value is variable by changing the bias currents Ib for the transistors Q1 and 05. This means that the circuit configuration shown in Fig. 5 realizes a tunable MOS linear transconductance amplifier.
Additionally, the transconductance value may be adjusted by changing the emitter-area ratio K of the transistor Q2.
Fig. 6 shows the transfer characteristic of the MOS linear trans conductance amplifier according to the first embodiment of the present invention, which was measured by the inventor under the following condition.
The MOS differential pair 2 was formed by a PA572T- type transistor array. The first and second bipolar squareroot circuits 1a and ib were formed by a CTW4-type transistor array of the Test Element Group (TEG) produced by the CS processes. The power supply voltage Vcc was set as 5.0 V. The constant current (or, tail current) Io of the constant current sink 3 was set as approximately 12 mA. The common emitter voltage of the square-root circuits la and lb was set as 2.0 V. The emitter area ratio K was set as 9. The bias current Ib for the transistors Q1 and Q5 was set as approximately 90 A, 110 A, and 140 A. The operating input voltage range of the MOS differential pair 2 was 1 VP-P when the constant or tail current Io was approximately 12mA.
It is seen from Fig.6 that the differential output current #I has a completely-linear transfer characteristic within the specific range and that the completely-linear transfer characteristic of the differential output current Al may be shifted according to the -bias currents Ib for the transistors Q1 and 05.
SECOND EMBODIMENT Fig. 8 shows a MOS linear trans conductance amplifier according to a second embodiment of the present invention, in which the circuit configuration shown in Fig. 7 is used as each of the first and second square-root circuits la and ib.
Fig. 7 shows an example of the first square-root circuit la. Since the second square-root circuit ib has a same configuration as the first square-root circuit la, the description about the second square-root circuit ib is omitted here.
In Fig. 7, the first square-root circuit la is comprised of four n-channel MOSFETs M3, M4, MS, and M6, a second constant current source 10 supplying a second constant current Ib for driving the MOSFET M3, a first set 21 of n serially-connected n-channel MOSFETs M21-1 to M21-n, and a second set 22 of n serially-connected n-channel MOSFETs M22-1 to M22-n, where n 2 1.
The MOSFET M4 has a ratio (W/L) of the gate-width W to the gate-length L of K1 times as large as the MOSPETs M3 and the first set 21 of n MOSPETs M21-1 to M21-n, where K1 is a constant equal to or greater than unity (i.e., K1 2 1). The MOSFETs M5 and M6 and the second set 22 of n MOSFRTs M22-1 to M22-n have a same ratio (W/L) of K2 times as large as the MOSFETs M3 and the first set 21 of n MOSFETs M21-1 to M21-n, where K2 is a constant equal to or greater than unity (i.e., K2 2 1).
A source of the MOSFET M3 is connected to the ground through the first set 21 of n MOSFETs M21-1 to M21-n. A source of the MOSFET M6 is connected to the ground through the second set 22 of n MOSFETs M22-l to M22-n.
Unlike the bipolar configuration shown in Fig. 4 according to the first embodiment, no constant voltage source for voltage-level adjustment is provided. This is because the first set 21 of n diode-connected MOSFETs M21-1 to M21-n and the second set 22 of n diode-connected MOSFETs M22-1 to M22-n serve as constant voltage sources for the MOSPETs M3 and M6, respectively.
A gate of the MOSFET M3 is connected to a source of the MOSPET M4. A drain of the MOSFET M3 is connected to a power supply line applied with a power supply voltage VDD through the constant current source 10. The MOSFET M3 is driven by the constant current Ib from the second constant current source 10.
A gate of the MOSFET M5 is connected to the gate of the MOSFET M4 and the drain of the MOSFET M3. A drain of the MOSFET M5 serves as an output terminal from which the third output current I* is derived.
A gate and a drain of the MOSFET M6 are coupled together; in other words, the MOSFET M4 has a diode connection. The coupled gate and drain of the MOSFET M6 is connected to the source of the MOSFET M5.
Each of the first set 21 of n serially-connected MOSFETs M21-1 to M21-n has a diode connection. A drain and a gate of the MOSFET M21-1 are connected to the source of the MOSFET MS. A source of the MOSFET M21-n is connected to the ground.
Each of the second set 22 of n serially- connected MOSFETs M22-1 to M22-n has a diode connection. A drain and a gate of the MOSFET M22-1 are connected to the source of the MOSFET M6. A source of the MOSFET M22-n is connected to the ground.
Thus, the source of the MOSFET M3 is connected to the source of the MOSFET M6 through the first and second sets 21 and 22 of MOSFETs M21-1 to M21-n and M22-1 to M22-n.
Next, the operation principle of the MOS square-root circuit la shown in Fig. 7 is explained below.
Here, the transconductance parameter of the MOSFET M3 is defined as ss. Then, the transconductance parameters of the MOSFETs M21-1 to M21-n are expressed as ss, the transconductance parameter of the MOSFET M4 is expressed as K1P. the transconductance parameters of the MOSFETs M5, M6, and M22-1 to M22-n are expressed as K2.
By using the previously-described equation (2), the bias current Ib. an input current I1 (= the drain current ID1), and the output current I+ are expressed by the following equations (16), (17), and (18), respectively.
Ib = ID3 = ss (VGS3 - VTH) (16) I1 = ID1 = K1ss (VGS4 - VTH) (17) I+ = ID5 = K2ss (VGS5 - VTH) (18) In the equations (16), (17), and (18), ), VGS4, and VGS5 are gate-to-source voltages of the MOSFETs M3, M4. and MS, and 1D3 and ID5 are drain currents of the MOSFETs M3 and M5, respectively.
Also, each of the MOSFETs M21-1 to M21-n has a same gate-to-source voltage as VGS3 of the MOSFET M3, and each of the MOSFETs M22-1 to M22-n and M6 has a same gate-to-source voltage as VGS5 of the MOSFET M5. Therefore, the following equation (19) is established.
(n + 1) VGS3 + VGS4 = (n + 2) VGS5 (19) If the equations (16), (17), and (18) are substituted into the equation (19), the following equation (20a) is given.
It is seen from the equation (20a) that the output current I (IDS) of the first square-root circuit la shown in Fig. 7 is expressed by using a square-root of Ii. However, the equation (20a) includes first-order terms of I1 and Ib.
In the MOS linear transconductance amplifier according to the second embodiment shown in Fig. 8, the second square-root circuit ib is comprised of four n-channel MOSFETs M7. M8, M9. and M10, a constant current source 11 supplying a same constant current Ib as the constant current source 10 for the purpose of driving the MOSFET M7, a third set 23 of n serially-connected n-channel MOSFETs M23-1 to M23-n, and a fourth set 24 of n serially-connected n-channel MOSFETs M24-l to M24-n.
The MOSFET M8 has a ratio (W/L) of the gate-width W to the gate-length L of K1 times as large as the MOSFETs M7 and the third set 23 of n MOSFETs M23-1 to M23-n. The MOSFETs M9 and MlO and the fourth set 24 of n MOSFETs M24-1 to M24-n have a same ratio (W/L) of K2 times as large as the MOSFETs M7 and the third set 23 of n MOSFETs M23-1 to M23-n.
A source of the MOSFET M7 is connected to the ground through the third set 23 of n MOSFETs M23-1 to M23-n. A source of the MOSFET M10 is connected to the ground through the fourth set 24 of n MOSFETs M24-1 to M24-n. No constant voltage source for voltage-level adjustment is provided.
A gate of the MOSFET M7 is connected to a source of the MOSFET M8. A drain of the MOSFET M7 is connected to the power supply line applied with the power supply voltage VDD through the constant current source ll. The MOSFET M7 is driven by the constant current Ib from the constant current source 11.
A gate of the MOSFET M9 is connected to the gate of the MOSFET M8 and the drain of the MOSFET M7. A drain of the MOSFET M9 serves as another output terminal from which the output current I- is derived.
A gate and a drain of the MOSFET M10 are coupled together; in other words, the MOSFET MIO has a diode connection. The coupled gate and drain of the MOSFET M10 is connected to the source of the MOSFET M9.
Each of the third set 23 of n serially-connected MOSFETs M23-1 to M23-n has a diode connection. A drain and a gate of the MOSFET M23-1 are connected to the source of the MOSFET M7. A source of the MOSFET M23-n is connected to the ground.
Each of the fourth set 24 of n serially-connected MOSFETs M24-1 to M24-n has a diode connection. A drain and a gate of the MOSFET M24-1 are connected to the source of the MOSFET M10. A source of the MOSFET M24-n is connected to the ground.
Thus, the source of the MOSFET M7 is connected to the source of the MOSFET M10 through the third and fourth sets 23 and 24 of MOSFETs M23-1 to M23-n and M24-1 to M24-n.
The output current I. of the second square-root circuit Ib is expressed by the following equation (20b).
To cancel the first-order term of I1 in the equations (20a) and (20b) by subtracting the output current I from the output current I for the purpose of producing the differential output current Awl, the following relationship needs to be established.
K2 = 1 t21) K1 (n + 2) In this case, the differential output current Al of the MOS linear trans conductance amplifier according to the second embodiment will be proportional to I1.
For example, K1 is set as 1, the relationship (21) is changed to the following relationship (22).
K2=(n+2)2 (22) The minimum value of K2 is given at n = 0 in the expression (22). In this case, K2 = 4.
Here, the setting of K2 as an integer equal to or greater than 4 is equivalent to the division of the output currents ID1 and 1D2 of the MOS differential pair 2 into (ID1 /K2) and (ID2/K2), respeQtively.
There are the same advantages as those in the first embodiment.
THIRD EMBODIMENT Fig. 9 shows an example of the first square-root circuit la used for a MOS linear trans conductance amplifier according to a third embodiment. In this transconductance amplifier, the output currents Ini and 1D2 of the MOS differential pair 2 shown in Fig. 7 are simply divided into ID1 /K2) and (ID2/K2), respectively.
In Fig. 9, a set 25 of K2 n-channel MOSFETs M4-1 to M4-K2 are provided instead of the MOSFET M4 in Fig. 7. Gates of the MOSFETs M4-1 to M4-K2 are commonly connected to the drain of the MOSFET M3. Sources of the MOSFETs M4-1 to M4-K2 are commonly connected to the gate of the MOSFET M3. Drains of the MOSFETs M4-1 to M4-K2 are commonly connected to the power supply line applied with the voltage VDD.
The sum of the drain currents 1b4.1 to ID4-K2 of the MOSFETs M4-1 to M4-K2 is equal to the first output current 1i of the MOS differential pair 2, or I1.
There are the same advantages as those in the first embodiment.
There is an additional advantage that this squareroot circuit la can be realized under the condition that K1 = K2 = 1; in other words. each of the MOSFETs is formed by a unit MOSFET.
FOURTH EMBODIMENT Fig. 10 shows an example of the first square-root circuit la used for a MOS linear transconductance amplifier according to a fourth embodiment, in which the constant K2 needs to be expressed by the multiplication of two positive integers i and j.
In this transconductance amplifier, the output currents ID1 and 1D2 of the MOS differential pair 2 shown in Fig. 8 are divided into (ID1ti-j) and (ID2/i01). respectively.
In Fig. 10, a pair 26 of n-channel MOSFETs M4a-1 and M4a-2 and a set 27 of n-channel MOSFETs M4b-1 to M4b-j are provided instead of the MOSFET M4 in Fig. 7.
Gates of the MOSFETs M4a-1 and M4a-2 are commonly connected to the drain of the MOSFET M3. Sources of the MOSFETs M4a-1 to M4a-2 are commonly connected to the gate of the MOSFET M3. A drain of the MOSFET M4a-1 is directly connected to the constant voltage line applied with the voltage VDD. A drain of the MOSFET M4a-2 is connected to the power supply line applied with the voltage VDD through the MOSFET M4b-1.
Gates of the MOSFETs M4b-1 to M4b-3 are commonly connected to the drain of the MOSFET M3. Sources of the MOSFETs M4b-1 to M4b-j are commonly connected to the drain of the MOSFET M4a-2. Drains of the MOSFETs M4b-l to M4b-j are commonly connected to the power supply line applied with the voltage VDD.
The sum of the drain currents ID4b1 to ID4b-1 of the MOSFETs M4b-1 to M4b-j is equal to the drain current ID4@-2 of the MOSFET M4a-2. The sum of the drain current 1DAa-2 of the MOSFET M4a-2 and the drain current ID4al of the MOSFET M4a-1 is equal to the first output current ID1 of the MOS differential pair.2, or I1 There are the same advantages as those in the first embodiment.
There is an additional advantage that (a) this square-root circuit la can be realized under the condition that K1 = K2 = 1; in other words, each of the MOSFETs is formed by a unit MOSFET, and that (b) the necessary number of MOSFETs for the square-root circuit la is smaller than the third embodiment shown in Fig. 9.
FIFTH EMBODIMENT Fig. 11 shows a MOS linear transconductance amplifier according to a fifth embodiment of the present invention.
In this amplifier, each of the first and second square-root circuits la and ib has the circuit configuration shown in Fig. 7, where n = 0 and K2 = 4. A constant voltage source 4a supplying a constant voltage Vs is additionally provided between the coupled sources of the MOSFETs M3. M6, M7, and M10 and the ground.
The differential output current Al of the MOS linear trans conductance amplifier according to the fifth embodiment is expressed as the following equation (23).
There are the same advantages as those in the first embodiment SIXTH EMBODIMENT Fig. 12 shows a MOS linear transconductance amplifier according to a sixth embodiment of the present invention.
In Fig. 12, the first square-root circuit la is comprised of four n-channel MOSFETs Mull, M12, M13, and M14, and a constant current source 10 supplying a constant current Ib for driving the MOSFET M11. The second square-root circuit ib is comprised of four n-channel MOSFETs M15, M16, M17, and M18, and a constant current source 11 supplying a same constant current Ib for driving the MOSFET M15, Each of the MOSPETs Mli and M12 has a diode connection. A gate and a drain of the MOSFET Mli are connected to the power supply line applied with the voltage VDD through the constant current source 10. A source of the MOSFET Mli is connected to a gate and a drain of the MOSFET M12.
A gate of the MOSFET M13 is connected to the gate and the drain of the MOSFET M11. A source of the MOSFET M13 is connected to the drain of the MOSFET M1 of the differential pair 2. A drain of the MOSFET M13 serves as an output terminal of this transconductance amplifier from which the output current If is derived.
A gate of the MOSFET M14 is connected to the source of the MOSFET M13. A drain of the MOSFET M14 is connected to a drain of the MOSFET M17.
Each of the MOSFETs M15 and M16 has a diode connection. A gate and a drain of the MOSFET M15 are connected to the power supply line applied with the voltage VDD through the constant current source 11. A source of the MOSFET M15 is connected to a gate and a drain of the MOSFET M16.
A gate of the MOSFET M17 is connected to the gate and the drain of the MOSFET M15. A source of the MOSFET M17 is connected to the drain of the MOSFET M2 of the differential pair 2. A drain of the MOSFET M17 serves as another output terminal of this transconductance amplifier from which the output current I- is derived.
A gate of the MOSFET M18 is connected to the source of the MOSFET M17. A drain of the MOSFET M18 is connected to a drain of the MOSFET M13.
A constant voltage source 4a supplying a constant voltage VS is provided between the coupled sources of the MOSFETs M12, M14, M16, and M18 and the ground.
Next, the operation principle of the MOS linear transconductance amplifier according to the sixth embodiment is explained below.
First, the following equation (24) is established for the MOSFETs M11 and M12 from the above equation (2).
Ib = (VGS11 - VTH) = (VGS12 - VTH) (24) The following equations (25) and (26) are established for the MOSFETs M13 and M14 from the above equation (2), respectively.
ID13 = ID1 = (VGS13 - VTH) (25) ID14 = (VGS14 - VTH) (26) Further, the following equation (27) is established.
VGS11 + VGS12 = VGS13 + VGS14 (27) Solving the equations (24), (25). (26), and (27) gives the following equation (28).
Accordingly, from the equation (28), the drain current ID14 of the MOSFET M14 is expressed as follows.
In the same way as the drain current ID14 of the MOSFET M14, the drain currents ID17 and ID18 of the MOSFETs M17 and M18 are expressed as follows.
1Dl7 = 1D2 = (VGS17 - VTH) (30a)
Accordingly, using the equations (25), (29), (30a), and (30b), the differential output current At of the MOS linear transconductance amplifier is expressed by the following expression (31).
#I = I@ - I- = (ID13 + ID18) - (ID14 + ID17)
Thus, the differential output current Al of the MOS linear transconductance amplifier according to the sixth embodiment has a completely-linear characteristic with respect to the differential input voltage Vi.
Fig. 13 shows the transfer characteristic of the MOS linear transconductance amplifier according to the sixth embodiment, which was measured by the inventor under the following condition.
The MOS differential pair and the first and second square-root circuits la and ib were formed by a PA572T-type power MOS transistor array, where VTn was approximately 1.5 V.
The power supply voltage VDD was set as approximately 8.0 V.
The constant current (or, tail current) Io of the constant current sink 3 was set as approximately 12 mA. The common source voltage of the square-root circuits la and lb was set as 2.0 V. The bias current Ib for the MOSFETs Mll and M15 was set as approximately 3 mA, 4.5 mA, and 6 mA. The operating input voltage range of the MOS differential pair 2 was 1 Vpp when the constant or tail current Io was approximately 12mA.
It is seen from Fig. 13 that the differential output current hI has a completely-linear transfer characteristic within the specific range, and that the completely-linear transfer characteristic of the differential output current Al may be shifted according to the bias current Ib for the MOSFETs M11 and M15.
SEVENTH EMBODIMENT In the above-explained first to sixth embodiments, the transconductance is proportional to the square root of the bias current Ib, i.e., Ib. It is often preferred that the trans conductance is proportional to the bias current Ib itself from the view point of practical use. This linear characteristic of the bias current Ib is realized by simply supplying the bias current Ib to the corresponding bipolar transistor Q1 or MOSFET M3 or M13 through a squarer circuit.
Fig. 14 shows a bipolar squarer circuit used for a MOS linear trans conductance amplifier according to a seventh embodiment. This squarer circuit is a current-input and current-output type.
In Fig. 14, the bipolar squarer circuit is comprised of four pnp-type bipolar transistors Qli, Q12, Q13, and Q14, and a constant current source 31 supplying a constant current Ic to the transistor Q13.
Each of the transistors Oil and Q12 has a diode connection. An emitter of the transistor Q11 is connected to a power supply line applied with a power supply voltage Vcc.
A base and a collector of the transistor Qll are connected to an emitter of the transistor Q12.
The bias current 1b is sunk from a base and a collector of the transistor Q12.
An emitter of the transistor Q13 is connected to the ground. A base of the transistor Q13 is connected to the base and the collector of the transistor 012. A collector of the transistor Q13 is connected to the power supply line applied with the voltage Vcc through the constant current source 31.
A base of the transistor Q14 is connected to the base and collector of the transistor Q11 and the emitter of the transistor Q13. An emitter of the transistor Q14 is connected to the power supply line applied with the voltage Vcc.
An output current Isp of the squarer circuit has a square transfer characteristic with respect to the input bias current Ib.
The operation principle of the squarer circuit shown in Fig. 14 is explained below.
From Fig. 14, the following equations (33), (34), (35), and (36) are established.
VBE11 + VBE12 = VBE13 + VBE14 (33)
Solving the equation (36) using the equations (33), (34), and (35) gives the following equation (37).
2 @b ISQ = (37) IC As clearly seen from the equation (37), the output current- ISQ of the squarer circuit -shown in Fig. 14 is proportional to a square of the bias current Ib.
For example, if the squarer circuit shown in Fig. 14 is applied to the bipolar square-root circuit la shown in Fig.
4, the differential output current bI of the MOS linear transconductance amplifier is expressed as follows.
As seen from the equation (38), the differential output current Al is proportional to the bias current Ib.
EIGHTH EMBODIMENT Fig. 15 shows a MOS squarer circuit used for a MOS linear transconductance amplifier according to an eighth embodiment. This squarer circuit is a voltage-input and current-output type.
In Fig. 15, four n-channel MOSFETs M33, M34, M35, and M36, sources of which are coupled together and which are driven by a constant current Is sunk by a constant current sink 43, constitute a quadritail cell. An input voltage Vc is applied across gates of the MOSFETs M33 and M34. A half of the voltage Vc, i.e.. (Vc/2), is commonly applied to gates of the MOSFETs M35 and M36, where (Vc/2) is produced by two resistors 41 and 42 with a same resistance R.
Two p-channel MOSFETs M37 and M38 constitute a current mirror. Two p-channel MOSFETs M39 and M40 constitute a current mirror. Two n-channel MOSFETs M41 and M42 constitute a current mirror.
The sum of drain currents ID33 and ID34 of the MOSFETs M33 and M34, i.e., (ID33 + ID34), flows through the MOSFET M37.
Therefore, a drain current ID3B Of the MOSFET M38 is equal to (ID33 + ID34) The sum of drain currents ID35 and ID36 of the HOSFETs M35 and M36, i.e., (ID35 + ID36), flows through the MOSFET M39.
Therefore, a drain current ID40 of the MOSFET M40 is equal to (ID35 + ID36). This drain current ID40 Of the MOSFET M40 is equal to a drain current ID41 of the MOSFET M41 and a drain current ID42 of the MOSFET M42; i.e., ID41 = (ID35 + ID36) = ID42.
Therefore. an output current ISQ is expressed as the difference between the drain currents ID38 and ID42; i.e., ISQ = ID38 - ID42 = (ID33 + ID34) - (ID35 +ID36) Here, the following equations (39), (40), (41), and (42) are established from the circuit configuration in Fig.
*15.
VGS33=VGS35+ 2 (39) VC VGS34 = VGS35 - (40) 2 VGS35 = VGS36 (41) ID33 + ID34 + ID35 + ID36 = IS (42) If the equations (39), (40), (41), and (42) are solved by using the above-described equation (2), the output current ISQ is expressed in the following way.
ISQ = (ID33 + ID34) - (ID35 + ID36) = ###
As clearly seen from the equation (43). the output current Iso of the squarer circuit shown in Fig. 15 is proportional to a square of the input voltage Vc which corresponds to the bias current Ib.
For example, if the squarer circuit shown in Fig. 15 is applied to the MOS square-root circuit la shown in Fig. 7. the differential output current AI of the MOS linear transconductance amplifier is expressed as follows.
It is seen from the equation (44) that the differential output current Al is proportional to the input voltage Vc, i.e., the bias voltage Ib.
While the preferred forms of the present invention has been described, it is to be understood that modifications will be apparent to those skilled in the art without departing from the scope of the invention. The scope of the invention, therefore, is to be determined solely by the following claims.

Claims (12)

  1. CLAIMS 1. A MOS linear transconductance amplifier comprising: (a) a MOS differential pair of source-coupled first and second MOSFETs; (b) a first constant current source/sink connected to said coupled sources of said first and second MOSFETs and supplying/sinking a first constant current for driving said MOS differential pair; (c) a first square-root circuit connected to a drain of said first MOSFET; and (d) a second square-root circuit connected to a drain of said second MOSFET; wherein said MOS differential pair is applied with an input voltage at gates of said first and second MOSFETs and differentially outputs first and second output currents at respective drains of said first and second MOSFETs; and wherein said first square-root circuit is applied with said first output current of said MOS differential pair and outputs a third output current; and wherein said second square-root circuit is applied with said second output current of said MOS differential pair and outputs a fourth output current; and wherein an output current of said MOS linear transconductance amplifier is given by a difference between said third and fourth output currents.
  2. 2. An amplifier as claimed in claim 1, wherein each of said first and second square-root circuits has first, second, third, and fourth bipolar transistors, and a second constant current source/sink supplying/sinking a second constant current for driving the first transistor; and wherein a base and an emitter of said second transistor are connected to a collector and a base of said first transistor, respectively, and said second transistor is driven by a corresponding one of said first and second output currents of said MOS differential pair; and wherein a base of said third transistor is connected to said base of said second transistor. and wherein a base and a collector of said fourth transistor are connected to said emitter of said third transistor, and an emitter of said fourth transistor is connected to said emitter of said first transistor; and wherein a collector current of said third transistor serves as a corresponding one of said third and fourth output currents.
  3. 3. An amplifier as claimed in claim 2, wherein said second transistor has anFemitter area K times as large as said first, third, and fourth transistors, where K is a constant greater than unity.
  4. 4. An amplifier as claimed in claim 2, or claim 3, wherein said second constant current source/sink is designed so that said second constant current is variable.
  5. 5. An amplifier as claimed in claim 1, wherein each of said first and second square-root circuits has third, fourth, fifth, and sixth MOSFETs, and a second constant current sourceXsink supplying/sinking a second constant current for driving said third MOSFET; and wherein a gate and a source of said fourth MOSFET are connected to a drain and a gate of said third MOSFET, respectively, and said fourth MOSFET is driven by a corresponding one of said first and second output currents of said MOS differential pair; and wherein a gate of said fifth MOSFET is connected to said gate of said fourth MOSFET; and wherein a gate and a drain of said sixth MOSFET are connected to said source of said fifth MOSFET, and a source of said sixth MOSFET is connected to said source of said third MOSFET; and wherein a drain current of said fifth MOSFET serves as a corresponding one of said third and fourth output currents.
  6. 6. An amplifier as claimed in claim 5, wherein said fourth MOSFET has a gate-width to gate-length ratio K1 times as large as said third MOSFET, and said fifth and sixth MOSFETs have a gate-width to gate-length ratio K2 times as large as said third MOSFET, where K1 and K2 are constants greater than unity.
  7. An An amplifier as claimed in claim 5 or claim 6, wherein said second constant current source/sink is designed so that said second constant current is variable.
  8. 8. An amplifier as claimed in claim 1, wherein each of said first and second square-root circuits further comprises a first set of n serially-connected MOSFETs and a second set of n serially-connected MOSFETs, where n is an integer equal to or greater than unity; wherein each of said first set of n seriallyconnected MOSFETs has a diode connection, and a drain and a gate of a first one of said first set of n MOSFETs are connected to said source of said third MOSFET; and wherein each of said second set of n seriallyconnected MOSFETs has a diode connection, and a drain and a gate of a first one of said second set of n MOSFETs are connected to said source of said sixth MOSFET: and wherein said source of said third MOSFET is connected to said source of said sixth MOSFET through said first set of n MOSFETs and said second set of n MOSFETs.
  9. 9. An amplifier as claimed in claim 1, wherein each of said first square-root circuit has third, fourth, fifth, and sixth MOSFETs1 and a second constant current source/sink supplylng/sinking a second constant current for driving said third MOSFET, and said second-square-root circuit has seventh, eighth, ninth, and tenth MOSFETs, and a third constant current source/sink supplying/sinking a third constant current for driving said seventh MOSFET; and wherein said third. fourth, seventh, and eighth MOSFETs are diode-connected; and wherein a gate and a drain of said third MOSFET are connected to said second constant current source/sink, a source of said third MOSFET is connected to a gate and a drain of said fourth MOSFET; and wherein a source of said fourth MOSFET is connected to a source of said sixth MOSFET; and whereon a gate of said fifth MOSFET is connected to said gate of said first MOSFET; a drain of said fifth MOSFET serves as an output terminal from which said third output current is derived; and a source of said fifth MOSFET is connected to a corresponding one of said drains of said first and second MOSFETs; and wherein a gate of said sixth MOSFET is connected to said source of the fifth NOSFET; and wherein a gate and a drain of said seventh MOSFET are connected to said third constant current source/sink, and a source of said seventh MOSFET is connected to a gate and a drain of said eighth MOSFET: and wherein a source of said eighth MOSFET is connected to a source of said tenth MOSFET; and wherein a gate of said ninth MOSFET is connected to said gate of said second MOSFET; a drain of said ninth MOSFET serves as an output terminal from which said fourth output current is derived; and a source of said ninth MOSFET is connected to a corresponding one of said drains of said first and second MOSFETs; and wherein a gate of said tenth MOSFET is connected to said source of said ninth MOSFET; and wherein a drain of said sixth MOSFET is connected to said drain of said seventh MOSFET, and a drain of said tenth MOSFET is connected to said drain of said fifth MOSFET.
  10. 10. An amplifier as claimed in claim 2, wherein said output current of said MOS linear trans conductance amplifier has a linear characteristic with respect to said second constant current.
  11. 11. An amplifier as claimed in claim 5, wherein said output current of said MOS linear trans conductance amplifier has a linear characteristic with respect to said second constant current.
  12. 12. A MOS linear transconductance amplifier substantially as herein described, with reference to Figures 2 to 15 of the accompanying drawings.
GB9803348A 1997-02-17 1998-02-17 Adjustable linearised MOS transconductance amplifier using a source-coupled pair and square-root circuits Withdrawn GB2322247A (en)

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Publication number Priority date Publication date Assignee Title
GB2325341A (en) * 1997-03-28 1998-11-18 Nec Corp A composite transistor for a current squarer and analog multiplier
CN100403205C (en) * 2001-11-15 2008-07-16 精工电子有限公司 Voltage regulator

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GB9803348D0 (en) 1998-04-15
CN1191414A (en) 1998-08-26
JPH10229311A (en) 1998-08-25
AU5534298A (en) 1998-08-20

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