CN1191414A - Tunable MOS linear transconductance amplifier - Google Patents

Abstract

The present invention provides a MOS linear transconductance amplifier, which can realize the complete linear conversion characteristic and the transconductance tune. The amplifier comprises (a) a MOS differential pair of a first MOSFET and a second MOSFET with a linked source cathode, (b) a first constant current source/exchanger which is linked with the first MOSFET and the second MOSFET with the linked source cathode and provides/exchanges a first constant current used for driving the MOS differential pair, (c) a first square root circuit which is linked with the drain electrode of the first MOSFET and (d) a second square root circuit which is linked with the drain electrode of the second MOSFET.

Description

Tunable MOS linear transconductance amplifier

The present invention relates to a kind of linear transconductance amplifier, especially have the linear transconductance amplifier of mos field effect transistor (MOSFET) differential pair, it is linear operation and tuning mutual conductance fully.

In recent years, linear transconductance amplifier is generally acknowledged as the basic functional blocks in the analog signal application.Especially, the demand for metal-oxide semiconductor (MOS) (MOS) linear transconductance amplifier that can tuning mutual conductance becomes more and more stronger.

Usually, Chang Gui MOS linear transconductance amplifier has two transistors of floating of the square-law transfer characteristic formation of utilizing MOSFET.The output current of this conventional MOS linear transconductance amplifier is two differences of floating between transistorized two output currents.

The linearity of mutual conductance is determined by equation (1) in conventional MOS linear transconductance amplifier.

β(V _i+V _TH) ²-β(V _i-V _TH) ²＝4βV _TH·V _i (1)

In equation (1), Vi is the difference input voltage, V _THBe the threshold voltage of MOSFET, β is the transconductance parameters of MOSFET.Transconductance parameters β is following definite: $\mathrm{\&beta;}=\frac{{\mathrm{\&mu;<figure-callout\; id="2"\; label="C\; OX"\; filenames="A9810062400302.png,A9810062400321.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{OX}}}{2}\&CenterDot;\frac{W}{L}$ Here μ is the mobility of charge carrier rate, and Cox is the gate oxide capacitance of each unit are, and W and L are respectively grid level width and the grid lengths of MOSFET.

Equation (1) is set in this case and is provided, that is, (a) feature of all MOSFET is consistent, and (b) channel length modulation and body effect can be ignored, (c) the drain current I of MOSEFT _DAccording to grid and the source voltage V of square-law characteristic with it _GSChange; That is, set up following equation (2).

I _D＝β(V _GS-V _TH) ² (2)

Fig. 1 shows an example of this conventional MOS linear transconductance amplifier.This amplifier is one piece of article publishing on August 29th, 1996, the IEE electronics is collected mail, the 32nd volume, No.18. disclose in the 1629-1630 page or leaf in, its exercise question is " the independent control of the transadmittance gain and the input range of linearity in the MOS linear transconductance amplifier ", is shown by J.MahattanakulC.Toumazou.

A known fact is described in this article, promptly, electric current with square-law characteristic is by square root circuit shown in Figure 1, bipolar square root circuit and MOS square root circuit shown in Fig. 2, and the MOS linear transconductance amplifier of use MOS differential pair and linearizing with reference to the Weir grandson current mirror institute of Fig. 3.

Conventional MOS trsanscondutance amplifier shown in Figure 1 has following structure.

Two n channel mosfet M101 and M102 constitute a MOS differential pair.Three n channel mosfet M103, M107 and M109 constitute one first Weir grandson current mirror circuit.Three n channel mosfet M104, M108 and M110 constitute one second Weir grandson current mirror circuit.Two n channel mosfet M105 and M106 are as floating transistor.

The source electrode of MOSFET M101 and M102 links together, and by subsideing constant current I _SSA constant-current converter be added with supply voltage V _SSPower line connect.The grid of MOSFET M101 and M102 is added with the first and second input voltage V respectively _In1And V _In2, V here _In1-V _In2=V _iThe drain electrode of MOSFET M101 and M102 is connected the source electrode of MOSFET M105 and M106 respectively.

The source electrode of MOSFET M103 is connected with ground.The grid of MOSFET M103 is connected with drain electrode with the grid of MOSFET M109.The drain electrode of MOSFET M103 is through subsideing constant current I _OA constant-current converter be added with supply voltage V _DDA power line connect.

The source electrode of M109 is connected with ground.Grid and the drain electrode of MOSFET M109 link together, and are connected with the source electrode of MOSFET M107.

The grid of MOSFET M107 is connected with the drain electrode of MOSFET M103 and the grid of MOSFET M105.The drain electrode of MOSFET M107 is connected with the drain electrode of MOSFET M106 at the Y point.

The source electrode of MOSFET M104 is connected with ground.The grid of MOSFET 104 is connected with drain electrode with the grid of MOSFETM110.The drain electrode of MOSFET M104 is through subsideing constant current I _OPower pack be added with supply voltage V _DDPower line connect.

The source electrode of MOSFET M110 is connected with ground.The grid of MOSFET M110 links together with drain electrode and is connected with the source electrode of MOSFET M108.

The grid of MOSFET M108 is connected with the drain electrode of MOSFET M104 and the grid of MOSFET M106.The drain electrode of MOSFET M108 is connected with the drain electrode of MOSFET M105 at the X point.

The operation principle of this conventional MOS linear transconductance amplifier will be described below, and it is that analysis according to the inventor provides.

Here, set all MOSFET M101, M102, M103, M104, M105, M106, M107, M108, M109 and M110 and be operated in saturation area.Also have, the drain current of MOSFET M101 to M110 is defined as I respectively _D101, I _D102, I _D103, I _D104, I _D105, I _D106, I _D107, I _D108, I _D109, I _D110

So, the equation (2) above using is set up following equation (3a) and (3b). $I_{\mathrm{<figure-callout\; id="101"\; label="D"\; filenames="A9810062400291.png,A9810062400311.png"\; state="\{\{state\}\}">D</figure-callout>}101}=I_{\mathrm{<figure-callout\; id="105"\; label="D"\; filenames="A9810062400351.png"\; state="\{\{state\}\}">D</figure-callout>}105}=\frac{1}{2}\{I_{\mathrm{SS}}+\mathrm{\&beta;}{V}_i\sqrt{\frac{{2I}_{\mathrm{SS}}}{\mathrm{\&beta;}}-{V_i}^2}\}---\left(3a\right)$ $\left[\right|V_i|\&le;\sqrt{\frac{I_{\mathrm{SS}}}{\mathrm{\&beta;}}}]$ $I_{\mathrm{<figure-callout\; id="102"\; label="D"\; filenames="A9810062400301.png,A9810062400321.png"\; state="\{\{state\}\}">D</figure-callout>}102}=I_{D106}=\frac{1}{2}\{I_{\mathrm{SS}}-\mathrm{\&beta;}{V}_i\sqrt{\frac{{2I}_{\mathrm{SS}}}{\mathrm{\&beta;}}-{V_i}^2}\}---\left(3b\right)$ $\left[\right|V_i|\&le;\sqrt{\frac{I_{\mathrm{SS}}}{\mathrm{\&beta;}}}]$

Because MOSFET is M103, M107 and the combination of M109 and the combination of MOSFET M104, M108 and M110 have constituted Weir grandson current mirror circuit respectively, so provide equation (4).

I _D103＝I _D107＝I _D109＝I _D104＝I _D108＝I _D110＝I _O (4)

Therefore, if the electric current that flow through X and Y are ordered is defined as I ₁₀₁-I ₁₀₂, so at the output current I of the conventional MOS linear transconductance amplifier shown in Fig. 1 _OutProvide by equation (5).

I _OUT＝I ₁₀₁-I ₁₀₂＝(I _D105+I _D108)-(I _D106+I _D107)

(5) $=\mathrm{\&beta;}{V}_i\sqrt{\frac{{2I}_{\mathrm{SS}}}{\mathrm{\&beta;}}{V_i}^2}\left[\right|V_i|\&le;\sqrt{\frac{I_{\mathrm{SS}}}{\mathrm{\&beta;}}}]$

Equation (5) is identical with the known difference output current of simple MOS differential pair.Therefore, there is a problem in the conventional MOS linear transconductance amplifier shown in Fig. 1, and linear transformation characteristic completely promptly can not be arranged.

Conventional amplifier shown in Figure 1 also has another problem, that is, when the hold amplifier characteristic was constant, transconductance value was nonadjustable.

The purpose of this invention is to provide a kind of MOS linear transconductance amplifier of realizing complete linear transformation characteristic.

Another object of the present invention provides a kind of in the indeclinable while of hold amplifier characteristic, MOS linear transconductance amplifier that can tuning mutual conductance.

To make those skilled in the art that the purpose of special statement such as above-mentioned purpose and other is had clearer understanding by following description.

MOS linear transconductance amplifier according to the present invention comprises: (a) the MOS differential pair of first and second MOSFET of source electrode connection, (b) the first constant-current source/converter that is connected with the source electrode that is connected of first and second MOSFET, it provides/subsides first constant current for the driven MOS differential pair, (c) first square root circuit that is connected with the drain electrode of a MOSFET, and second square root circuit that (d) is connected with the drain electrode of the 2nd MOSFET.

Grid at first and second MOSFET applies an input voltage to the MOS differential pair, exports first and second output currents in the drain electrode difference separately of first and second MOSFET.

First square root circuit is applied in first output current of MOS differential pair, and its output and first output current have the 3rd output current of square root transfer characteristic.

Second square root circuit is applied in second output current of MOS differential pair, and its output and second output current have the 4th output current of square root transfer characteristic.

The output current of MOS linear transconductance amplifier is that the difference by third and fourth output current provides.

For according to MOS linear transconductance amplifier of the present invention, first and second output currents of MOS differential pair are added to first and second square root circuits respectively, this MOS differential pair is that identical transfer characteristic is arranged with respect to input voltage, just input voltage polarity difference.

On the other hand, the 3rd output current has a square root transfer characteristic with respect to first output current, and the 4th electric current has a square root transfer characteristic with respect to second output current.

Therefore, the difference between the 3rd of first and second square root circuits the and second output current is the characteristic of a complete linear transformation.This determines that by equation (6) a is a parameter here, and X is a variable. $\sqrt{a+\sqrt{2}x\sqrt{a-\frac{1}{2}{x}^2}}-\sqrt{a-\sqrt{2}x\sqrt{a-\frac{1}{2}{x}^2}}=\sqrt{2}x---\left(6\right)$

The difference output current of MOS linear transconductance amplifier is represented on the left side of equation (6); In other words, i.e. difference between third and fourth output current of first and second square root circuits.Input voltage is represented on the right side of equation (6).

In most preferred embodiment according to amplifier of the present invention, in first and second square root circuits each all has the first, second, third and the 4th bipolar transistor and provides/subside second constant current to be used to drive the second constant-current source/converter of the first transistor.

The base stage of transistor seconds is to be connected with base stage with the collector electrode of the first transistor respectively with emitter.Transistor seconds is by a corresponding driving in first and second output currents of MOS differential pair.

The 3rd transistorized base stage is connected with the base stage of transistor seconds.

The 4th transistorized base stage is connected with the 3rd transistorized emitter with collector electrode.The 4th transistorized emitter is connected with the emitter of the first transistor.

The 3rd transistorized collector current is as in third and fourth output current corresponding one.

In the case, to be preferably designed as second constant current be variable to second constant-current source/converter.The advantage that is produced is that the mutual conductance of MOS linear transconductance amplifier also is variable; In other words, mutual conductance is adjustable.

In according to another most preferred embodiment of the present invention, each of first and second square root circuits all has the 3rd, the 4th, the 5th and the 6th MOSFET and is used to drive second constant-current source/converter that the 3rd MOSFET provided/absorbed second constant current.

The grid of the 4th MOSFET is connected respectively with the drain and gate of the 3rd MOSFET with drain electrode.The 4th MOSFET is by the corresponding driving in first and second output currents of MOS differential pair.

The grid of the 5th MOSFET is connected with the grid of the 4th MOSFET.

The grid of the 6th MOSFET is connected with the source electrode of the 5th MOSFET with drain electrode.The source electrode of the 6th MOSFET is connected with the source electrode of the 3rd MOSFET.

The drain current of the 5th MOSFET is as in third and fourth output current corresponding one.

In the case, preferably to be designed to second constant current be variable to second constant-current source/converter.The advantage that is increased is that the mutual conductance of MOS linear transconductance amplifier is variable; In other words, mutual conductance is adjustable.

In another most preferred embodiment of the present invention, each in first and second square root circuits also has first group of n MOSFET that is connected in series and second group of n MOSFET that is connected in series, and wherein n is equal to or greater than one integer.

Among first group of n MOSFET that is connected in series each has a diode to connect.The drain and gate of first MOSFET of first group of n MOSFET is connected with the source electrode of the 3rd MOSFET.

Among second group of n MOSFET that is connected in series each has a diode to connect.The drain and gate of first MOSFET of second group of n MOSFET is connected with the source electrode of the 6th MOSFET.

The source electrode of the 3rd MOSFET is connected with the source electrode of the 6th MOSFET with second group of n MOSFET through first group of n MOSFET.

In the most preferred embodiment of another amplifier of the present invention, first square root circuit has the 3rd, the 4th, the 5th and the 6th MOSFET, and be used to drive second constant-current source/converter that the 3rd MOSFET provided/absorbed second constant current, and second square root circuit has the 7th, the 8th, the 9th and the tenth MOSFET, and is used to drive the 3rd constant-current source/converter that the 7th MOSFET provided/absorbed the 3rd constant current.

Three, the 4th, the 7th is that diode is connected with the 8th MOSFET.

The grid of the 3rd MOSFET is connected with second constant-current source/converter with drain electrode.The source electrode of the 3rd MOSFET is connected with drain electrode with the grid of the 4th MOSFET.

The source electrode of the 4th MOSFET is connected with the source electrode of the 6th MOSFET.

The grid of the 5th MOSFET is connected with the grid of a MOSFET.The drain electrode of the 5th MOSFET is as an output of therefrom drawing the 3rd output current.Corresponding one is connected in the drain electrode of the source electrode of the 5th MOSFET and first and second MOSFET.

The 6th MOSFET is connected with the source electrode of the 5th MOSFET.

The grid of the 7th MOSFET is connected with the 3rd constant-current source/converter with drain electrode.The utmost point of the 7th MOSFET is connected with drain electrode with the grid of the 8th MOSFET.

The 8th MOSFET is connected with the source electrode of source electrode with the tenth MOSFET.

The grid of the 9th MOSFET is connected with the grid of the 2nd MOSFET.The drain electrode conduct of the 9th MOSFET is from wherein drawing an output of the 4th output current.Corresponding one in the drain electrode of the source electrode of the 9th MOSFET and first and second MOSFET is connected.

The grid of the tenth MOSFET is connected with the source electrode of the 9th MOSFET.

The 6th MOSFET is connected with the drain electrode of the 7th MOSFET with drain electrode.The drain electrode of the tenth MOSFET is connected with the drain electrode of the 5th MOSFET.

In according to another most preferred embodiment of the present invention, the output current of MOS linear transconductance amplifier has the linear characteristic suitable with second constant current.

For implementing the present invention more easily, now describe with reference to the accompanying drawings.

Fig. 1 is the circuit diagram of conventional MOS linear transconductance amplifier.

Fig. 2 is the circuit diagram of the basic structure of an expression MOS linear transconductance amplifier of the present invention.

Fig. 3 is the curve chart of the transfer characteristic of expression MOS linear transconductance amplifier of the present invention.

Fig. 4 is the circuit diagram that is used for a bipolar square root circuit of a MOS linear transconductance amplifier of the present invention.

Fig. 5 is the circuit diagram according to a MOS linear transconductance amplifier of the first embodiment of the present invention, and it comprises two bipolar square root circuits as shown in Figure 4.

Fig. 6 shows the curve chart according to the transfer characteristic that tests out of a MOS linear transconductance amplifier of the first embodiment of the present invention.

Fig. 7 is the circuit diagram that is used for a MOS square root circuit of a MOS linear transconductance amplifier of the present invention.

Fig. 8 is the circuit diagram of a MOS linear transconductance amplifier according to a second embodiment of the present invention, and it comprises two MOS square root circuits shown in Fig. 7.

Fig. 9 is the circuit diagram that is used for according to a MOS square root circuit of a MOS linear transconductance amplifier of third embodiment of the invention.

Figure 10 is the circuit diagram that is used for according to a MOS square root circuit of a MOS linear transconductance amplifier of the fourth embodiment of the present invention.

Figure 11 is the circuit diagram according to a MOS linear transconductance amplifier of fifth embodiment of the invention, and it comprises two MOS square root circuits as shown in Figure 7, wherein n=0 and K ₂=4.

Figure 12 is the circuit of a MOS linear transconductance amplifier according to a sixth embodiment of the invention

Figure 13 is the curve chart of the transfer characteristic that tests out of a MOS linear transconductance amplifier according to a sixth embodiment of the invention.

Figure 14 is the circuit diagram of a bipolar square root circuit of a MOS linear transconductance amplifier according to a seventh embodiment of the invention.

Figure 15 is the circuit diagram that is used for according to a MOS squaring circuit of a MOS linear transconductance amplifier of the eighth embodiment of the present invention.

Most preferred embodiment of the present invention is described below with reference to accompanying drawings.

Has as shown in Figure 2 a basic structure according to a MOS linear transconductance amplifier of the present invention.

In Fig. 2, this MOS linear transconductance amplifier has the differential pair of being made up of the MOSFET M1 of source electrode connection and M2.Be connected with the source electrode that is connected of MOSFET M1 and M2 in order to drive this MOS differential pair, and provide/absorb constant current I _OFirst constant-current source/converter 3, the first square root circuit 1a that is connected with the drain electrode of MOSFET M1 and the second square root circuit 1b that is connected with the drain electrode of MOSFET M2.

This MOS differential pair 2 be on the grid of MOSFET M1 and M2 by difference add input voltage V ₁, and at MOSFET M1 and M2 drain electrode difference ground output first and second output currents (that is the drain current of MOSFET M1 and M2) I separately _D1And I _D2

The first square root circuit 1a has been provided the first output current I of MOS differential pair 2 _D2, it exports second electric current I ⁺=(I _D1) ^1/2

The second square root circuit 1b has been provided the second output current I of MOS differential pair 2 _D2, it exports the 4th output current I-=(I _D2) ^1/2

The output current Δ I of this MOS linear transconductance amplifier is by the third and fourth output current I ⁺And I ^-Between difference provide; That is,

For according to MOS linear transconductance amplifier of the present invention, the first and second output current I of MOS differential pair 2 _D1And I _D2Added to first and second square root circuit 1a and the 1b respectively, this electric current I _D1And I _D2Has identical square-law characteristic, just the polarity difference.

Therefore, the third and fourth output current I of the first and second square root circuit 1a and 1b ⁺And I ^-Between difference DELTA I be fully linear transfer characteristic.This is guaranteed by the equation of front (6).

Specifically, if constant a and variable X are respectively by 1 and [V in equation (6) _i/ (I _O/ β) ^1/2] replace the equation (7) below so just having provided. $\sqrt{I_{D1}}-\sqrt{{\mathrm{<figure-callout\; id="2"\; label="I\; D"\; filenames="A9810062400302.png,A9810062400321.png"\; state="\{\{state\}\}">I</figure-callout>}}_D}=\mathrm{\&Delta;I}=\sqrt{\mathrm{\&beta;}}{V}_i\left[\right|V_i|\&le;\sqrt{\frac{I_O}{\mathrm{\&beta;}}}]---\left(7\right)$

From equation (7), can find out the difference output current Δ I=(I of MOS linear transconductance amplifier of the present invention ⁺-I ^-) be difference input voltage V _iLinear function.This just means that this trsanscondutance amplifier has the transfer characteristic of complete linearity.

Fig. 3 shows the third and fourth output current I of the first and second square root circuit 1a and 1b ⁺=(I _D1) ^1/2. and I ^-[=(I _D2) ^1/2] transfer characteristic, and the difference output current Δ I[=(I of this amplifier _D1) ^1/2-(I _D2) ^1/2].

As can be seen from Figure 3, the 3rd output current I ⁺[=(I _D1) ^1/2] square-law characteristic is arranged, and the 4th output current I ^-[=(I _D2) ^1/2] polarity and the 3rd output current I arranged ⁺Opposite one identical square-law characteristic is created in the linear characteristic fully of difference output current Δ I.

First embodiment

Fig. 5 shows the MOS linear transconductance amplifier according to first embodiment of the invention, and circuit structure shown in Figure 4 therein is used as each first and second square root circuits 1a and 1b.

Fig. 4 shows the example of the first square root circuit 1a.Because the second square root circuit 1b has the identical structure with the first square root circuit 1a, so will omit to the description of the second square root circuit 1b.

In Fig. 4, the first square root circuit 1a provides the second constant current I by four npn type bipolar transistor Q1, Q2, Q3 and Q4, for driving transistors Q1 _bOne second constant-current source 10 and constant voltage V is provided _E Constant pressure source 4 form.Transistor Q2 has a K doubly to the emitter area of transistor Q1, Q3 and Q4, and K is the constant (that is K 〉=1) greater than 1 here.

The emitter of transistor Q1 and Q4 links together, and is connected with ground through constant pressure source 4.The base stage of transistor Q1 is connected with the emitter of transistor Q2.The collector electrode of transistor Q1 is through constant-current source 10 and supply voltage V is provided _CCPower line connect.Transistor Q1 is by the constant-current bias I from second constant-current source 10 _bDrive.

The base stage of transistor Q2 is connected with the collector electrode of transistor Q1.The collector electrode of transistor Q2 be added with voltage V _CCPower line connect.The emitter of transistor Q2 is connected with the drain electrode of the MOSFET M1 of MOS differential pair 2.Transistor Q2 is the electric current I by MOS differential pair 2 ₁(that is first output current I, _D1) drive.

The base stage of transistor Q3 is connected with the base stage of transistor Q2 and the collector electrode of transistor Q1.The collector electrode of transistor Q3 is as drawing the 3rd output current I ⁺An output.

Base stage and the collector electrode of transistor Q4 link together; In other words, transistor Q4 is that a diode connects.The base stage of the connection of transistor Q4 is connected with the emitter of collector electrode with transistor Q3.

The operation principle of bipolar square root circuit 1a shown in Figure 4 will be described below.

Usually, the collector current I of bipolar transistor _cWith its base stage to the voltage V of emitter _BEThe characteristic that one index law is arranged.Therefore, set up following equation (8). $I_C=I_S\{\exp \left(\frac{V_{\mathrm{BE}}}{V_T}\right)-1\}---\left(8\right)$

In equation (8), I _SBe the saturation current of bipolar transistor, V _TBe defined as V _TThe thermal voltage of=KT/9, wherein K is a Boltzmann constant, and T is the absolute temperature of Kelvin, and q is the electric weight of electronics.

When bipolar transistor is to be operated in base stage to emitter voltage V _BEWhen being the operate as normal district of about 600mV, the exponential part " exp (V in equation (8) _BE/ V _T) " value of approximate e10 arranged.Therefore, constant component " 1 " can be left in the basket.Therefore, equation (8) can be approximately following equation (9). $I_C=I_S\exp \left(\frac{V_{\mathrm{BE}}}{V_T}\right)---\left(9\right)$

By the loop that is made of transistor Q1, Q2, Q3 and Q4 is used Kirchhoff's second law, be the equation (10) below the first square root circuit 1a has set up, wherein V _BE1, V _BE2, V _BE3And V _BE4The base stage that is transistor Q1, Q2, Q3 and Q4 respectively is to emitter voltage.

V _BE1+V _BE2＝V _BE3+V _BE4 (10)

Base stage is to emitter voltage V _BE1, V _BE2, V _BE3And V _BE4Represented as following equation (11), (12) and (13). $V_{\mathrm{BE}1}=V_T\ln \left(\frac{I_b}{I_S}\right)---\left(11\right)$ $V_{\mathrm{BE}2}=V_T\ln \left(\frac{{\mathrm{<figure-callout\; id="1"\; label="I\; D"\; filenames="A9810062400302.png"\; state="\{\{state\}\}">I</figure-callout>}}_D}{{\mathrm{KI}}_S}\right)---\left(12\right)$ $V_{\mathrm{BE}3}=V_{\mathrm{BE}4}=V_T\ln \left(\frac{I^{+}}{I_S}\right)---\left(13\right)$

By separating equation (13) with equation (10), (11) and (12), the 3rd output current I of the first square root circuit 1a ⁺(14a) provides by equation. $I^{+}=\sqrt{\frac{I_b{I}_{D1}}{K}}---\left(14a\right)$

Equation (14a) is represented output current I ⁺Be proportional to the square root or the first output current I of the drain current that applies _D1In other words, circuit structure shown in Figure 4 has provided the square root function with respect to its input signal.

Below, the MOS linear transconductance amplifier according to the first embodiment of the present invention is described.

As shown in Figure 5, the second square root circuit 1b provides identical constant current I by four npn type bipolar transistor Q5, Q6, Q7 and Q8 and for driving transistors Q5 _bThe 3rd constant-current source form.Constant pressure source 4 is that the second square root circuit 1b is shared.

The emitter of transistor Q5 and Q8 links together, and is connected with ground through constant pressure source 4.The base stage of transistor Q5 is connected with the emitter of transistor Q6.The collector electrode of transistor Q5 is through constant-current source 11 and apply voltage V _CcPower line connect.Transistor Q5 is by the constant-current bias I from the 3rd constant-current source 11 _bDrive.

The base stage of transistor Q6 is connected with the collector electrode of transistor Q5.The collector electrode of transistor Q6 with apply voltage V _CcPower line connect.The emitter of transistor Q6 is connected with the drain electrode of the MOSFET M2 of MOS differential pair 2.Transistor Q6 is the electric current I by M0 differential pair 2 ₂(that is second output current I, _D2) drive.

The base stage of transistor Q7 is connected with the base stage of transistor Q6 and the collector electrode of transistor Q5.The collector electrode of transistor Q7 is therefrom drawn the 4th output current I ^-Another output.

Base stage and the collector electrode of transistor Q8 link together; In other words, transistor Q8 is that diode connects.The base stage of the connection of transistor Q8 is connected with the emitter of collector electrode with transistor Q7.

As above illustrated, the 3rd output current I of the first square root circuit 1a ⁺(14a) provides by equation.With with the same way as of the first square root circuit 1a, the 4th output current I of the second square root circuit 1b ^-Be to provide by the equation that is similar to top equation (14a) (14b). $I^{-}=\sqrt{\frac{I_b{I}_{D2}}{K}}---\left(14b\right)$

If with equation (14a) and (14b) equation of substitution front (7), the difference output current Δ I according to the MOS linear transconductance amplifier of first embodiment of the invention is provided by equation (15) so. $\mathrm{\&Delta;I}=I^{+}-I^{-}=\sqrt{\frac{I_b{I}_{D1}}{K}}-\sqrt{\frac{I_b{I}_{D2}}{K}}$ $=\sqrt{\frac{{\mathrm{\&beta;I}}_b}{K}}{V}_i\left[\right|V_i|\&le;\sqrt{\frac{I_O}{\mathrm{\&beta;}}}]---\left(15\right)$

Can find out from equation (15), be proportional to difference input voltage V according to the difference output current Δ I of the MOS linear transconductance amplifier of first embodiment of the invention _iIn other words, the MOS linear transconductance amplifier according to first embodiment of the invention has with respect to difference input voltage V _iLinear fully transfer characteristic.

In addition, can find out from equation (15), be variable by the bias current transconductance value that changes transistor Q1 and Q5.This means that circuit structure shown in Figure 5 realized a kind of adjustable MOS linear transconductance amplifier.

In addition, the ratio K of the emitter area by changing transistor Q2 can adjust transconductance value.

Fig. 6 shows the transfer characteristic according to the MOS linear transconductance amplifier of first embodiment of the invention, and it is that the inventor tests under the following conditions.

MOS differential pair 2 is to be made of-μ PA572T transistor npn npn array.The first and second bipolar square root circuit 1a and 1b are that the CTW4 transistor npn npn array of the testing element group (TEG) made by CHS technology constitutes.Supply voltage V _CcBe set to 5.0V.The constant current of constant-current converter 3 (or tail current) I _OBe set at about 12mA.The common emitter voltage of square root circuit 1a and 1b is made as 2.0V.Emitter area ratio K is made as 9.The bias current I of transistor Q1 and Q5 _bBe set at and be similar to 9 μ A, 110 μ A and 140 μ A.As constant or tail current I _OWhen being about 12mA, the work input voltage range of MOS differential pair 2 is 1V _P-P

As can be seen from Figure 6, in specific scope, difference output current Δ I has the transfer characteristic of complete linearity, and according to the bias current I of transistor Q1 and Q5 _b, this complete linear transformation characteristic can move.

Second embodiment

Fig. 8 shows the MOS linear transconductance amplifier according to second embodiment of the invention, and circuit structure shown in Figure 7 therein is used as each first and second square root circuits 1a and 1b.

Fig. 7 shows the embodiment of the first square root circuit 1a.Because the second square root circuit 1b has the identical structure with the first square root circuit 1a, therefore omitted description here to the second square root circuit 1b.

In Fig. 7, the first square root circuit 1a is by 4 n channel mosfet M ₃, M ₄, M ₅And M ₆, one is driven MOS FET M ₃The second constant current I is provided _bThe n channel mosfet M of n series connection of 10, the first group 21 of second constant-current source _21-1To M _21-n, and the n channel mosfet M of second group 22 n series connection _22-1To M _22-nMM, wherein n 〉=1.

MOSFET M ₄Grid width W and the ratio (W/L) of grid length L MOSFET M is arranged ₃N MOSFET M with first group 21 _21-1To M _21-nK ₁Doubly, K here ₁Be a constant (that is K, greater than 1 ₁〉=1).MOSFET M ₅And M ₆N MOSFETM with second group 22 _22-1To M _22-nHas M for MOSFET ₃N MOSFET M with first group 21 _21-1To M _21-nK ₂Identical ratio (W/L) doubly, wherein K ₂Be a constant (that is K, greater than 1 ₂〉=1).

The source electrode of MOSFET M3 is connected with ground through first group 21 n MOSFET M21-1 to M21-n, and the source electrode of MOSFET M6 is connected with ground through second group 22 n MOSFET M22-1 to M22-n.

Different with the dipolar configuration of first embodiment shown in Figure 4, be not provided for any constant pressure source that voltage level is adjusted.This is because the MOSFET M22-1 to M22-n that the MOSFET M21-1 to M21-n of n diode of first group 21 connection is connected with second group 22 n diode is respectively the constant pressure source of MOSFET M3 and M6.

The grid of MOSFET M3 is connected with the source electrode of MOSFET M4.The drain electrode of MOSFET M3 is through constant-current source 10 and supply voltage V is provided _DDPressure-wire connect.MOSFET M3 is by from second

The grid of MOSFET M5 is connected with the grid of MOSFET M4 and the drain electrode of MOSFET M3, and the drain electrode of MOSFETM5 is as drawing the 3rd output current I ⁺An output.

The grid of MOSFET M6 and a drain electrode link together; In other words, MOSFET M6 is that a diode connects.The grid of the connection of MOSFET M6 is connected with the source electrode of drain electrode with MOSFET M5.

Among the MOSFET M21-1 to M21-n of first group 21 n series connection each all is that diode connects.The drain electrode of MOSFET M21-1 and grid link to each other with the source electrode of MOSFET M3, the source ground of MOSFET M21-n.

Each of the MOSFET M22-1 to M22-n of second group 22 n series connection has a diode and connects.The drain electrode of MOSFET M21-1 and grid link to each other with the source electrode of MOSFET M6.The source ground of MOSFETM22-n.

Therefore, first and second group 21 and 22 of the source electrode of MOSFET M3 by MOSFET M21-1 to M21-n and MOSFET M21-1 to M21-n links to each other with the source electrode of MOSFET M6.

Then, below the operating principle of the MOS square root circuit shown in Fig. 7 is described.

Here, the transconductance parameters of MOSFET M3 is set to β.Then, the transconductance parameters of MOSFET M21-1 to M21-n represents that with β the transconductance parameters of MOSFET M4 represents that with K1 β MOSFETM5, M6 and M221 are to the transconductance parameters K of M22-n ₂β represents.

By using aforesaid equation (2), use following equation (16), (17), (18) expression bias current I respectively _b, input current I ₁(=drain current I _D1) and output current I ⁺

I _b＝I _D3＝β(V _GS3-V _TH) ² (16)

I ₁＝I _D1＝K ₁β(V _GS4-V _TH) ² (17)

I ⁺＝I _D5＝K ₂β(V _GS5-V _TH) ² (18)

In equation (16), (17), (18), V _GS3, V _GS4And V _GS5Be the grid of MOSFETM3, M4 and M5 voltage to source electrode, and I _D1And I _D2Be respectively the drain current of MOSFET M3 and M5.

Equally, each among the MOSFET M21-1 to M21-n has the V with MOSFET M3 _GS3Identical grid one source pole voltage, and each and the M6 of MOSFET M21-1 to M21-n also have the V with MOSFET M5 _GS5Identical grid-source voltage.Therefore, produced following equation (19).

(n+1)V _GS3+V _GS4＝(n+2)V _GS5 (19)

If with equation (16), (17) and (18) substitution equatioies (19), can provide following and equation (20a). $I^{+}=K_2{[\left(\frac{n+1}{n+2}\right)\sqrt{I_b}+\left(\frac{1}{n+2}\right)\sqrt{\frac{I_1}{K_1}}]}^2---\left(20a\right)$ $=\left\{\frac{K_2}{{(n+2)}^2}\right\}\{{(n+1)}^2{I}_b+\frac{I_1}{{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="A9810062400302.png"\; state="\{\{state\}\}">K</figure-callout>}}_1}+2(n+1)\sqrt{\frac{I_b{I}_1}{K_1}}\}$

Can find out the output current I of first square root circuit shown in Fig. 7 in the equation (20a) ⁺(I _D5) use I ₁Square root represent.Yet equation (20a) comprises I ₁And I _bThe item first time.

In according to the MOS linear transconductance amplifier according to second embodiment shown in Fig. 8, the second square root circuit 1b comprises 4 n-channel mosfet M7, M8 and M9 and M10, one for driven MOS FET M7 as same constant current I is provided _bThe constant-current source 11, the 3rd group 23 n series connection n channel mosfet M23-1 of constant-current source 10 to n the n channel mosfet M24-1 to M24-n that connects of M23-n and the 4th group 24.

MOSFET M ₈Grid width W and the ratio (W/L) of grid length L n MOSFET M23-1 being MOSFET M7 and the 3rd group 23 to the K of M23-n ₁Doubly so big, the ratio (W/L) of n MOSFET M24-1 to M24-n of MOSFET M9 and M10 and the 4th group 24 is the K of n MOSFET M23-1 to M23-n of MOSFETM7 and the 3rd group 23 ₂Doubly so big.

The source electrode of MOSFET M7 passes through the 3rd group 23 n MOSFET M23-1 to M23-n ground connection.The source electrode of MOSFET M10 passes through the 4th group 24 n MOSFET M24-1 to M24-n ground connection.Be not provided for the constant pressure source that voltage level is regulated.

The grid of MOSFET M7 links to each other with the source electrode of MOSFET M8.The drain electrode of MOSFET M7 is by constant-current source 11 and voltage V is provided _DDPower circuit link to each other.MOSFET M7 is by the constant current I from constant-current source 11 _bDrive.

The grid of MOSFET M9 links to each other with the grid of MOSFET M8 and the drain electrode of MOSFET M7.The drain electrode of MOSFETM9 is as another output and produce output current I thus ^-

Grid and the drain electrode of MOSFET M10 connect together, and in other words, MOSFET M10 is that diode connects.The grid by connecting of MOSFET M10 links to each other with the source electrode of drain electrode with MOSFET M9.

The MOSFET M23-1 of the 3rd group 23 n series connection has the diode connection to each of M23-n.The drain and gate of MOSFET M23-1 links to each other with the source electrode of MOSFET M7.The source ground of MOSFET M23-n.

The 4th group 24 n series connection MOSFET M24-1 has the diode connection to each of M24-n.The drain and gate of MOSFET M24-1 links to each other with the source electrode of MOSFET M10.And the source ground of MOSFETM24-n.

Therefore, the source electrode of MOSFET M7 links to each other with MOSFET M10 to M24-n with MOSFET M24-1 to M23-n by third and fourth group of 23 MOSFET M23-1 with 24.

Output circuit I with following equation (20b) the expression second square root circuit 1b ^- $I^{-}=K_2{[\left(\frac{n+1}{n+2}\right)\sqrt{I_b}-\left(\frac{1}{n+2}\right)\sqrt{\frac{I_1}{K_1}}]}^2---\left(20b\right)$ $=\left\{\frac{K_2}{{(n+2)}^2}\right\}\{{(n+1)}^2{I}_b-\frac{I_1}{{\mathrm{<figure-callout\; id="1"\; label="K"\; filenames="A9810062400302.png"\; state="\{\{state\}\}">K</figure-callout>}}_1}+2(n+1)\sqrt{\frac{I_b{I}_1}{K_1}}\}$

Pass through from output current I in order to produce difference output current Δ I ⁺In deduct output current I ^-Disappear equation (20a) and (20b) in I ₁The item first time, and need set up following equation. $\frac{K_2}{K_1{(n+2)}^2}=1---\left(21\right)$

In the case, the difference output current Δ I according to the MOS linear transconductance amplifier of second embodiment will be proportional to I ₁

For example, K ₁Be set to 1, equation (21) will be changed to following equation (22)

K ₂＝(n+2) ² (22)

In equation (22), provide K during at n=0 ₂Minimum value.In the case, K ₂=4.

Here, K ₂Be set at more than or equal to 4 integer and equal respectively output current I MOS differential pair 2 _D1And I _D2Be divided into (I _D1/ K ₂) and (I _D2/ K ₂).

This is identical with benefit among first embodiment.

The 3rd embodiment

Fig. 9 shows an example according to the first square root circuit 1a that is used for the MOS linear transconductance amplifier of the 3rd embodiment.In than trsanscondutance amplifier, the output current I of the MOS differential pair 2 shown in Fig. 7 _D1And I _D2Only be divided into (I respectively _D1/ K ₂) and (I _D2/ K ₂).

In Fig. 9, use K ₂Individual n-channel mosfet M _4-1To M4-K ₂One group 25 replace the MOSFET M4 shown in Fig. 7.MOSFET M4-1 is to M4-K ₂Grid and the drain electrode of MOSFET M3 connect altogether.MOSFET M4-1 is to M4-K ₂Source electrode jointly link to each other with the grid of MOSFET M3.MOSFET M4-1 is to M4-K ₂Drain electrode jointly link to each other with the power circuit that voltage VDD is provided.

MOSFET M4-1 is to M4-K ₂Leakage current I _D4-1To I _D4-K2And equal first output current or the I of MOS differential pair 2 ₁

It has and the same advantage of first enforcement.

Also has the another one benefit, promptly at K ₁=K ₂Can obtain this square root circuit 1a under=1 the situation; In other words, each of MOSFET is all formed by unit MOSFET.

The 4th embodiment

Figure 10 shows example, wherein a constant K according to the first square root circuit 1a that is used for the MOS linear transconductance amplifier of the 4th embodiment ₂Need to represent with the product of two positive integer i and j.

In this trsanscondutance amplifier, the output current I of the MOS differential pair 2 shown in Fig. 8 _D2And I _D2Be divided into (I respectively _D2/ i.j) and (I _D2/ i.j).

In Figure 10, with a pair of 2b of n-channel mosfet M4a-1 and M4a-2 and n-channel mosfet M4b-1 one group of 27 MOSFET M4 that replaces among Fig. 7 to M4b-j.

The grid of MOSFET M4a-1 and M4a-2 links to each other with the drain electrode of MOSFET M3 jointly.The source electrode of MOSFETM4a-1 and M4a-2 links to each other with the grid of MOSFET M3 jointly.The drain electrode of MOSFET M4a-1 directly links to each other with the constant voltage circuit that voltage VDD is provided.The drain electrode of MOSFET M4a-2 links to each other with the power circuit that voltage VDD is provided by MOSFETM4b-1.

MOSFET M4b-1 links to each other with the drain electrode of MOSFET M3 jointly to the M4b-j grid.MOSFETM4b-1 links to each other with the drain electrode of MOSFET M4a-2 jointly to the source electrode of M4b-j.MOSFET M4b-1 links to each other with the power circuit that voltage VDD is provided jointly to the drain electrode of M4b-j.

MOSFET M4b-1 is to the drain current I of M4b-j _D4b-1To I _D4b-jAnd equal the drain current I of MOSFETM4a-2 _D4a-2The drain current I of MOSFET M4a-2 _D4a-2Leakage current I with MOSFET M4a-1 _D4a-1And equal the first output current I of MOS differential pair 2 _D1Or I ₁

It has and identical advantage during first implements.

Also have the another one benefit, promptly (a) can realize this square root circuit 1a under the condition of K1=K2=1; In other words, each among these MOSFET is all formed by single MOSFET.And (b) number of the required MOSFET of square root circuit 1a than required lacking among the 3rd embodiment shown in Fig. 9.

The 5th embodiment

Figure 11 shows the MOS linear transconductance amplifier according to fifth embodiment of the invention.

In this amplifier, the first and second square root circuit 1a and 1b have the structure shown in Fig. 7, and wherein n=0 and K2=4 are provided with the constant pressure source 4a that constant voltage VS is provided in addition between the source electrode that links to each other of MOSFET M3, M6, M7 and M10 and ground.

With the difference output current Δ I of following equation (23) expression according to the MOS linear transconductance amplifier of the 5th embodiment. $\mathrm{\&Delta;I}=I^{+}-I^{-}=2\sqrt{I_b{I}_{D1}}-2\sqrt{I_{\mathrm{<figure-callout\; id="2"\; label="b\; I\; D"\; filenames="A9810062400302.png,A9810062400321.png"\; state="\{\{state\}\}">b</figure-callout>}}{I}_D{2}_{}}$ $=2\sqrt{{\mathrm{\&beta;I}}_b}{V}_i\left[\right|V_i|\&le;\sqrt{\frac{I_O}{\mathrm{\&beta;}}}]---\left(23\right)$

It has and identical advantage during first implements.

The 6th embodiment

Figure 12 shows the MOS linear transconductance amplifier according to sixth embodiment of the invention.

In Figure 12, first square root circuit 1 _aForm by the constant-current source 11 that four n-channel mosfet M11, M12, M13 and M14 are provided for the constant current Ib of driven MOS FET M15.Second square root circuit 1 _bBe by four n channel mosfet M15, M16, M17 and M18, and provide identical drive current I for driven MOS FET M15 _bConstant-current source 11 form.

Each of MOSFET M11, M12 all is that diode connects, and the grid of MOSFET M11 links to each other with the power circuit that voltage VDD is provided by constant-current source 10 with drain electrode.The source electrode of MOSFET M11 links to each other with drain electrode with the grid of MOSFET M12.

The grid of MOSFET M13 links to each other with drain electrode with the grid of MOSFET M11.The source electrode of MOSFET M13 links to each other with the drain electrode of the MOSFET M1 of differential pair 2.The drain electrode of MOSFET M13 also produces output current I thus as the output of this trsanscondutance amplifier ⁺

The grid of MOSFET M14 links to each other with the source electrode of MOSFET M13.The drain electrode of MOSFET M14 links to each other with the drain electrode of MOSFET M17.

Each of MOSFET M15 and M16 all is that diode is connected.The grid of MOSFET M15 links to each other with the power circuit that voltage VDD is provided by constant-current source 11 with drain electrode.The source electrode of MOSFET M15 links to each other with drain electrode with the grid of MOSFET M16.

The grid of MOSFET M17 links to each other with drain electrode with the grid of MOSFET M15.The source electrode of MOSFET M17 links to each other with the drain electrode of the MOSFET M2 of differential pair 2.The drain electrode of MOSFET M17 also produces output current I thus as another output of this trsanscondutance amplifier ^-

The grid of MOSFET M18 links to each other with the source electrode of MOSFET M17.The drain electrode of MOSFET M18 links to each other with the drain electrode of MOSFET M13.

Between the source electrode that links to each other of MOSFET M12, M14, M16 and M18 and ground, provide the 4a of the constant pressure source with constant voltage Vs.

Below, the operation principle according to the MOS linear transconductance amplifier of the 6th embodiment is described.

At first, derive the following equation (24) of MOSFET M11, M12 from top equation (2).

I _b＝β(V _GS11-V _TH) ²＝β(V _GS12-V _TH) ² (24)

Derive following equation (25) and (26) that are used for MOSFET M13 and M14 respectively from top equation (2).

I _D13＝I _D1＝β(V _GS13-V _TH) ² (25)

I _D14＝β(V _GS14-V _TH) ² (26)

In addition, can set up following equation (27)

V _GS11+V _GS12＝V _GS13+V _GS14 (27)

Separate equation (24), (25), (26) and (27), can provide following equation (28). $\sqrt{{\mathrm{<figure-callout\; id="1"\; label="I\; D"\; filenames="A9810062400302.png"\; state="\{\{state\}\}">I</figure-callout>}}_D}+\sqrt{I_{D14}}=2\sqrt{I_b}---\left(28\right)$

Therefore, from equation (28), the leakage current of MOSFET M14 can be expressed as follows. $I_{D14}=4I_b+I_{D1}-4\sqrt{I_b{I}_{D1}}---\left(29\right)$

Leakage current I with MOSFET M14 _D14Identical mode, the leakage current I of MOSFET M17 and M18 _D17And I _D18Can be expressed as follows.

Correspondingly, (30a) reach (30b) the difference output current of available following equation (31) expression MOS linear transconductance amplifier by equation (25) (29).

I _D17＝I _D2＝β(V _GS17-V _TH) ² (30a) $I_{D18}={4I}_b+I_{D2}-4\sqrt{I_b{I}_{D1}}---\left(30b\right)$

In addition, utilize equation (25), (29), (30a) and (30b), the output current Δ I of MOS linear transconductance amplifier can be represented by following formula (31).

ΔI＝I ⁺-I ^-

＝(I _D13+I _D18)-(I _D14+I _D17) $={4I}_b(\sqrt{I_{D1}}-\sqrt{I_{D2}})---\left(31\right)$ $=4\sqrt{\mathrm{\&beta;}{I}_b}{V}_i$

Therefore, according to the difference output current Δ I of the MOS linear transconductance amplifier of the 6th embodiment with respect to difference input voltage V _iCharacteristic with complete linearity.

Figure 13 shows the transfer characteristic according to the MOS linear transconductance amplifier of the 6th embodiment.It is that the inventor measures under following condition.

NOS differential pair and first and second square root circuit 1a and 1b are made of μ PA572T-type power MOS transistor array.V wherein _TMBe approximately 1.5V.Supply voltage V _DDBe set at and be approximately 8.0V.The constant current of constant-current converter 3 (or wake flow) I _OBe set to about 12mA.The public power voltage of square root circuit 1a and 1b is set as 2.0V.The bias current I of MOSFETM11 and M15 _bBe set to about 3mA, 4.5mA and 6mA.As constant current or wake flow I _OWhen being approximately 12mA, the work input voltage range of MOS differential pair 2 is 1V _P-p

As can be seen from Figure 13, difference output current Δ I has the transfer characteristic of the full linear finished in particular range, and the complete linear transformation characteristic of difference output current Δ I can be according to the bias current I of MOSFETM11 and M15 _bAnd be moved.

The 7th embodiment

In first to the 6th above-mentioned embodiment, mutual conductance is proportional to bias current I _b, i.e. I _b ^1/2Normally, best mutual conductance is proportional to bias current I from practical standpoint _bItself.Only provide bias current I to corresponding bipolar transistor Q1 or MOSFET M3 or M13 by square root circuit _bRealize bias current I _bLinear speciality.

Figure 14 shows the bipolar square root circuit that is used for the MOS linear transconductance amplifier according to the 7th embodiment.This square root circuit is electric current input and current-output type.

In Figure 14, bipolar square root circuit is by 4 pnp type bipolar transistor Q11, Q12, Q13 and Q14, and provides constant current I to transistor Q13 _cConstant-current source 31 form.

Each of transistor Q11 and Q12 is connected for diode.The emitter of transistor Q11 with supply voltage V is provided _CcPower circuit link to each other.The base stage of transistor Q11 links to each other with the emitter of collector electrode with transistor Q12.

Bias current I _bBe that base stage and collector electrode from transistor Q12 is absorbed.

The grounded emitter of transistor Q13, the base stage of transistor Q13 links to each other with collector electrode with the base stage of transistor Q12.The collector electrode of transistor Q13 is by constant-current source and voltage V is provided _CcPower circuit link to each other.

The base stage of transistor Q14 links to each other with the base stage of transistor Q11 and the emitter of collector electrode and transistor Q13.The emitter of transistor Q14 with voltage V is provided _CcPower circuit link to each other.

The output current I of square root circuit _SQWith respect to input bias current I _bHas a square transfer characteristic.

The operating principle of the square root circuit shown in Figure 14 is described below.

As seen from Figure 14, clearly can set up following equation (33), (34), (35) and (36).

V _BE11+V _BE12＝V _BE13+V _BE14 (33) $V_{\mathrm{BE}11}+V_{\mathrm{BE}12}=V_T\ln \left(\frac{I_C}{I_S}\right)---\left(34\right)$ $V_{\mathrm{BE}13}=V_T\ln \left(\frac{I_b}{I_S}\right)---\left(35\right)$ $V_{\mathrm{BE}14}=V_T\ln \left(\frac{I_{\mathrm{SQ}}}{I_S}\right)---\left(36\right)$

Solve an equation (36) with equation (33), (34) and (35), can provide following equation (37). $I_{\mathrm{SQ}}=\frac{{I_b}^2}{I_C}---\left(37\right)$

From equation (33), can be clear that the output current I of the square root circuit shown in Figure 14 _SQBe proportional to bias current I _bSquare.

For example, if the square root circuit shown in Figure 14 is applied to the bipolar square root circuit 1a shown in Fig. 4, the difference output current Δ I of MOS linear transconductance amplifier can be expressed as follows: $\mathrm{\&Delta;I}=I^{+}-I^{-}=\sqrt{\frac{I_{\mathrm{SQ}}{I}_{D1}}{K}}-\sqrt{\frac{I_{\mathrm{SQ}}{I}_{D2}}{K}}$ $=\sqrt{\frac{\mathrm{\&beta;}}{{\mathrm{KI}}_C}}{I}_b{V}_i\left[\right|V_i|\&le;\sqrt{\frac{I_O}{\mathrm{\&beta;}}}]---\left(38\right)$

Can find out that from equation (38) difference output current Δ I is proportional to bias current I _b

The 8th embodiment

Figure 15 shows the MOS square root circuit that is used for according to the MOS linear transconductance amplifier of the 8th embodiment.This square root circuit is voltage input and current-output type.

In Figure 15, the source electrode of four n-channel mosfet M32, M34, M35 and M36 connects together, and its constant current I that is absorbed by constant-current converter 43 _SDrive, form one and return lead wire unit.The grid of cross-over connection MOSFET M33 and M34 provides input voltage with V _cVoltage V _cHalf, promptly Vc/2 is added to the grid of MOSFET M35 and M36, wherein Vc/2 is produced by two resistance 41 with similar resistance and 42.

Two P channel mosfet M37 and M38 form a current mirror.Two P channel mosfet M39 and M40 form a current mirror.Two n channel mosfet M41 and M42 form a current mirror.

The leakage current I of MOSFET M33 and M34 _D33And I _D34And, i.e. (I _D33+ I _D34) flow through MOSFET M37.Therefore, the drain current I of MOSFET M38 _D38Equal (I _D33+ I _D34).

The drain current I of MOSFET M35 and M36 _D35And I _D36And, i.e. (I _D35+ I _D36) flow through MOSFET M39.Therefore, the drain current of MOSFET M40 equals (I _D35+ I _D36).The drain current I of MOSFET M40 _D40Equal the drain current I of MOSFET M41 _D41Drain current I with MOSFET M42 _D42, i.e. I _D41=(ID35+ID36+)=I _D42

Therefore, output current I _SQBe expressed as drain current I _D38And I _D42Poor, that is:

I _SQ＝I _D38-I _D42＝(I _D33+I _D34)-(I _D35+I _D36).

Here, the equation (39) below the circuit structure from Figure 15 can produce, (40), (41) and (42). $V_{\mathrm{GS}33}=V_{\mathrm{GS}35}+\frac{V_C}{2}---\left(39\right)$ $V_{\mathrm{GS}34}=V_{\mathrm{GS}35}-\frac{V_C}{2}---\left(40\right)$

V _GS35＝V _GS36 (41)

I _D33+I _D34+I _D35+I _D36＝I _S (42)

If above-mentioned equation (2) is separated equation (39), (40), (41) and (42), output current I _SQCan be expressed as following form: $I_{\mathrm{SQ}}=(I_{D33}+I_{D34})-(I_{D35}+I_{D36})=\frac{{{\mathrm{\&beta;<figure-callout\; id="2"\; label="V\; C"\; filenames="A9810062400302.png,A9810062400321.png"\; state="\{\{state\}\}">V</figure-callout>}}_C}^2}{2}$ $\left[\right|V_C|\&le;\sqrt{\frac{{2\mathrm{<figure-callout\; id="3"\; label="I\; O"\; filenames="A9810062400301.png,A9810062400391.png"\; state="\{\{state\}\}">I</figure-callout>}}_O}{3\mathrm{\&beta;}}}]---\left(43\right)$

From equation (43), can clearly be seen that the output current I of the square root circuit shown in Figure 15 _SQBe proportional to corresponding to bias current I _bInput voltage V _cSquare.

For example, if the square root circuit shown in Figure 15 is used the MOS square root circuit shown in Fig. 7, the difference output current Δ I of MOS linear transconductance amplifier can be expressed as follows so: $\mathrm{\&Delta;I}=I^{+}-I^{-}=\sqrt{I_{\mathrm{SQ}}{I}_{D1}}-\sqrt{I_{\mathrm{<figure-callout\; id="2"\; label="SQ\; I\; D"\; filenames="A9810062400302.png,A9810062400321.png"\; state="\{\{state\}\}">SQ</figure-callout>}}{I}_D{2}_{}}=\mathrm{\&beta;}{V}_C{V}_i---\left(44\right)$ $\left[\right|V_i|\&le;\sqrt{\frac{{2I}_S}{3\mathrm{\&beta;}}},|V_i|\&le;\sqrt{\frac{I_O}{\mathrm{\&beta;}}}]$

As can be seen, difference output current Δ I is proportional to input voltage V from equation (44) _c, i.e. bias current I _b

Though described optimised form of the present invention, must the clear and definite various modifications of being done for those skilled in the art can't break away from essence of the present invention.Therefore scope of the present invention is only limited by following claim.

Claims (11)

1, a kind of MOS linear transconductance amplifier is characterized in that comprising:

(a) the MOS differential pair of first and second MOSFET that link to each other of source electrode;

(b) be connected with the described source electrode that links to each other of described first and second MOSFET, and provide/absorb the first constant-current source/converter of first constant current that is used to drive described MOS differential pair;

(c) with first square root circuit that links to each other of the drain electrode of a MOSFET; And

(d) second square root circuit that links to each other with the drain electrode of described the 2nd MOSFET;

Wherein said MOS differential pair is that the grid at described first and second MOSFET provides input voltage, and at drain electrode difference ground output first and second output currents separately of described first and second MOSFET;

And wherein described first square root circuit is provided described first output current of described MOS differential pair, it then exports the 3rd electric current;

Provide described second output current of described MOS differential pair to described second square root circuit, then it exports the 4th output current;

And the output current of described MOS linear transconductance amplifier is that the difference by described third and fourth output current provides.

2, amplifier according to claim 1, each that it is characterized in that described first and second square root circuits has the first, second, third and the 4th bipolar transistor, and the second constant-current source/converter that provides/absorb second constant current that is used to drive the first transistor;

And the base stage of described transistor seconds links to each other with base stage with the collector electrode of described the first transistor respectively with emitter, and described transistor seconds is driven by corresponding of described first and second output currents of described MOS differential pair;

And wherein said the 3rd transistor base links to each other with the described base stage of described transistor seconds;

The wherein said the 4th transistorized base stage links to each other with the described the 3rd transistorized described emitter with collector electrode, and the described the 4th transistorized emitter links to each other with the described emitter of described the first transistor;

And the wherein said the 3rd transistorized collector current as the described the 3rd and described the 4th output current in corresponding one.

3, amplifier according to claim 2, the emitter area K that it is characterized in that wherein said transistor seconds is doubly to described the first, the 3rd and the 4th transistorized emitter area, and wherein K is the constant greater than 1.

4, amplifier according to claim 2 is characterized in that it is variable that described second constant-current source/converter is designed to cause described second constant current.

5, amplifier according to claim 1, each that it is characterized in that described first and second square root circuits has the 3rd, the 4th, the 5th and the 6th MOSFET, and the second constant-current source/converter that provides/absorb second constant current that is used to drive described the 3rd MOSFET;

The grid of wherein said the 4th MOSFET links to each other with the drain and gate of source electrode with described the 3rd MOSFET, and described the 4th MOSFET by corresponding one of described first and second output currents of described MOS differential pair drive;

And the grid of wherein said the 5th MOSFET links to each other with the described grid of described the 4th MOSFET;

And the grid of wherein said the 6th MOSFET links to each other with the described source electrode of described the 5th MOSFET with drain electrode, and the source electrode of described the 6th MOSFET links to each other with the described source electrode of described the 3rd MOSFET;

And the drain current of wherein said the 5th MOSFET is as one in described third and fourth output current.

6, amplifier according to claim 5 is characterized in that described the 4th MOSFET has K ₁Doubly to the grid width and grid length ratio of described the 3rd MOSFET, and the described the 5th and the grid width of the 6th MOSFET and the ratio of grid length be the K of described the 3rd MOSFET ₂Doubly so big, K wherein ₁And K ₂Constant greater than 1.

7, amplifier according to claim 5 is characterized in that it is variable that described second Heng Yuan/converter is designed to be used in described second constant current.

8, amplifier according to claim 1, each that it is characterized in that described first and second square root circuits also comprise first group n series connection MOSFET and second group n the MOSFET that connects, and wherein n is the integer more than or equal to 1;

Each of wherein said first group n series connection MOSFET is diode connection, and first the drain and gate of described first a group n MOSFET links to each other with the described source electrode of described the 3rd MOSFET;

And each of wherein said second group n series connection MOSFET is diode connection, and first the drain and gate of described second a group n MOSFET links to each other with the described source electrode of described the 6th MOSFET;

And the described source electrode of wherein said the 3rd MOSFET links to each other with described second group n MOSFET and described source electrode described the 6th MOSFET by described first a group n MOSFET.

9, amplifier according to claim 1, it is characterized in that described each first square root circuit has the 3rd, the 4th, the 5th and the 6th MOSFET, and provide/absorb the second constant-current source/converter of second constant current for driving described the 3rd MOSFET, and described second square root circuit has the 7th, the 8th, the 9th and the tenth MOSFET, and is used to drive the 3rd constant-current source/converter that described the 7th MOSFET provided/absorbed the 3rd constant current;

And the wherein said the 3rd, the 4th, the 7th be that diode is connected with the 8th MOSFET;

And the grid of described the 3rd MOSFET links to each other with described second constant-current source/interchanger with drain electrode, and the source electrode of described the 3rd MOSFET links to each other with drain electrode with the grid of described the 4th MOSFET;

And the source electrode of wherein said the 4th MOSFET links to each other with the source electrode of described the 6th MOSFET;

Wherein said the 5th MOSFET grid links to each other with the described grid of a described MOSFET; The drain electrode of described the 5th MOSFET is as the output of drawing described the 3rd output current thus; Corresponding one of the described drain electrode of the source electrode of described the 5th MOSFET and described first and second MOSFET links to each other;

The grid of wherein said the 6th MOSFET links to each other with the described source electrode of the 5th MOSFET;

The grid of described the 7th MOSFET links to each other with described the 3rd constant-current source/converter with drain electrode; And the source electrode of described the 7th MOSFET links to each other with drain electrode with the grid of described the 8th MOSFET;

The source electrode of described the 8th MOSFET links to each other with the source electrode of described the tenth MOSFET;

The grid of described the 9th MOSFET links to each other with the described grid of described the 2nd MOSFET, and the drain electrode of described the 9th MOSFET is as an output of drawing described the 4th output current thus; Corresponding one of the described drain electrode of the source electrode of described the 9th MOSFET and described first and second MOSFET links to each other;

The grid of wherein said the tenth MOSFET links to each other with the described source electrode of described the 9th MOSFET;

The drain electrode of wherein said the 6th MOSFET links to each other with the described drain electrode of described the 7th MOSFET, and the drain electrode of described the tenth MOSFET links to each other with the described drain electrode of described the 5th MOSFET.

10, amplifier according to claim 2, the described output current that it is characterized in that wherein said MOS linear transconductance amplifier has the linear characteristic with respect to described second constant current.

11, amplifier according to claim 5 is characterized in that the described output current of described MOS linear transconductance amplifier has linear behavio(u)r with respect to described second constant current.

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