GB2312554A

GB2312554A - Process for the manufacture of semiconductor components comprising micromechanical structures

Info

Publication number: GB2312554A
Application number: GB9708501A
Authority: GB
Inventors: Franz Laermer; Andrea Schilp
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 1996-04-27
Filing date: 1997-04-25
Publication date: 1997-10-29
Anticipated expiration: 2017-04-25
Also published as: DE19616970A1; DE19616970B4; FR2748159B1; GB9708501D0; FR2748159A1; GB2312554B

Description

2312554 Process for the manufacture of semiconductor components comprising

micromechanical structures

The invention relates to a process for the manufacture of semiconductor components comprising micromechanical structures in accordance with the preamble to Claim 1.

State of the Art It is known to apply micromechanical structures to the surface of semiconductor elements, for example of silicon wafers comprising integrated circuits (IC). Said structures may be, for example, freely mobile sensor elements designed as capacitive acceleration sensors consisting of a resiliently suspended seismic mass as well as a combstructure arrangement for capacitive evaluation of the deflection of the seismic mass due to acceleration.

The traditional processes for surface micromechanics utilise, with a view to creating such components, sacrificial layers which are, for example, integrated into the wafer structure and active silicon layers above said sacrificial layers, said active silicon layers consistin& for exaniple, of polysilicon above islands of silicon oxide, so that a massive intervention into the IC process has to be undertaken.

According to another known manufacturing process these sensor elements are created in galvanically deposited metal layers with the aid of the LIGA technique. In the LIGA process, high X-ray-resist structures produced by synchrotron exposure are formed galvanically and from said structures an initial stamping mould is firstly obtained. This stamping mould is then used for the stamping under high pressure of polymer layers applied to wafers which consequently result in a negative mould that is then filled galvanically. The polymer mould is 2 subsequently destroyed so that the sensor element is exposed. In this case it is a disadvantage that a synchrotron exposure can only be carried out with great and therefore expensive effort by means of additional synchrotron installations that are not customary for the manufacture of a semiconductor component. Furthermore, as a result of the high stamping pressures during the stamping of the negative structures there is a risk of destruction of the wafer, of the stamping mould or of the electronic circuits integrated within the wafer. Furthermore, in the course of stamping the sensor elements an accurate adjustment in relation to the circuits contained on the wafers is problematic. As a result of wear and tear of the stamping mould it is necessary, by restamping, to produce several daughter moulds before the actual manufacture of the sensor elements can take place. It has hitherto not been possible in practice to demonstrate the function of the process as a whole. In any case, the stamping on an IC wafer constitutes a risky intervention into the IC process.

From DE 44 18 163 AI a process is known in which the micromechanical structures are subsequently structured onto a fully processed senniconductor component by the later structures being formed in additionally applied layers and later being grown galvanically. In this case it is a disadvantage that as a result of the galvanic forming of the micromechanical structures the entire semiconductor component consists of differing materials which in marginal applications of the semiconductor components can lead to failures by reason of their differing thermal behaviour.

Advantages of the Invention

Claims

The process according to the invention with the characteristics specified

in Claim 1 offers the advantage that, besides the decoupling of the manufacture of the micromechanical structures from the process for manufacture of the integrated

3 circuits so as to form a fully processed wafer, the micromechanical structures can be generated in similar materials that are conventional for the manufacture of the wafer that comprises integrated circuits. By virtue of the fact that the micromechanical structures are structured in a second wafer and this second wafer is joined with the first wafer comprising the integrated circuits so as to form the semiconductor component it is possible in advantageous manner to achieve a complete technical decoupling of the manufacturing processes relating to both the electronic part and the sensor part of the semiconductor component. At no point in the manufacture is it necessary to have recourse to details of the manufacture of the first wafer comprising the integrated circuits or to effect interventions in the latter. As a result of the subsequent joining of the electronic part (first wafer) and of the sensor part (second wafer) it is possible to achieve a sandwich-type construction of the semiconductor component in which the sensor part can be arranged directly above the electronic part. As a result no additional surfaces are required by the sensor part. Altogether a very compact semiconductor component can be achieved in which both the electronic part and the sensor part consist substantially of similar materials. This results, both under continuous load and under a multitude of load changes, in outstanding mechanical properties which are to be ascribed in particular to similar thermal behaviour.

Advantageous configurations of the invention will become apparent from the other characteristics that are specified in the subclaims.

Drawing The invention is elucidated 'm more detail below in an example of an embodiment with reference to the accompanying drawings in which the manufacturing process is clarified mi Figures 1 to 6 on the basis of a schematic representation of a semiconductor component.

4 Description of the Embodiment Example The ffidividual process steps for the manufacture of a semiconductor component 10 are represented in Figures 1 to 6. Basically the semiconductor component 10 consists of a first wafer 12, for example a silicon wafer, which comprises integrated circuits that are not shown in any detail. The wafer 12 forms the later electronic part of the semiconductor component 10.

The semiconductor component 10 fin-ther comprises a second wafer 14, for example also a silicon wafer, within which micromechanical structures are structured, for example a capacitive acceleration sensor consisting of a resiliently suspended seismic mass and also a comb-structure arrangement for the capacitive evaluation of a deflection of the seismic mass due to acceleration. The second wafer 14 forms the later sensor part of the semiconductor component 10.

The individual process steps for the manufacture of the fully processed semiconductor component 10 shown in Figure 6 will be elucidated in more detail below. Similar parts are provided in Figures 1 to 6 with the same reference symbols and are each elucidated once only.

Figure 1 shows the second wafer 14 in its initial state. The wafer 14 consists, for example, of a highly (h)-doped silicon substrate 16, on which a highly (p')-doped silicon layer 18 is grown epitaxially. The p'doped silicon layer can be deposited in totally stress-free manner by codoping with germanium during the epitaxy, so that the wafer 14 is totally plane and does not warp. Between the p, silicon layer 18 and the h' silicon substrate 16 a zone 22 having low effective n-doping remains m the region of the pn transition 20. The zone 22 can be additionally widened as required by the epitaxy of the p' silicon layer 18 firstly starting without doping gases - that is to say, by a layer of very lowly doped silicon firstly being grown, and by the doping gases, for example B2H, and Gell, being added only after growing this additional layer. During the epitaxial growing of the strongly doped silicon layer 18 n-doping substances from one side and p- doping substances from the other side diffuse out into the lowly doped starting layer (zone 22) so that in particular, a region of markedly low n-doping is formed.

In a second process step which is clarified in Figure 2 the n silicon substrate 16 is converted into porous silicon 24. This conversion can be effected, for example, by means of an electrochemical anodising process in hydrofitioric acid solution, whereby the anodic connection of the wafer 14 to the p- wafer side can be effected directly via the electrolyte - that is to say, via the p- silicon layer 18. For this purpose the wafer 14 may, for example, be clamped into a suitable holder in the electrolyte that has current passing through it, whereby the holder prevents the direct flow of current around the wafer 14. The p+ silicon layer 18 is located opposite the anode - that is to say, it is itself connected so as to constitute a cathode in relation to the electrolyte. The high p-doping of the silicon layer 18 is necessary in order to reduce the effect of the Schottky diode between the electrolyte and the silicon of the wafer 14. Another possibility for the conversion of the substrate 16 into porous silicon consists in metallising one side of the wafer 14 and contacting the metal surface directly. In this case, however, the metaffisation and the contact have to be protected against attack by the electrolyte during the anodising, for example by incorporation of the wafer 14 into an etching box.

The electrochenncal conversion of the silicon substrate 16 so as to form the porous silicon 24 stops with a suitable choice of potential at the lowly n-doped zone 22. The wafer 14, extensive parts of which are now porous, largely retains its mechanical stability which is sufficiently high for further processing. However, the porous silicon 24 that is generated is extremely unstable chemically and 6 dissolves in many chemical reagents in a short time when subjected to an appropriate reactant. In order to achieve sufficient chemical stabilisation for further processing of the wafer 14 a pre-oxidation is carried out at about 450' C. This ensures that the porous silicon 24 remains stable in the course of the ensuing process steps.

According to the next process step shown in Figure 3 the micromechanical structures of the sensor part and the fastening elements thereof on the electronic part (wafer 14 and wafer 12 respectively) are defined 'm the wafer 14 from the side of the non-porous p- silicon layer 18. To this end, via, for example, photolithographic processes that are known per se a mask is produced on the p' silicon layer 18 that permits subsequent trenching of blanks 26 of the later micromechanical structures. Corresponding to the number, the choice and the dimensional design of the individual micromechanical structures, trench grooves 28 are produced. With a view to generating the micromechanical structures and the fastening elements, use is advantageously made of two masks, for example a plasma oxide for the definition of the later fastening elements and a second photoresist mask for the definition of the sensor structures. By means of two successive plasma-trench processes it is possible, with the aid of the photoresist mask, for the later micromechanical sensors and then, with the aid of the plasmaoxide mask, for the later fastening elements to be generated (Figure 4). The trench grooves 28 for defining the later micromechanical structures are in this case etched beyond the zone 22 right into the porous silicon 24.

The plasma-etching process clarified in Figure 4 for generating the fastening elements 30 constitutes a planar back-etching process. In order to protect the trench grooves 28 already created previously from a further etching attack, a photoresist or deposited plasma polymer, for example, can be employed as edge protection.

7 The process elucidated in Figures 1 to 4 constitutes a preprocess g of the second wafer 14. This second wafer 14, prepared in this way, is joined in an ensuing process step with the already fully processed first wafer 12 (electronic part), as Figure 5 makes clear. To this end the wafer 14 is placed over the wafer 12 in such a way that the fastening elements 30 rest on contact regions 32 of the wafer 12 that are provided for this purpose. The joining of the wafer 14 with the wafer 12 is effected in this case using an adjusted joining process, so that it is ensured that each fastening element 30 contacts the contact region 32 assigned to it. By a suitable chemical pretreatment of the wafer 12, for example hydrophilising, as a result of van der Waals forces a firm contact is achieved between the fastening elements 30 consisting of silicon and the contact regions 32, consisting for example of aluminium.

In a next process step the wafer 14 (sensor part) is heated for a short time, whereas the wafer 12 (electronic part) is cooled. This process step can be implemented by means of a suitable device, comprising for example a cooling device that comes into contact with the wafer 12 and a heating device that comes into contact with the wafer 14. By this means it is ensured that the point of contact between the fastening elements 30 and the contact regions 32 can be heated to temperatures greater than 450' C, while at the same time the wafer 12 is protected against excessive heating. As a result of the heating of the contact region an alloy is formed between the silicon of the fastening elements 30 and the aluminium of the contact regions 32, so that the wafer 14 is firmly connected mechanically and electrically to the wafer 12 by formation of an aluminium/silicon eutectic. Instead of this, use may also be made, of course, of a solder which is previously pressed onto the contact pads of the IC wafer.

In a final process step the porous silicon 24 of the wafer 12 is dissolved and by this means the micromechanical structures 34 are exposed. In order to dissolve the 8 porous silicon 24, the silicon that has previously been pre-oxidised with a view to chemical stabilisation can be chemically reactivated, for example by means of a strongly diluted hydrofluoric acid solution. The internal oxide of the porous silicon 24 created by the pre-oxidation is removed by the hydrofluoric acid solution. The porous silicon 24, which is now unstable again, can be dissolved, for example by means of dilute ammoniacal liquor, dilute KOH solution, NaOH solution, an aqueous 14F/HNO, mixture or other suitable means. In this connection dissolution of the porous silicon is effected very rapidly, for example within a period of less than one minute. By virtue of this very short time during which the etching solutions act and the effectiveness thereof at low temperatures, for example at room temperature, damage to the wafer 12 and the micromechanical structures 34 is ruled out.

After the entire processing has been concluded the semiconductor component 10 shown in a schematic sectional representation in Figure 6 is formed. In this case the semiconductor component 10 comprises the wafer 12 with integrated circuits (not shown) and micromechanical structures arranged on the wafer 12 which remain by way of rudiment of the original wafer 14 and which are arranged firmly and durably on the wafer 12. Corresponding to the production, elucidated in Figure 3 and 4, of the trench grooves 28 and the fastening elements 30, respectively, it is possible in this way to create in simple manner resiliently suspended seismic masses and corresponding comb structures for the capacitive evaluation or capacitive drive of movements of the seismic masses.

Another manufacturing variant consists in bonding the unstructured wafer 14 shown in Figure 2, which comprises the porous silicon 24, to the wafer 12, then removing the porous silicon 24 and implementing the structuring of the micromechanical structures thereafter from the top side on the remaining active layer (zone 22, p silicon layer 18). This avoids the joining of the fully 9 preprocessed wafer 14 with the wafer 12 (Figure 5) in a manner whereby accuracy depends on adjustment. A disadvantage in this case, however, is that the wafer 12 has to have appropriate contact bumps onto which the wafer 14 can be bonded.

Another manufacturing variant consists in preparing the wafer 14 as far as the state shown 'm Figures 1 to 3 and then bonding the latter against contact bumps of the wafer 12 and finally removing the porous silicon 24. By this means the process step of surface re-etching with a view to generating the fastening elements 30 (Figure 4) is eliminated. As a result of the application of the contact bumps on the wafer 12, however, an intervention is necessary into the processing within the wafer 12 - that is to say, generation of the integrated circuits.

The mechanical and electrical connection elucidated between the wafers 14 and 12 (sensor part and electronic part) is merely exemplary. Thus, besides the generation of the aluminium/silicon eutectic at the connecting point, other known techniques, for example the use of conductive adhesives or solders, are possible.

On the basis of the description it becomes clear that by means of a few, generally controllable, process steps in materials of the same type both for the wafer 12 (electronic part) and the wafer 14 (sensor part) it is possible to create all structures that are conceived or necessary for an appropriate semiconductor component 10. The same choice of material for the wafers 12 and 14 results in a very advantageous thermal behaviour of the semiconductor component 10, both under continuous load and 'm the case of alternating loads.

Claims 1. Process for the manufacture of semiconductor components comprising micromechanical stiuctures, characterised in that the micromechanical structures (34) are structured in a second wafer (14) and this second wafer (14) is joined with a first wafer (12) so as to form the semiconductor component (10).
2. Process according to Claim 1, characterised in that a p±doped silicon layer (18) is generated on an n'-doped silicon substrate (16) with a view to manufacturing the wafer (14).
3. Process according to one of the preceding claims, characterised in that a sufficiently wide, lowly n-doped zone (22) is applied between the silicon substrate ( 16) and the silicon layer (18).
4. Process according to one of the preceding claims, characterised in that the silicon substrate (16) is converted into porous silicon (24).
5. Process according to Claim 4, characterised in that the conversion is effected by an electrochemical anodising process.
6. Process according to one of the preceding claims, characterised in that the porous silicon (24) is chemically stabilised by a pre-oxidation.
7. Process according to one of the preceding claims, characterised in that the micromechanical structures (34) and fastening elements (30) for the micromechanical structures (34) are defined and generated from the side of the silicon layer (18) in the wafer (14).
8. Process according to Claim 7, characterised in that the generation of the micromechanical structures (34) and of the fastening elements (30) is effected via at least one mask and subsequent plasma-trench processes.
9. Process according to one of the preceding claims, characterised in that the prepared wafer (14) is joined onto the wafer (12) in a manner whereby accuracy depends on adjustment.
10. Process according to one of the preceding claims, characterised in that the fastening elements (30) of the wafer (14) with assigned contact regions (32) of the wafer (12) are connected mechanically and in electrically conductive manner.
11. Process according to one of the preceding claims, characterised in that the wafer (14) is subjected to a heating means and the wafer (12) is subjected to a cooling means in such a way that a durable connection between the fastening elements (30) and the contact regions (32) arises via a solder or a eutectic connection.
12. Process according to one of the preceding claims, characterised in that the porous silicon (24) is removed with a view to exposing the micromechanical structures (34).
13. Semiconductor component with micromechanical structures arranged on the surface of a wafer comprising integrated circuits, characterised in that the semiconductor component (10) is manufactured in accordance with at least one of Claims 1 to 12.

12
14. Process for the manufacture of semiconductor components substantially as hereinbefore described with reference to the accompanying drawings.
15. A semiconductor component with micromechanical structures manufactured according to claim 14.