GB2309823A - SOI semiconductor device and method of fabricating the same - Google Patents
SOI semiconductor device and method of fabricating the same Download PDFInfo
- Publication number
- GB2309823A GB2309823A GB9626974A GB9626974A GB2309823A GB 2309823 A GB2309823 A GB 2309823A GB 9626974 A GB9626974 A GB 9626974A GB 9626974 A GB9626974 A GB 9626974A GB 2309823 A GB2309823 A GB 2309823A
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- United Kingdom
- Prior art keywords
- layer
- conduction
- gate electrode
- forming
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- 239000004065 semiconductor Substances 0.000 title claims description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000012535 impurity Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 26
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 24
- 229920005591 polysilicon Polymers 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 14
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 238000009413 insulation Methods 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 8
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims 2
- 229910052750 molybdenum Inorganic materials 0.000 claims 2
- 239000011733 molybdenum Substances 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 238000000059 patterning Methods 0.000 claims 1
- 238000007796 conventional method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Description
2309823 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
BACKGROUND OF THE INVENTION
In on a SOI is The present invention relates to a semiconductor device, and more particularly to a metal oxide semiconductor ("MOS") transistor formed on a silicon-on insulator ("SOI") substrate and a method of fabricating the same.
general, since a MOS transistor which is formed substrate reduces junction capacitance, improves endurance voltage of an isolation film and prevents latch-up that a parasitic thyristor turns on is prevented as compared with a MOS transistor which is formed on a bulk Si substrate, it is excellent in the performance speed of a device and resistant-soft error of integration degree.
A conventional method of fabricating a MOS transistor on such SOI substrate is illustrated FIG.1A and FIG.1B. As shown in FIG.1A, a SCI wafer 100 where an insulation film 12 and a thin Si layer are formed on a Si base substrate 11 is prepared. Herein, the base substrate 11 wherein the insulation film 12 is formed is bonded to a Si substrate and then the Si substrate is ground to form a thin Si layer, thereby obtaining the SOI wafer. To forming the Si layer thinly is to improve a gate electric 1 field dominance in a channel region, control punchthrough, and form a device minutely. Preferably, the Si layer is formed to be 500-1500A in a thickness.
Then, a field oxide 14 for isolation is formed at the predetermined portion of the Si layer 13 and a gate oxide 15 and a polysilicon layer 16 are formed on the Si layer.
As shown in FIG.1B, the polysilicon layer 16 and the gate oxide 15 are patterned to form a gate electrode 16A. In order to form a lightly doped drain ("LDW), impurity ions of low concentration are implanted into an exposed Si layer 13 to form a low concentration impurity region 17. An insulation film is deposited over the resultant and then anisotropically blanket-etched to form sidewall spacers 18 at the both sides of the gate electrode 16A. Impurity ions of high concentration are implanted into an exposed Si layer using the gate electrode 16A and the sidewall spacers as a mask to form a high concentration impurity region 19, thereby forming a junction region 20 of a LDD structure.
However, according to the conventional method of fabricating a MOS transistor, since the Si layer is thinly formed, the depth of the junction region in the MOS transistor is shallow according to the thickness of the Si layer 13. The depth of the junction region 2 formed, however, is insufficient, resulting in the junction resistance of the junction region is increased.
SUMARY OF THE INVENTION
An object of the present invention is to provide a MOS transistor formed on a SOI substrate and a method of fabricating the same which can reduce the junction resistance of a junction region.
Another object of the present invention is to provide a MOS transistor formed on a SOI substrate and a method of fabricating the same which can improve the performance speed thereof.
In accordance with one embodiment, there is provided a semiconductor device comprising: a SOI wafer including a Si base substrate and an insulation film and a Si layer which are formed on said Si base substrate; an isolation film formed at the selected portion of said Si layer; a gate electrode formed on said Si layer; a conduction layer spaced apart from said gate electrode, said conduction layer formed over said Si layer and said insulation film; sidewall spacers formed over said Si layer between said gate electrode and said conduction layer and at one side of said conduction layer over said isolation film; low concentration impurity regions formed at said Si layer below said sidewall spacers; and high 3 concentration impurity regions formed adjacent to said low concentration impurity regions at said Si layer below said conduction layer.
And, there is also provided a method of fabricating a semiconductor, comprising the steps of: providing a SOI substrate including a Si base substrate and an insulation film and a Si layer which are formed on said Si base substrate, said Si layer including an isolation film where is formed; forming conduction layers over said Si layer and said isolation film, said conduction layers spaced part from each other; forming a gate oxide film and a gate electrode on said Si layer between said conduction layers; forming low concentration impurity regions in said Si layer at both sides of said gate electrode; forming sidewall spacers over said Si layer between said gate electrode and said conduction layer and at one side of said conduction over said isolation film; and forming high concentration impurity regions in said conduction layers and said underlying Si layer adjacent to each low concentration impurity region.
BRIEF DESCRIPTION OF THE DRAWINGS
The objects and feature of the invention may be 25 better understood with reference to the following detailed description, appended claims, and attached 4 drawings wherein:
FIG.1A and FIG.1B are sectional views illustrating a process of fabricating a MOS transistor on a SOI substrate according to the prior art; and
FIG.2A through FIG.2E are sectional views illustrating a process of fabricating a MOS transistor on a SOI substrate in accordance with one embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG.2A, in accordance with one embodiment of the present invention, there is provided a SOI wafer 200 comprising a Si base substrate 21, an insulating film 22 and a Si layer 23 which are formed on the Si base substrate 21. A field oxide 24 for isolation between devices is formed at a predetermined portion of the Si layer 23 by a conventional selective oxidation method, and a first poly silicon layer 25 is formed over 20 the SOI wafer 200 to a thickness of 2000-5000A by a chemical vapor deposition("CVD"). Referring to FIG.2B, the poly silicon layer 25 is patterned to be remained over only the portion of the Si layer where a high concentration impurity region is to formed is to be formed and the field oxide 24 adjacent to the portion, thereby forming a polysilicon pattern 25A. 5
Herein, the polysilicon pattern 25A is form in order to make sure of the sufficient junction depth which is to be formed hereinafter. A gate oxide 26 is uniformly deposited in a thickness of 50-200A over the exposed Si layer 23 existing in between the polysilicon pattern 25A, the polysilicon patterns 25A itself, and the field oxide 26. A second polysilicon 27 for a gate electrode is deposited in a thickness of 2000-4000A over the gate oxide 26.
Referring to FIG.2C, the second polysilicon layer 27 is patterned to form a gate electrode 27A to be positioned between the polysilicon patterns 25A. Subsequently, impurity ions, for example phosphorous(P) ions are implanted into the portion of the Si layer between the polysilicon pattern 25A and the gate electrode 27A at a low concentration of 1x101' - 1x10"' atoms /CM3 with energy of 50-100KeV, to form low concentration impurity regions 28.
insulation film for a spacer. for example TEOS oxide film, is uniformly deposited to a thickness of approximately 1000-2000A over the resultant structure and then anisotropically etched to form sidewall spacers 29 at the both sides of the gate electrode 27A and the polysilicon pattern 25A.
Next, impurity ions, for example arsenic(As) ions are implanted into the polysilicon pattern 25A and the Referring to FIG.2D, an 6 underlying Si layer 23 at high 1X1019 atoms / CM3 with energy of concentration of 1X1013 _ 80-150KeV, to form high concentration impurity regions 30, and thereby form a junction region 31 of a LDD structure. Herein, the junction region 31 comprises the low concentration impurity region 28 and the high concentration impurity region 30 which are f ormed in the Si layer 23 and the highly doped polysilicon pattern 25A.
Referring to the FIG.2E, in order to increase the conductivity of the polysil-icon pattern 25A and the gate electrode 27A, a metal silicide 32 is selectively deposited only on the gate electrode 27A and the polysilicon pattern 25A by a selective deposition method. For use as the metal silicide, titanium silicide, tungsten silicide, tantalum silicide, or molybdenum silicide, are available, and any one of which can be used.
According to the MOS transistor formed on the SOI substrate of this invention, the shallow junction region is formed as well as the sufficient junction depth is ensured, thereby reducing the junction resistance.
While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense.
Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be 7 1 apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
8
Claims (22)
- What is claimed is is 1. A semiconductor device, comprising:a SOI wafer including a Si base substrate and an insulation film and a Si layer which are formed on said Si base substrate; an isolation film formed at the selected portion of said Si layer; a gate electrode formed on said Si layer; a conduction layer spaced apart from said gate electrode, said conduction layer formed over said Si layer and said isolation film; sidewall spacers formed over said Si layer between said gate electrode and said conduction layer and at one side of said conduction over said isolation film; low concentration impurity regions formed at said Si layer below said sidewall spacers; and high concentration impurity regions formed adjacent to said low concentration impurity regions at said Si layer below said conduction layer.
- 2. The semiconductor device claimed in claim 1, further comprising metal silicides formed on said conduction layers and said gate electrode oxide.9
- 3. The semiconductor as claimed in claim 2, wherein said metal silicide comprises any one of titanium silicide, tungsten silicide, tantalum silicide, or molybdenum.
- 4. The semiconductor as claimed in claim 1, wherein said conduction layer comprises a highly doped polysilicon layer.
- 5. The semiconductor as claimed in claim 4, wherein said highly doped polysilicon layer has a thickness of 2000-500o A.
- 6. The semiconductor as claimed in claim 4, wherein said highly doped polysilicon layer has the same concentration as said high concentration impurity regions.
- 7. The semiconductor as claimed in claim 4, wherein said highly doped polysilicon layer serves as a high concentration impurity region.
- 8. The semiconductor as claimed in claim 1, wherein said sidewall spacers comprises a TEOS oxide film.
- 9. The semiconductor as claimed in claim 1, wherein said gate electrode has a thickness of 2000-50oo A
- 10. A method of fabricating a semiconductor device, comprising the steps of:providing a SOI substrate including a Si base substrate and an insulation film and a Si layer which are formed on said Si base substrate, said Si layer including an isolation film where is formed; forming conduction layers over said Si layer and said insulation film, said conduction layers spaced part from each other; forming a gate oxide film and a gate electrode on said Si layer between said conduction layers; forming low concentration impurity regions in said is Si layer at both sides of said gate electrode; forming sidewall spacers over said Si layer between said gate electrode and said conduction layer and at one side of said conduction over said isolation film; and forming high concentration impurity regions in said conduction layers and said underlying Si layer adjacent to each low concentration impurity region.
- 11. The method as claimed in claim 10, wherein said step for forming said conduction layers includes the steps of: depositing a polysilicon layer over said SOI substrate; and Patterning said polysilicon layer to form said conduction layer over said insulation film and said Si layer.
- 12. The method as claimed in claim 11, wherein said polysilicon layer is deposited to a thickness of 2000- son A.
- 13. The method as claimed in claim 10, wherein said gate oxide film is formed to a thickness of 50-200 A.
- 14. The method as claimed in claim 10, wherein said gate electrode is formed to a thickness of 2000-4000A.
- 15. The method as claimed in claim 10, wherein said step for forming low concentration impurity regionsis carried out by implanting P ions into said Si layer at a low concentration of 1x101' - 1x101" atoms/ =3 with energy of 50-100KeV.
- 16. The method as claimed in claim 10, wherein the step for forming sidewall spacers includes the steps of:depositing an oxide film over said SOI wafer; and anisotropically etching to expose surfaces of said gate electrode and conduction layers, thereby forming 12 sidewall spacers over said Si layer between said gate electrode and said conduction layer and at one side of said conduction over said isolation film.
- 17. The method as claimed in claim 16, wherein said oxide film is TEOS oxide film.
- 18. The method as claimed in claim 16, wherein said oxide film is deposited to a thickness of 1000-2000A.
- 19. The method as claiqied in claim 10, wherein said step for forming high concentration impurity regions is carried out by implanting As ions into said conduction layers and said Si layer at a high concentration of IX1013 _ lx!019 atoms /CM3 with energy of 80-150KeV_
- 20. The method as claimed in claim 12, further comprising the step of forming metal silicides on said conduction layers and said gate electrode.
- 21. The method as claimed in claim 20, wherein said step of forming said metal silicides is carried out by a selective deposition method.
- 22. The method as claimed in claim 20, wherein said mer-al silicide comprises any one of titanium silicide, 13 tungsten silicide.silicide, tantalum silicide or molybdenum 1 14
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950069506A KR100209937B1 (en) | 1995-12-30 | 1995-12-30 | Method of fabricating transistor of semiconductor device |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| GB9626974D0 GB9626974D0 (en) | 1997-02-12 |
| GB2309823A true GB2309823A (en) | 1997-08-06 |
| GB2309823B GB2309823B (en) | 2000-11-15 |
Family
ID=19448490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9626974A Expired - Fee Related GB2309823B (en) | 1995-12-30 | 1996-12-27 | Semiconductor device and method of fabricating the same |
Country Status (4)
| Country | Link |
|---|---|
| JP (1) | JP3191091B2 (en) |
| KR (1) | KR100209937B1 (en) |
| DE (1) | DE19653656C2 (en) |
| GB (1) | GB2309823B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0924773A1 (en) * | 1997-12-15 | 1999-06-23 | Nec Corporation | Semiconductor device including a SOI MOSFET having source and drain electrodes comprising a metal silicide layer and method of making the same |
| WO2011102217A1 (en) * | 2010-02-19 | 2011-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0480635A1 (en) * | 1990-10-09 | 1992-04-15 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and a method of manufacturing thereof |
| EP0487220A2 (en) * | 1990-11-19 | 1992-05-27 | Mitsubishi Denki Kabushiki Kaisha | SOI-Field effect transistor and method of manufacturing the same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2507567B2 (en) * | 1988-11-25 | 1996-06-12 | 三菱電機株式会社 | MOS field effect transistor formed in semiconductor layer on insulator substrate |
| US5395784A (en) * | 1993-04-14 | 1995-03-07 | Industrial Technology Research Institute | Method of manufacturing low leakage and long retention time DRAM |
-
1995
- 1995-12-30 KR KR1019950069506A patent/KR100209937B1/en not_active IP Right Cessation
-
1996
- 1996-12-20 DE DE19653656A patent/DE19653656C2/en not_active Expired - Fee Related
- 1996-12-26 JP JP35709296A patent/JP3191091B2/en not_active Expired - Fee Related
- 1996-12-27 GB GB9626974A patent/GB2309823B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0480635A1 (en) * | 1990-10-09 | 1992-04-15 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and a method of manufacturing thereof |
| EP0487220A2 (en) * | 1990-11-19 | 1992-05-27 | Mitsubishi Denki Kabushiki Kaisha | SOI-Field effect transistor and method of manufacturing the same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0924773A1 (en) * | 1997-12-15 | 1999-06-23 | Nec Corporation | Semiconductor device including a SOI MOSFET having source and drain electrodes comprising a metal silicide layer and method of making the same |
| WO2011102217A1 (en) * | 2010-02-19 | 2011-08-25 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19653656A1 (en) | 1997-07-03 |
| GB9626974D0 (en) | 1997-02-12 |
| JPH1041517A (en) | 1998-02-13 |
| GB2309823B (en) | 2000-11-15 |
| KR970053098A (en) | 1997-07-29 |
| KR100209937B1 (en) | 1999-07-15 |
| DE19653656C2 (en) | 2003-02-20 |
| JP3191091B2 (en) | 2001-07-23 |
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Effective date: 20061227 |