GB2301937A - IC package with a ball grid array on a single layer ceramic substrate - Google Patents
IC package with a ball grid array on a single layer ceramic substrate Download PDFInfo
- Publication number
- GB2301937A GB2301937A GB9611726A GB9611726A GB2301937A GB 2301937 A GB2301937 A GB 2301937A GB 9611726 A GB9611726 A GB 9611726A GB 9611726 A GB9611726 A GB 9611726A GB 2301937 A GB2301937 A GB 2301937A
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuit
- digital integrated
- circuit package
- package
- vias
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/15—Containers comprising an insulating or insulated base
- H10W76/153—Containers comprising an insulating or insulated base having interconnections in passages through the insulating or insulated base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W40/00—Arrangements for thermal protection or thermal control
- H10W40/20—Arrangements for cooling
- H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
- H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
- H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
- H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
- H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US47109595A | 1995-06-06 | 1995-06-06 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB9611726D0 GB9611726D0 (en) | 1996-08-07 |
| GB2301937A true GB2301937A (en) | 1996-12-18 |
Family
ID=23870234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB9611726A Withdrawn GB2301937A (en) | 1995-06-06 | 1996-06-05 | IC package with a ball grid array on a single layer ceramic substrate |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPH09213829A (enExample) |
| KR (1) | KR970003879A (enExample) |
| DE (1) | DE19622650A1 (enExample) |
| GB (1) | GB2301937A (enExample) |
| MX (1) | MXPA96002171A (enExample) |
| TW (1) | TW299487B (enExample) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0915505A1 (en) * | 1997-11-06 | 1999-05-12 | Sharp Kabushiki Kaisha | Semiconductor device package, manufacturing method thereof and circuit board therefor |
| GB2377080A (en) * | 2001-09-11 | 2002-12-31 | Sendo Int Ltd | Integrated circuit package and printed circuit board arrangement |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6284566B1 (en) | 1996-05-17 | 2001-09-04 | National Semiconductor Corporation | Chip scale package and method for manufacture thereof |
| US6140708A (en) * | 1996-05-17 | 2000-10-31 | National Semiconductor Corporation | Chip scale package and method for manufacture thereof |
| US5783866A (en) * | 1996-05-17 | 1998-07-21 | National Semiconductor Corporation | Low cost ball grid array device and method of manufacture thereof |
| GB9818474D0 (en) * | 1998-08-26 | 1998-10-21 | Hughes John E | Multi-layer interconnect package for optical devices & standard semiconductor chips |
| US6198166B1 (en) * | 1999-07-01 | 2001-03-06 | Intersil Corporation | Power semiconductor mounting package containing ball grid array |
| DE10010461A1 (de) * | 2000-03-03 | 2001-09-13 | Infineon Technologies Ag | Vorrichtung zum Verpacken elektronischer Bauteile mittels Spritzgußtechnik |
| JP6397806B2 (ja) | 2015-09-11 | 2018-09-26 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
| EP0664562A1 (en) * | 1994-01-12 | 1995-07-26 | AT&T Corp. | Ball grid array plastic package |
| US5490324A (en) * | 1993-09-15 | 1996-02-13 | Lsi Logic Corporation | Method of making integrated circuit package having multiple bonding tiers |
-
1996
- 1996-06-05 MX MXPA96002171A patent/MXPA96002171A/es unknown
- 1996-06-05 JP JP8143210A patent/JPH09213829A/ja active Pending
- 1996-06-05 GB GB9611726A patent/GB2301937A/en not_active Withdrawn
- 1996-06-05 DE DE19622650A patent/DE19622650A1/de not_active Withdrawn
- 1996-06-07 KR KR1019960020252A patent/KR970003879A/ko not_active Withdrawn
- 1996-06-17 TW TW085107304A patent/TW299487B/zh active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5355283A (en) * | 1993-04-14 | 1994-10-11 | Amkor Electronics, Inc. | Ball grid array with via interconnection |
| US5490324A (en) * | 1993-09-15 | 1996-02-13 | Lsi Logic Corporation | Method of making integrated circuit package having multiple bonding tiers |
| EP0664562A1 (en) * | 1994-01-12 | 1995-07-26 | AT&T Corp. | Ball grid array plastic package |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0915505A1 (en) * | 1997-11-06 | 1999-05-12 | Sharp Kabushiki Kaisha | Semiconductor device package, manufacturing method thereof and circuit board therefor |
| US6157080A (en) * | 1997-11-06 | 2000-12-05 | Sharp Kabushiki Kaisha | Semiconductor device using a chip scale package |
| GB2377080A (en) * | 2001-09-11 | 2002-12-31 | Sendo Int Ltd | Integrated circuit package and printed circuit board arrangement |
| GB2377080B (en) * | 2001-09-11 | 2003-05-07 | Sendo Int Ltd | Integrated circuit package and printed circuit board arrangement |
| US6734555B2 (en) | 2001-09-11 | 2004-05-11 | Sendo International Limited | Integrated circuit package and printed circuit board arrangement |
| US6900544B2 (en) * | 2001-09-11 | 2005-05-31 | Sendo International, Limited | Integrated circuit package and printed circuit board arrangement |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19622650A1 (de) | 1996-12-12 |
| KR970003879A (ko) | 1997-01-29 |
| MXPA96002171A (es) | 2002-04-19 |
| TW299487B (enExample) | 1997-03-01 |
| GB9611726D0 (en) | 1996-08-07 |
| JPH09213829A (ja) | 1997-08-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |