GB2299893A

GB2299893A - Method for producing a quantum wire structure

Info

Publication number: GB2299893A
Application number: GB9610876A
Authority: GB
Inventors: Hirotaka Kizuki; Norio Hayafuji; Tatsuya Kimura
Original assignee: Mitsubishi Electric Corp
Current assignee: Mitsubishi Electric Corp
Priority date: 1992-09-10
Filing date: 1993-09-07
Publication date: 1996-10-16
Anticipated expiration: 2013-09-07
Also published as: GB2299893B; GB9610876D0; GB2299894A; GB9610877D0; GB2299709B; GB2299894B; GB2299707A; GB9610868D0; GB2299707B; GB2299709A; GB9610885D0

Description

2299893 1 METHOD FOR PRODUCING A QUANTUM WIRE STRUCTURE The present

invention relates to a method for producing a quantum wire structure.

BACKGROUND OF THE INVENITON

Recently, in manufacturing semiconductor laser diodes or quantum wire structures, a fine structure producing technique utilizing etching and regrowth has been developed. More specifically, this technique includes selectively etching away a portion of a crystal layer and growing an epitaxial layer on the surface of the crystal layer exposed by the etching, which epitaxial layer is electrically and optically different from the crystal layer, whereby desired electronic state is achieved. In this process, forming a fine structure in desired shape with high controllability and maintaining a clean regrowth interface are very important. Especially when AlGaAs is employed as a material of the device, since Al is an easily oxidizable material, an oxide film formed on the surface adversely affects the etching process, resulting in a fine structure in unwanted 2 shape. In addition, since the regrowth interface is contaminated, the quality of a regrown crystal layer is significantly deteriorated. These problems must be solved when the technique is employed in the manufacture of the devices.

Japanese Published Patent Application No. 58-53834 discloses a prior art method for etching an AlGaAs layer by reactive dry etching. In this method, a GaAs cap layer disposed on the AlGaAs layer prevents the surface of the AlGaAs layer from being oxidized. This prior art describes that a favorable AlGaAs etching is achieved for the first time when the reactive dry etching is performed from the GaAs cap layer. Japanese Published Patent Application No. 61-184892 also discloses an AlGaAs etching method employing a GaAs cap layer. In this prior art, the AlGaAs layer with the GaAs cap layer is etched by HC1 gas.

A description is given of problem? in the prior art AlGaAs etching method employing the GaAs cap layer.

Figures 30(a)-30(c) and 31(a)-31(c) are sectional views for explaining experiments conducted to confirm the effects of the prior art AlGaAs etching method. In the figures, reference numeral 1 designates a regrown GaAs layer, numeral 2 designates an AlxGal_xAs layer, numeral 23 designates a GaAs substrate, and numeral 211 designates a GaAs cap layer. A first sample and a second sample are formed according to the process steps illustrated in figures 30(a)-30(c) and figures 31(a)- 31(c), respectively.

Initially, as illustrated in figure 30(a), the Al.Gaj xAs layer 2 and the GaAs cap layer 211 are successively grown on the GaAs substrate 23 by MOCVD (first crystal growth of the first sample). On the other hand, in the step of figure 31(a), only the AlxGal-xAs layer 2 is grown on the GaAs substrate 23 by MOCVD (first crystal growth of the second sample). The AlxGal_xAs layer 2 is 2 im thick and the GaAs cap layer 211 is 0.1 pm thick. The first and second samples are taken out from the reaction chamber and left in the air for a few days. Thereafter, each of the first and second samples is etched by I gm from the surface using HC1 gas (figures 30(b) and 31(b)) and, subsequently, in the same reaction chamber, the GaAs layer 1 is grown to 2 pm by MOCVD (figures 30(c) and 31(c)).

Figures 32(a) and 32(b) illustrate SIMS (Secondary Ion mass Spectroscope) profiles of impurity ion concentrations in the vicinity of the regrowth interface, i.e., the interface between the AlxGal_xAs layer 2 and the regrown GaAs layer 1. Figure 32(a) illustrates the SIMS profile of the first sample shown in figure 30(c) and figure 32(b) illustrates the SIMS profile of the second sample shown in figure 31(c). In the figures, reference numeral 1 designates the regrown GaAs layer, numeral 2 designates the 4 AlxGal_xAs layer, and numeral 3 designates the regrowth interface. In both samples, segregations of oxygen (0) and chlorine (Cl) are observed in the vicinity of the regrowth interface. In addition, the dislocation density of the regrown GaAs layer 1 of the first sample is 5 x 105 pieces/cm2 and that of the second sample is 5 x 108 pieces/cm2.

These results are construed as follows. In the second sample, since the etching is started from the AIxGai-xAs layer 2 whose surface is oxidized, the oxide film on the surface reacts on Cl during the etching, and the products are attached to the wafer surface and segregated on the regrowth interface 3. The segregations of 0 and Cl on the regrowth interface 3 adversely affect the quality of the regrown GaAs layer 1.

On the other hand, in the first sample with the GaAs cap layer 211, since the cap layer prevents the surface of the AlxGal-xAs layer 2 from being oxidized, segregations of 0 and C1 in the vicinity of the regrowth interface 3 are reduced compared to the second sample, which means that the GaAs cap layer 211 improves the quality of the regrown GaAs layer 1.

However, the segregations of 0 and Cl on the regrowth interface are not completely prevented by the GaAs cap layer as shown in figure 32(a), and the dislocation density of the regrown GaAs layer of the first sample, i.e., 5 x 105 pieces/cm2, is, by one order of magnitude, higher than 1 x 104 pieces/cm2 that is a typical dislocation density required for a compound semiconductor device. This result shows that even a slight oxide film formed on the surface of the GaAs cap layer causes the segregations of 0 and Cl on the regrowth interface.

That is, the GaAs cap layer alone cannot provide a clean regrowth interface of the AlGaAs layer. Therefore, i is difficult to attain a clean regrowth interface and a high-quality regrown GaAs layer by the prior art etching method disclosed in Japanese Published Patent Application No. 58-53834.

Figure 34 is a schematic diagram for explaining a vapor phase etching method disclosed in Japanese Published Patent Application No. 62-153199. In the figure, reference numeral 241 designates a reactor, numeral 242 designates a pedestal, numeral 243 designates a semiconductor substrate, numeral 244 designates a resistance heating means, numeral 245 designates a bypass pipe, numeral 246 designates a low temperature region, numeral 247 designates a high temperature region, and numeral 248 designates an etching gas inlet.

in this etching method, initially, HC1 gas is sufficiently applied to the surface of the semiconductor substrate 243 in the low temperature region 246. Then, the substrate 243 is moved to the high temperature region and, after a prescribed time, it is returned to the low temperature region 246. This is one cycle of the etching process. In the low temperature region 246 of about 4000C, the substrate 243 is not etched by the HC1 gas but only Cl is adsorbed by the substrate occurs. When the substrate is moved to the high temperature region 247 of about 6000C, the adsorbed Cl escapes from the surface as GaC13, whereby a monomolecular layer level etching is carried out with high controllability.

However, this prior art vapor phase etching method has the following drawbacks.

In this etching method, the wafer is moved between the low temperature region and the high temperature region and, in each region, it is left for a prescribed time until the substrate temperature reaches a desired degree. Therefore, one cycle of the etching takes a few minutes, providing a very low etching rate. In addition, since it is difficult to control separations of As atoms and Ga atoms from the GaAs surface separately from each other, the etching is not smoothly carried out.

Figure 35 is a sectional view illustrating a quantum wire laser structure disclosed in Applied Physics Letters, 55(1989), pp. 2715 - 2717.In the figure, reference numeral 250 designates an n4' type GaAs substrate. There are successively disposed on the GaAs substrate 250 an n type Al y Gal_yAs first cladding layer 251, an AlXGai-xAs barrier layer 252, a GaAs quantum well layer 253, an AlxGai-xAs barrier layer 254, a p type Al y Gaj_yAs second cladding layer 255, a p+ type GaAs cap layer 256, and a Ti/Au electrode 257. An active layer 260 comprises the well layer 253 and the barrier layers 252 and 254. Reference numeral 258 designates high resistance regions formed by ion implantation. Reference numeral 259 designates an active region in which a quantum wire structure is formed.

In production, there are successively grown on the n+ type GaAs substrate 250 having a stripe-shaped V groove, the n type Al y Gal_yAs first cladding layer 251, the active layer 260 comprising the GaAs well layer 253 and the AlxGai-xAs barrier layers 252 and 254, the p type Al y Gal_yAs second cladding layer 255, and the p+ type GaAs cap layer 256. Then, impurity ions are selectively doped into portions of the second cladding layer 255 and the cap layer 256, forming the current narrowing layers 258.

While the active layer forms a quantum well structure on the flat surface of the substrate, it forms a quantum wire structure 259 at the bottom of the V groove.

The quantum wire structure 259 will be described in more detail. In figure 35, the GaAs substrate 250 has a 8 - (100) surface orientation. Since the stripe-shaped V groove is formed along the (61-1] direction by conventional photolithography and wet etching, a (111)A plane is exposed at opposite side walls of the V groove. Under the typical growth conditions of MOCVD (Metal Organic Chemical Vapor Deposition), the growth rate on the (100) surface is approximately equal to the growth rate on the (111)A surface. Therefore, the crystal layers 251 to 256 are grown parallel to each other along the V groove as shown in figure 35. Since the bottom end of the V groove is rounded, the (100) surface is partially exposed. Therefore, on the very narrow region at the bottom of the V groove where the (100) surface is exposed, the crystal growth proceeds perpendicularly to the (100) surface, so that the crystal layer grown on that region is thicker than the crystal layer grown on the side surfaces of the groove. In this way, the GaAs quantum well layer 253 forms the crescent-shaped quantum wire 259 at the bottom of the V groove.

However, this prior art laser structure has the following drawbacks. Since the crescent-shaped quantum wire 259 is formed continuously to the quantum well structure formed on the side surfaces of the V groove, the active region has electron states of the quantum well and the quantum wire, resulting in a multimode oscillation of the laser. Further, since the quantum wire is united with the quantum well, it is difficult to bring out characteristics of the quantum wire independently. Therefore, in this prior art, it is difficult to produce a plurality of quantum wires of uniform characteristics with high controllability and reproducibility.

Figure 33 is a perspective view illustrating a part of a high-power semiconductor laser with window layers grown on cleaved facets, disclosed in Japanese Journal of Applied Physics, Vol.30, 1991, pp. L904 - L906. In the figure, reference numeral 231 designates a p type GaAs substrate. There are successively disposed on the substrate 231 an n type GaAs current blocking layer 232, a p type AlO.33GaO.67AS cladding layer 233, a p type A10.08GaO.92As active layer 244, an n type AlO.33GaO.67As cladding layer 235, and an n type GaAs contact layer 236. Reference numeral 237 designates a cleaved (110) facet, and numeral As window layer grown on 23_8 designates an undoped AlO.4GaO.6 the cleaved (110) facet 237.

The window structure employed in this prior art laser will be described in more detail.

In the AlGaAs high-power laser, a lot of surface states are produced at the opposite oscillation facets. The surface states reduce the energy band gap in the vicinity of the facets compared with the energy band gap in the center of the laser. Therefore, regions in the vicinity of the - facets become light absorption regions with respect to the wavelength of the laser light, and the localized heat generation in the light absorption region is increased with an increase in the light output. Since the energy band gap is reduced with the temperature rise, the absorption of laser light is further encouraged, increasing the temperature at the facet, i.e., so-called positive feedback occurs. If the temperature rise is sufficient, localized melting of the semiconductor materials can occur, resulting in catastrophic optical damage (COD) that destroys the laser. In order to reduce the light absorption at the opposite oscillation facets of the laser and increase the power level without risk of COD, the window layers having energy band gap larger than that equivalent to the oscillation wavelength of the laser are formed on the facets.

In the prior art high-power laser, the window layers 238 are formed according to the process steps described in the following. Initially, the laser structure is fabricated using conventional wet etching and LPE growth. More specifically, after growing the n type GaAs current blocking layer 232 on the p type GaAs substrate 231, the stripeshaped V groove is formed in the center of the wafer penetrating through the current blocking layer 232. Then, the p type AlO.33Ga0.67As cladding layer 233, the p type

A10.08Gao.92As active layer 244, the n type A10.33Gao.67AS cladding layer 235, and the n type GaAs contact layer 236 are successively grown on the wafer. After scrubbing the wafer to a desired thickness, the wafer is cleaved in a plurality of bars each having a width equal to the resonator length of the laser. The resonator length of a typical high-power layer is 300 - 600 gm. Then a material having an energy band gap laser than the energy band gap equivalent to the oscillation wavelength is deposited on a part of the bar-shaped wafer corresponding to the resonator facet, preferably by MOCVD.

In this prior art laser, since the laser oscillation wavelength is 830 nm that is equivalent to 1.49 eV, the undoped AlO.4Ga0.6A9 layer 238 having energy band gap of about 1.93 eV is employed as the window layer. After forming electrodes and coating the window layers, the barshaped wafer is divided into a plurality of chips, completing the laser device shown in figure 33. The prior art literature, i.e., Japanese Journal of Applied Physics, Vol.30, 1991, pp. L904 - L906, describes that the window layers prevent the COD and increase the output power and life time of the laser.

However, the prior art laser with the window layers has the following drawbacks.

In fabricating semiconductor lasers, generally, process steps until the formation of electrodes are carried out on a wafer to secure mass production with high reproducibility. That is, the production method of this prior art, in which the window layers are formed on portions corresponding to resonator facets after cleaving the wafer in a plurality of bars each having a width equivalent to the resonator length, provides very poor producibility, so that this method is not industrially available. Further, when the window layers are formed by MOCVD after the formation of the resonator facets by cleaving, the cleaved facets are easily oxidized and surface states are produced thereon so long as the cleaving is performed in the air. Since the surface states on the facets adversely affect the effect of the window layers, the process steps from the cleaving to the growth of the window layers have to be carried out in inactive gas or in vacuum.

The reason why the prior art laser is fabricated in such complicated process will be described.

Since the resonator facets of the laser also serve as laser light reflecting facets, they must be optically flat. In addition, they must be perpendicular to the resonator length direction. Therefore, the prior art method, in which the semiconductor substrate having (100) surface orientation is employed and the resonator facets perpendicular to the (100) surface are formed by cleaving, has been proposed and employed as a general production method. However, with the advance of developments of high power and multifunction semiconductor lasers, a technique for fabricating resonator facets of lasers without cleaving the wafer has been desired, and facet formation methods utilizing dry etching, such as reactive ion etching (RIE), have been developed. However, the present RIE technique has a problem of physical damage due to the collision of ions, that adversely affects the quality of crystal layers at the resonator facets, although perpendicular facets can be produced by RIE. Further, it is difficult to produce a facet as smooth as a cleavage plane. Therefore, the facet formation technique using RIE is not yet established. For the reasons described above, the oscillation facets are formed by cleaving at present.

Figures 36(a) to 36(e) are sectional views illustrating process steps in a method for fabricating a semiconductor laser disclosed in, for example, IEEE Journal of Quantum Electronics, Vol.23, 1987, p.720.

Initially, there are successively grown on an n type GaAs substrate 300 an n type GaAs buffer layer 301, an n type AlGaAs cladding layer 302, an undoped GaAs active layer 303, a p type AlGaAs cladding layer 304, and an n type GaAs current blocking layer 305. These layers are grown by MOCVD on a substrate with a (100) surface orientation. Thereafter, an SiO film 306 is deposited on the current blocking layer 305 by sputtering and patterned by conventional photolithography to form a stripe-shaped opening along the [C7111 direction (figure 36(a)).

In the step of figure 36(b), the n type GaAs current blocking layer 305 is etched using a tartaric acid base etchant, forming a stripe-shaped groove. In this etching process, a very thin portion of the current blocking layer 305 is left at the bottom of the groove. If the etching is carried out until the surface of p type AlGaAs cladding layer 304 is exposed at the bottom of the groove, the exposed surface is unfavorably oxidized in the air and the solution, that adversely affects a crystal layer grown thereon. In addition, (111)A planes are exposed on the opposite side surfaces of the groove.

In the step of figure 36(c), the wafer is put in a reactor of an MOCVD apparatus, and a portion of the current blocking layer 305 remaining at the bottom of the groove is selectively removed by vapor phase etching using HC1 gas and AsH3 gas.

Subsequently, in the same reactor, a p type AlGaAs cladding layer 307 is selectively grown in the groove by MOCVD (figure 36(d)). As shown in figure 36(d), the p type AlGaAs cladding layer 307 is not grown with a flat surface. The reason will be described using figure 37. As shown in figure 37, the growth of the cladding layer 307 starts from the opposite side surfaces of the groove, i.e., the (111)A planes, and from the flat bottom surface of the groove, i.e., the (100) surface. After the groove is completely filled with the layer 307, the growth proceeds forming the (111)B plane that forms an angle of about 54 with respect to the (100) surface, resulting in the uneven surface of the cladding layer 307.

After removing the SiO film 306 using a hydrogen fluoride (HF) bass etchant, a p type GaAs contact layer 308 is grown by MOCVD (figure 36(e)). Even if the p type GaAs contact layer 308 is grown thick as shown in figure 36(e), the wafer surface remains uneven.

In this prior art method, the uneven surface of the wafer adversely affects the process after the crystal growth, for example, a photolithography for patterning an upper electrode. Further, if the semiconductor laser fabricated by this prior art method is adhered to a heat sink with the p type GaAs contact layer in contact with the heat sink (junction down), compressive stress is applied to the active layer, reducing the reliability of the laser.

By the way, a technique for growing a crystal layer on a different kind substrate is a key technology for realizing an advanced information processing device, for example, a hybrid IC including an Si electron device and a compound semiconductor light emitting device. Therefore, this - 16 crystal growth technique has been extensively studied in many laboratories. Especially a technique for growing GaAs layer on Si has been desired because it has very wide application. In the growth of GaAs on Si, however, unwanted stress is applied to the GaAs layer due to a difference in thermal expansion coefficients between GaAs and Si, resulting in cracks in the GaAs layer.

Figures 38(a) to 38(e) are sectional views illustrating a method for growing a GaAs layer on an Si substrate in which the generation of cracks is suppressed, disclosed in U.S. Patent No. 514593.

Initially, as illustrated in figure 38(a), a first GaAs layer 503 is grown on a first surface of an Si substrate 501 by a two-stage growth method and, thereafter, a BN (boron nitride) film 502 is formed on a second surface of the Si substrate 501 at room temperature. In the two- stage growth method, a low temperature buffer layer 100 - 400 A thick is grown at a temperature below 5000C and, thereafter, the wafer is heated to about 7000C that is suitable for the growth of GaAs and the GaAs layer 503 is grown to a desired thickness. This two-stage growth method suppresses the three-dimensional growth of GaAs, providing a high-quality epitaxial layer.

Then, as illustrated in figure 38(b), grooves 504 are formed by selectively removing portions of the first GaAs layer 503. These grooves 504 are easily formed by conventional photolithography and wet etching.

After heating the wafer with the grooves 504 to 700 BOOOC (figure 38(c)), a second GaAs layer 505 and a third GaAs layer 506 to be active layers of the device are successively grown on the wafer by MOCVD (figure 38(d)). During the growth, since a spontaneous oxide film is formed on the surface of the Si substrate 501 exposed in the grooves 504, the GaAs crystal is not grown in the grooves but selectively grown on the first GaAs layer 503.

Thereafter, portions of the GaAs layers 503, 505, and 506 in the vicinity of each groove 504 are selectively removed, forming a groove 507 larger than the groove 504. The reason why the groove 507 is formed will be described hereinafter. During,growing the second and third GaAs layers 505 and 506 in the step of figure 38(d), the source gases reaching the groove 504 do not deposit GaAs on the Si substrate 501. The gases are used for the GaAs growth in the vicinity of the groove 504. Therefore, the thickness of the GaAs layer is increased in the vicinity of the groove, and especially the opposite edges of the groove are sharply swollen. Since mechanical stress is concentrated in this swollen part, cracks are generated from this part. The groove 507 is formed by selectively removing the swollen part.

In addition, the BN film 502 on the second surface of the Si substrate suppresses the warpage of the wafer.

As shown in figure 40, the generation of cracks in the GaAs layer grown on the Si substrate is closely related with the thickness of the GaAs layer. More specifically, the cracks start to occur when the thickness of the GaAs layer exceeds 3 pm and increase with an increase in the thickness of the GaAs layer. Most of the cracks are generated from the abnormally grown part of the GaAs layer at the edge of the wafer.

Therefore, in the prior art method illustrated in figures 38(a)-,38(e), the first GaAs layer 503 thinner than 2 pm, that is hardly cracked, is grown first and then the grooves 504 are formed surrounding a region where a device is to be formed (hereinafter referred to as a device region). Thereafter, the second GaAs layer 505 and the third GaAs layer 506 to be active regions of the device are successively grown on the first GaAs layer 503. Therefore, the grooves 504 prevent the cracks produced at the edge of the wafer from reaching the device region.

However, this prior art method has the following problems.

Figures 39(a) and 39(b) are diagrams for explaining the problems in the prior art method for growing GaAs on Si. In figure 39(a), reference numeral 510 designates the GaAs layer and numeral 511 designates cracks. In our experiment, most of the cracks in the GaAs layer are produced from the edge of the wafer and stopped by the grooves 504 before reaching the device region. However, we found more than ten cracks in the 5 cm x 5 cm region inside the grooves. On investigation, it was found that the source of these cracks is a rhombic pit shown in figure 39(b) which is produced from the interface between the first GaAs layer 503 and the second GaAs layer 505.

The case of the rhombic pit will be described. After the growth of the first GaAs layer 503, the grooves 504 are formed by conventional photolithography and wet etching. In this process, a photoresist deposited on the wafer is not completely removed but partially remains on the wafer as impuri ties that cause the rhombic pit. Generally, cleaning the surface of the GaAs layer is rather difficult compared to cleaning the surface of the Si substrate, so that it is very difficult to clean the surface of-the GaAs layer which is once contaminated by the deposition of the photoresist and the like. However, it is necessary to separate the device region from the wafer edge by the grooves 504 to prevent the cracks produced at the edge of the wafer from reaching the device region.

As a solution to the above-described problem, a GaAs growth on an Si substrate which is previously patterned using an insulating film is proposed. In this method, however, polycrystal is unfavorably deposited on the insulating film during growing the low temperature buffer layer. Generally, it is difficult to favorably perform a selective growth at a low temperature below 500C, and the polycrystal is deposited on the insulating film. If a GaAs layer is grown on the polycrystal at a temperature of about 7000C, another polycrystal is produced. As the result, crystals grown on the surface of the wafer are connected to each other, so that the isolation of the region patterned by the insulating film is impossible. Therefore, the cracks produced from the wafer edge unfavorably reach the device region through the polycrystal on the insulating film.

RUMMARY OF THV TNVPNTTON An object of the present invention is to provide a method for producing a semiconductor device in which a gas etching is combined with a crystal growth using MOCVD, which provides a clean regrowth interface of AlGaAs and prevents the segregation of impurity on the regrowth interface.

Another object of the present invention is to provide an AlGaAs etching technique using a chlorine containing gas which provides an etching surface as smooth as a cleavage plane.

A further object of the present invention is to provide method and apparatus for etching a compound semiconductor, in which the etching is controlled with one atomic layer level and a smooth etching surface is attained.

Another object of the present invention is to provide a method for fabricating quantum wire structures with high uniformity and high controllability.

Still another object of the present invention is to provide a method for fabricating a semiconductor laser in which resonator facets are formed by etching, which facets are perpendicular to the resonator length direction, optically very flat, as smooth as a mirror, and are not physically damaged.

Yet another object of the present invention is to provide a method for fabricating a semiconductor laser in which a flat surface is attained after the crystal growth, which flat surface facilitates the process after the crystal growth and secures high reliability even if the junctiondown bonding is employed.

A still further object of the present invention is to provide a method for growing a crystal layer on a different kind substrate in which a favorable selective growth is performed on a substrate with an insulating film pattern, at temperature lower than 500C, without producing cracks in region where a device is to be formed.

Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood, however, that the detailed description and specific embodiment are givenby way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

According to a first aspect of the present invention, in a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor laye-including aluminum, a mask pattern comprising an insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown layer.

According to a second aspect of the present invention, in a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern comprising an insulating film is formed on a part of the compound semiconductor cap layer, an oxide film on the compound semiconductor cap layer is removed in a reaction chamber, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in the reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown layer.

According to a third aspect of the present invention, in a method for producing a semiconductor device including etching an AlxGal_xAs (0 5 x 5 1) layer by a dry etching, the dry etching is a gas etching using a chlorine containing etching gas, a group V gas, and a hydrogen gas which are supplied at the same time. The chlorine containing etching gas is HC1 gas or C1.2 gas, the group V gas is arsine (ASH3) gas, tertiary butyl arsine (C4H9ASH2) gas, or trimethylarsine ((CH3)3As) gas. The gas etching is carried out under conditions that a partial pressure of the group V gas is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5. Therefore, a very smooth etching surface is attained and the etching surface is not damaged.

According to a fourth aspect of the present invention, in a method for fabricating a semiconductor laser, a plurality of AlxGal_xAs (0 S x S 0) layers are grown on a - 24 semiconductor substrate to form a prescribed laser diode structure, an etching mask comprising an insulating film is formed on a part of the laser diode structure, and an oscillation facet of the laser diode is formed by a gas etching using an etching gas selected from HC1 gas and C12 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and a hydrogen gas, which are supplied at the same time. The gas etching is performed under conditions that the partial pressure of the group V gas is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5. Therefore, the laser oscillation facet as smooth as a cleavage facet is easily formed by the gas etching.

According to a'fifth aspect of the present invention, in a method for fabricating a refractive index guide type semiconductor laser with a window structure, a plurality of AlxGal_xAs (0 5 z 5 0) layers are grown on a semiconductor substrate to form a semiconductor multilayer structure including an active region, a protective film is formed on a part of the semiconductor multilayer structure, the semiconductor multilayer structure is selectively etched away by a gas etching using an etching gas selected from HC1 gas and C12 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine HCH3)3As) gas, and a hydrogen gas, which gases are supplied at the same time, using the protective film as a mask. The gas etching is performed under conditions that the partial pressure of the group V gas is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5. Thereafter, a semi-insulating or high-resistivity semiconductor material having an energy band gap larger than that of the laser oscillation region is grown on opposite sides of a ridge structure formed by the etching process, providing a current blocking structure and a window structure at the same time. After removing the protective film, an ohmic contact layer is grown on the surface of the wafer. Therefore, the semiconductor laser diode having the window layer on the facet is easily fabricated.

According to a sixth aspect of the present invention, a method for producing a semiconductor device including etching a III-V compound semiconductor layer comprises a first etching step Including introducing a group V gas and a chlorine containing gas into a reactor so that the chlorine containing gas is supplied like a pulse for a time interval shorter than the supply time of the group V gas, and a second etching step including halting the supply of the group V gas and the chlorine containing gas and purging the inside of the reactor with a hydrogen gas. The first - 26 etching step and the second etching step are alternatingly repeated. Therefore, it is possible to control the etching at one-atomic layer level, providing a smooth etching surface.

According to a seventh aspect of the present invention, an apparatus for producing a semiconductor device includes a rotatable discoid susceptor an which a semiconductor wafer is disposed, and means for partitioning the surface of the susceptor into a plurality of regions using a hydrogen gas is prepared. At least one of the regions is filled with a gas mixture comprising a group V material hydride gas, a chlorine containing gas, and a hydrogen gas. At least one of the regions is filled with a hydrogen gas. A semiconductor wafer on the susceptor is successively moved through the regions with the rotation of the susceptor. Therefore, it is possible to control the etching at oneatomic layer level, providing a smooth etching surface.

According to an eighth aspect of the present invention, in a method for producing a semiconductor device, an apparatus including a rotatable discoid susceptor on which a semiconductor wafer is disposed and means for partitioning the surface of the susceptor into a plurality of regions using a hydrogen gas is prepared. At least one of the regions is filled with a gas mixture comprising a group V material hydride gas, a chlorine containing gas, and a hydrogen gas. At least one of the regions is filled with a hydrogen gas. A semiconductor wafer on the susceptor is successively moved through the regions with the rotation of the susceptor. A first etching step is carried out in the region filled with the gas mixture and a second etching step is carried out in the region filled with the hydrogen gas. The first etching step and the second etching step are alternatingly repeated. Therefore, it is possible to control the etching at one-atomic layer level, providing a smooth etching surface.

According to a ninth aspect of the present invention, in a method for producing a quantum wire structure, a first semiconductor layer is formed on a semiconductor substrate with a (100) surface orientation, an etching mask having a stripe-shaped opening extending along a <011> direction is formed on the first semiconductor layer, the first semiconductor layer is selectively etched away by a gas etching using an etching gas selected from HC1 gas and C12 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and a hydrogen gas, which gases are introduced into a reactor at the same time. The gas etching is carried out under conditions that the partial pressure of the group V gas is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5, thereby forming a stripe-shaped V groove with side surfaces of (111)B planes. Thereafter, a second semiconductor layer having an energy band gap smaller than that of the first semiconductor layer is formed in the vicinity of the bottom of the V groove, and a third semiconductor layer having an energy band gap larger than that of the second semiconductor layer is formed on the second semiconductor layer.

According to a tenth aspect of the present invention, in a method for producing quantum wire structures, a first high-resistivity layer comprising a first semiconductor is grown on a semiconductor substrate, a second highresistivity layer comprising a second semiconductor and having an electron affinity smaller than that of the first semiconductor and a third high-resistivity layer comprising the first semiconductor are successively grown on the first high-resistivity layer, and alternating projections and recesses are formed in the second high resistivity layer so that the cross section of each recess is an inverted triangle. The alternating projections and recesses are formed by a gas etching using an etching gas selected from HCI gas and C12 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and a hydrogen gas, which are introduced into a reactor at the same time, under - 29 conditions that the partial pressure of the group V gas is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5. Therefore, high-quality quantum wires are formed with high controllability.

According to an eleventh aspect of the present invention, in a method for fabricating a semiconductor laser, at least a first conductivity type Al y Gal_yAs cladding layer, an AlzGal_zAs (0 5 z < y) active layer, a second conductivity type AlwGal-wAs (z < w) cladding layer, and a first conductivity type GaAs current blocking layer are successively grown on a first conductivity type GaAs substrate with a (100) surface orientation, an insulating film having a stripe-shaped opening extending along a <011> direction is formed.on the semiconductor wafer after the crystal growth process, the semiconductor wafer is selectively etched away by a vapor phase etching with a chlorine containing gas using the insulating film as a mask, forming a stripe-shaped groove with side surfaces of Clll)B planes and a bottom surface of the second conductivity type cladding layer, and a second conductivity type AlwGal_wAs layer is grown in the stripe-shaped groove. Since no crystal is grown on the (111)B planes, the groove is filled with the crystal layer grown from the bottom surface of the groove, resulting in a flat surface of the wafer.

According to a twelfth aspect of the present invention, in a method for fabricating a semiconductor laser, at least a first conductivity type Al y Gal-yAs cladding layer, an AlzGal_zAs (0 5 z < y) active layer, and a second conductivity type AlwGal-wAs (z < w) cladding layer are successively grown on a first conductivity type GaAs substrate with a (100) surface orientation, a stripe-shaped insulating film pattern extending along a <011> direction is formed on a part of the semiconductor wafer after the crystal growth process, an oxide film on the surface of the semiconductor wafer is removed by an ammonium sulfide treatment or a surface cleaning conducted in a reaction chamber, the semiconductor wafer is selectively etched away by a vapor phase etching with a chlorine containing gas using the insulating film pattern as a mask, forming a stripe-shaped ridge structure with side walls of Clll)B planes, and a current blocking layer is formed on opposite sides. of the ridge structure contacting the side walls. Therefore, a highly-reliable AlGaAs buried heterojunction laser is achieved.

According to a thirteenth aspect of the present invention, in a method for epitaxially growing a III-V compound semiconductor layer on a substrate with an insulating film pattern by MOCVD, the epitaxial growth is carried out while supplying source gases and HC1 gas or C 12 gas at the same time under the condition that the molar flow rate of the HC1 gas or C12 gas to the group III gas is lower than 0.3.

According to a fourteenth aspect of the present invention, in a method for epitaxially growing a semiconductor layer comprising a second semiconductor material on a semiconductor substrate comprising a first semiconductor material by MOCVD, an insulating film is deposited on the semiconductor substrate and patterned so as to surround a region of the semiconductor substrate on which a device is to be produced, a low temperature buffer layer comprising the second semiconductor material is grown on the semiconductor substrate while supplying source gases and HC1 gas or C12 gas at a temperature lower than 500C, the semiconductor layer. comprising the second semiconductor material is grown at a temperature higher than 6000C. Therefore, cracks produced in the semiconductor layer grown on the different kind semiconductor substrate are suppressed.

According to a fifteenth aspect of the present invention, in the method for epitaxially growing the low temperature buffer layer comprising the second semiconductor material, the molar flow rate of the HC1 gas or C12 gas to the group III gas is lower than 0.3. Therefore, cracks produced in the semiconductor layer grown on the different kind semiconductor substrate are suppressed, and a high- quality crystal layer is grown on the substrate.

RRTPr nRSrRTPTTnN oF THE nRAwTNas Figures l(a)-l(e) are sectional views illustrating a method for fabricating a semiconductor device in accordance with a first embodiment of the present invention.

Figure 2 is a graph illustrating SIMS profiles of impurity ion concentrations for explaining an effect of a compound semiconductor etching method in accordance with a second embodiment of the present invention.

Figures 3(a) and 3(b) are graphs for explaining a method for fabricating a semiconductor device in accordance with a third embodiment of the present invention.

Figures 4(a)-4(c) are sectional views illustrating a method for fabricating a semiconductor laser in accordance with a fourth embodiment of the present invention.

Figures 5 and 6 are perspective views for explaining a method for fabricating a semiconductor laser in accordance with a fifth embodiment of the present invention.

Figure 7 is a perspective view illustrating a semiconductor laser fabricated by the method according to the fourth embodiment of the present invention.

Figures B(a)-8(h) and 9(a)-9(g) are sectional views illustrating process steps in a method for fabricating a refractive index guide type semiconductor laser with window 33 - structure in accordance with a sixth embodiment of the present invention.

Figures 10(a) and 10(b) are perspective views illustrating process steps corresponding to the step of figures 8(d) and 9(d) and the step of figures 8(f) and 9(f), respectively.

Figures 11(a)-11(d) are sectional views illustrating process steps in a method for fabricating a ridge type semiconductor laser in accordance with a seventh embodiment of the present invention.

Figure 12 Is a perspective view illustrating a ridge type semiconductor laser fabricated by the method according to the seventh e diment of the present invention.

Figure 13 is a diagram illustrating a gas introduction sequence for explaining a method for fabricating a semiconductor device in accordance with an eighth embodimen of the present invention.

Figure 14 Is a graph illustrating an etching rate for explaining a method for fabricating a semiconductor device in accordance with the eighth embodiment of the present invention.

Figure 15 is a schematic diagram illustrating an apparatus for fabricating a semiconductor device in accordance with a ninth embodiment of the present invention.

Figure 16 is a schematic diagram illustrating a plan view of the apparatus of figure 15.

Figures 17 and 18 are sectional views for explaining a method for fabricating a quantum wire structure in accordance with a tenth embodiment of the present invention.

Figure 19 is a sectional view illustrating a quantum wire structure in accordance with the tenth embodiment of the present invention.

Figures 20(a)-20(d) are sectional views illustrating process steps in a method for fabricating the quantum wire structure of figure 19.

Figure 21 is a sectional view illustrating a quantum wire structure.

Figures 22(a)-22(e) are sectional views illustrating process steps in a method for fabricating the quantum wire structure of figure 21 in accordance with an eleventh embodiment of the present invention.

- Figures 23(a)-23(c) are sectional.views illustrating process steps in a method for fabricating a semiconductor laser In accordance with a twelfth embodiment of the present invention.

Figure 24 Is a perspective view of the semiconductor laser in the process step of figure 23(a).

Figure 25 Is a sectional view for explaining a crystal growth in a groove in the process step of figure 23(c).

Figures 26(a)-26(e) are sectional views illustrating process steps in a method for fabricating a semiconductor laser in accordance with a thirteenth embodiment of the present invention.

Figures 27(a)-27(d) are sectional views illustrating process steps in a crystal growth method in accordance with a fourteenth embodiment of the present invention.

Figure 28 is a graph illustrating HU flow rate dependence of the crystal growth in a crystal growth method according to a fifteentW embodiment of the present invention.

Figure 29 is a graph illustrating 4.2 K photoluminescence spectrum in the crystal growth method according to the fifteenth embodiment of the present invention.

Figures 30(a)-30(c) are sectional views for explaining problems in a compound semiconductor etching method according to the prior art.

Figures 31(a)-31(c) are sectional views for explaining problems in a compound semiconductor etching method according to the prior art.

Figures 32(a) and 32(b) are graphs illustrating SIMS profiles of impurity ion concentrations for explaining problems in the compound semiconductor etching methods according to the prior art.

- 36 Figure 33 is a perspective view illustrating a prior art semiconductor laser with window structure.

Figure 34 is a schematic diagram for explaining a compound semiconductor etching method according to the prior art.

Figure 35 is a sectional view for explaining problems of a quantum wire of a prior art quantum wire laser.

Figures 36(a)-36(e) are sectional views illustrating process steps in a method for fabricating a semiconductor laser according to the prior art.

Figure 37 is a sectional view for explaining a crystal growth in a groove in the process step of figure 36(d).

Figures 38(a)-38(e) are sectional views illustrating process steps in a method for growing a GaAs layer on an Si substrate according,to the prior art.

Figures 39(a) and 39(b) are diagrams for explaining problems in the method of figures 38(a)-38(e).

Figure 40 is a graph illustrating a relation between the number of cracks produced in a GaAs layer grown on an Si substrate and the thickness of the GaAs layer.

nFTATT,pn nFgrRTPTTnN QF PRFFFRRPn FMBnnTMFNTA Figures l(a)-l(e) are sectional views illustrating a method for producing a semiconductor device in accordance with a first embodiment of the present invention.

Initially, an Al.Gal_,As layer 2 and a GaAs cap layer 11 are successively grown on a GaAs substrate 23 by MOCVD (first crystal growth). Preferably, the AlxGaj-xAs layer 2 is 2 pm thick and the cap layer 11 is 0.1 pm thick. This sample wafer is taken out from the reaction chamber and left in the air for a few days. During exposed to the air, a thin oxide film 12 is formed on the surface of the GaAs layer 11. The wafer in this state is illustrated in figure 1(a).

In the step of figure l(b), an SiN film pattern 21 of a desired shape is formed on the surface of the wafer. Then, the wafer is immersed in an ammonium sulfide solution at 60C for three hours. In this embodiment, (NH4)2S is employed as the ammonium sulfide solution. During this process, a part of the oxide film 12 which is not masked with the SiN film 21 is etched away and a sulfur film 13 is formed as shown in figure 1(c). Then, the wafer is put in an MOCVD chamber and annealed in a hydrogen ambience at 4500C for thirty minutes. Then, a part of the wafer that is not masked with the SiN film 21 is etched down to a depth of 1 = using a gas mixture of AsH2:HC1:H2 and, subsequently, a GaAs layer 1 is grown in the same chamber.

Figure 2 illustrates SIMS profiles of impurity ion concentrations in the vicinity of the regrowth interface 3 (cross section taken along line IIII of figure l(e)) of the sample wafer fabricated according to the process steps of 38 - figures 1(a)-l(e).

In figure 2, no segregation of impurities, i.e., 0 and Cl, on the regrowth interface 3 is observed and the dislocation density of the regrown GaAs layer 1 is improved to 1 x 104 ions/cm2. In the prior art method employing only the GaAs cap layer, the segregations of impurities on the regrowth interface are not completely prevented as shown in figure 32(a). In this first embodiment of the present invention, since the GaAs cap layer 11 is employed and the (NH4)2S treatment is performed before the etching process, the cleanliness of the regrowth interface and the quality of the regrown GaAs layer are significantly improved.

The effect of the (NH4)2S treatment is described in Applied Physics Letters, Vol.58, No.9, 1989, pp.1340 - 1344. The oxide film on the surface of the GaAs layer is etched away by the (NH4)2S treatment, and sulfur (S) atoms are attached to the surface of the GaAs layer forming a surface protection film that prevents the GaAs surface from being oxidized.

Meanwhile, in Japanese Published Patent Application No. 4-10683, before growing a crystal layer on a GaAs or AlGaAs; substrate, the surface of the substrate is cleaned using ammonium sulfide to remove an oxide film on the surface and to discourage the generation of another oxide film, whereby the quality of the crystal layer grown on the surface is improved.

However, in order to grow a high-quality GaAs layer on the surface of the GaAs layer covered with the sulfur thin film, the sulfur thin film must be removed by some means. According to an experiment by the inventor of this invention, the S atoms on the GaAs surface are not completely removed by the thermal cleaning due to the temperature rise before the MOCVD growth, and the S atoms segregated on the regrowth interface deteriorate the quality of the regrown crystal layer. On the other hand, no effective means for removing the sulfur thin film serving as a surface protection film has been reported.

In order to attain a clean regrowth interface after the vapor phase etching, the surface before the etching process must be unoxidized., Although the (NH4)2S treatment is suitable for this purpose, the sulfur film deposited on the surface during the treatment cannot be.completely removed as described above. The inventors of the present invention found that the HC1 gas etching is very effective to remove the sulfur film and confirmed that a clean regrowth interface is attained after the gas etching if the (NH4)2S treatment is combined with the HCL gas etching.

As described above, the GaAs cap layer alone cannot provide a clean regrowth interface after the vapor phase etching because the etching is adversely affected by the - very thin oxide film on the GaAs cap layer. Therefore, cleaning the surface of the GaAs cap layer is very important. In this first embodiment, since the (NH4)2S treatment, which is a conventional surface cleaning technique, is combined with the HC1 gas etching, an effective and practical surface treatment is attained for the first time, resulting in an advanced composite process comprising the HCI gas etching and the MOCVD growth.

While in the above-described first embodiment the wafer with the sulfur film is put in the MOCVD chamber and annealed in the hydrogen ambience, the annealing is not necessarily carried out in the hydrogen ambience. In addition, the annealing may be performed during increasing the wafer temperature in the reactor.

While in the above-described first embodiment the compound semiconductor including aluminum is AlGaAs and the compound semiconductor grown thereon and including no aluminum is GaAs, the present invention may be applied to other crystal growths employing other compound semiconductors.

A description is given of a method for producing a semiconductor device in accordance with a second embodiment of the present invention.

In the second embodiment of the present invention, after forming the GaAs cap layer 11 on the AlGaAs layer 2 A (figure l(a)) and forming the insulating mask 21 on a part of the cap layer (figure l(b)), the oxide film 12 on the cap layer 11 is removed not by the (NH4)2S treatment but by another surface cleaning method carried out in the reactor. Thereafter, an etching using a chlorine containing gas is carried out in the same reactor and, successively, the groove formed in the wafer by the gas etching is filled with a compound semiconductor layer by MOCVD.

Although it is described in the first embodiment that the (NH4)2S treatment is an effective technique for cleaning the GaAs cap layer, the surface cleaning process performed in the reactor before the gas etching and the crystal growth also provides a clean regrowth interface. Preferably, the surface cleaning method of this second embodiment is irradiation of ultraviolet light or application of hydrogen plasma that reduces the oxide film.

While in the above-described second embodiment the compound semiconductor including aluminum is AlGaAs and the compound semiconductor grown thereon and including no aluminum is GaAs, the present invention may be applied to crystal growths employing other compound semiconductors.

A description is give of a method for producing a semiconductor device in accordance with a third embodiment of the present invention. In this third embodiment, during the vapor phase etching of the compound semiconductor which

42 - is also carried out in the above-described first and second embodiments, etching conditions are precisely controlled to attain a smooth etching surface. The vapor phase etching of this third embodiment is developed in an experiment described below.

An Al.Gal_,As (x - 0.48) layer 2 pm thick with a GaAs cap layer 0.1 pm thick is employed as a sample. The etching is started from the GaAs cap layer, and the surface of the sample after the etching of about 1 pm is examined with a differential interference microscope.

In this experiment, the flow rate of AsH3 gas to HC1 gas exceeding a prescribed value results in a rough etching surface, and the AsH3 gas flow rate not reaching a prescribed value also results in a rough etching surface. Therefore, when GaAs or AlGaAs is etched with AsH3 gas, H2 gas, and HC1 gas which are introduced into the chamber at the same time, the flow rates of the AsH3 gas and the HC1 gas applied to the wafer surface must be precisely controlled to attain a smooth etching surface. More specifically, in order to etch the AlGaAs layer with a smooth surface, As chloride (for example, AsC13), Ga chloride (GaC13), and Al chloride (AlC13) have to be uniformly evaporated from the surface. However, since the evaporation temperatures of AsC13, GaC13, and AlC13 are different from each other, i.e., 130C, 201C, and 180'C, 43 - respectively, it is difficult to uniformly evaporate these chlorides from the surface. The evaporation of ASC13 from the surface is suppressed by adding a properamount of ASH3, whereby the evaporations of the respective chlorides are balanced. Therefore, it is necessary to optimize the flow rate of AsH3 gas to HC1 gas to attain a smooth etching surface.

Figure 3(a) is a graph illustrating AsH3 flow rate dependence of the dislocation density (EPD) of the GaAs regrown layer when the flow rate of 20 % dilute AsH3 gas is varied under conditions that the etching temperature is 7500C, the etching pressure is 10 Torr, the flow rate of 10 % dilute HC1 gas is 80 sccm, and the total gas flow rate is 2.5 slm. Figure 3(b) is a graph illustrating AsH3 flow rate dependence of oxygen density (10) and chlorine density (ICl) on the etching surface under the same etching conditions as described above. From the result of this experiment, it is found that the optimum etching condition is attained when the AsH3 partial pressure is 0.016 Torr and the flow rate of AsH3 gas to HC1 gas is 0.5. The AsH3 partial pressure is attained by dividing the AsH3 flow rate by the total flow rate and multiplying by the pressure in the reaction chamber. A smooth etching surface is attained when the AsH3 partial pressure is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of AsH3 gas to HC1 gas is below 2.5.

- 44 In addition, this etching method does not adversely affect the etching surface, differently from the conventional RIE, because the etching is carried out only by the chemical reaction.

According to the third embodiment of the present invention, in the vapor phase etching of AIxGai-xAs (0 5 x 1), the gas etching using HC1 gas, AsH3 gas, and H2, which are introduced into the reactor at the same time, is employed, and the gas etching is carried out with the AsH3 partial pressure in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the AsH3 gas to the HC1 gas lower than 2.5. Therefore, a smooth etching surface is attained and the etching surface is prevented from being damaged.

While in the above-described third embodiment the HC1 gas is employed as the etching gas and the AsH3 gas is employed as the group V gas, the etching gas may be C12 gas and the group V gas may be tertiary butyl arsine (C4H9AsH2) or trimethylarsine ((CH3)3As). Since the chemical reaction during the etching process with these gases is the same as described above, the same effects as described above are attained if the etching is carried out with the partial pressure of the group V gas in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas lower than 2.5.

If the etching method of this third embodiment is combined with the surface cleaning method according to the first or second embodiment, the segregation of impurities on the etching surface is suppressed, significantly improving the quality of a crystal layer grown on the etching surface.

A description is give of a method for fabricating a semiconductor laser in accordance with a fourth embodiment of the present invention.

Figures 4(a)-4(c) are sectional views for explaining a relation between the stripe direction of the mask pattern and the etching profile when the etching is carried out under the etching condition according to the abovedescribed third embodiment of the present invention.

In figure 4(a), an AlGaAs layer 2 and a GaAs cap layer 22 are disposed on a (100) surface of a GaAs substrate 23, and a stripe-shaped SiN pattern 21 is disposed on a part of the cap layer 22. Figure 4(b) illustrates an etching profile attained when the wafer is etched down using the stripeshaped SiN pattern 21 extending along the (0111 direction and figure 4(c) illustrates an etching profile attained when the wafer is etched down using the stripeshaped SiN pattern 21 extending along the [011] direction.

With the stripe-shaped mask pattern extending along the (C7111 direction, a ridge structure having two individual tapered planes, i.e., a (011) plane 24 and a (311) plane 25, is formed as shown in figure 4(b). On the other hand, with 46 - the stripe-shaped mask pattern extending along the [0111 direction, a ridge structure having a (111)B plane 26 is formed as shown in figure 4(c). These etching profiles attained by the HCl dry etching are compared to the etching profiles attained by the conventional wet etching in the Table 1 - Table 1 stripe direction <0 11 insulating (1MA (111) A Plane f ilm plane wet:: z, etching (311), (011) plane (111)B plane B plane -HC[ dry 32ZZ2Z etching When the etching method according to the third embodiment of the present invention is employed as the HC1 dry etching, opposite side surfaces of the ridge exposed by the etching are as smooth as a cleavage plane. In addition, no step is formed between the AlGaAs layer 2 and the GaAs cap layer 22 at the side wall of the ridge.

The method for fabricating a semiconductor laser according to the fourth embodiment of the present invention employs the etching method according to the third embodiment of the present invention. More specifically, as described above, the (011) surface 24 perpendicular to the (100) surface is partially exposed on the opposite side walls of the ridge structure when the etching is carried out with the stripe-shaped mask pattern extending along the (C11) direction. In this fourth embodiment, this (011) surface 24 is used as the oscillation facet of the laser.

in the figure,, reference numeral 50 designates an n type GaAs substrate. An n type AlXGal_xAs first cladding layer 51 is disposed on the substrate 50. An active layer 52 is disposed on the first cladding layer 51. A p type AlxGal_xAs second cladding layer 53 is disposed on the active layer 52. An n type GaAs current blocking layer 54 is disposed on the second cladding layer 53. A p type GaAs second cap layer 55 is disposed on the current blocking layer 54. A p type GaAs contact layer 56 is disposed on the cap layer 55. Reference numeral 57 designates a light emitting facet.

- 48 In production, first of all, a buried-ridge type laser structure is fabricated on the (100) GaAs substrate 50 by conventional MOCVD growth and wet etching. Since the process steps for fabricating the laser structure are well known, no detailed description is necessary.

The resonator length direction, i.e., the stripe direction of the ridge, is the [0111 direction. Then, a part of the wafer to be a resonator of the laser is masked with an insulating film, and the wafer is etched by the etching method according to the third embodiment of the present invention. Since the (011) plane perpendicular to the (100) surface of the substrate is formed at the resonator facet 57, the laser oscillation facet is easily formed. Thus formed resonator facet is very smooth and is not adversely affected by the etching process. Therefore, this resonator facet can stand comparison with a resonator facet formed by cleaving.

According to the fourth embodiment of the present invention, after the buried-ridge type laser structure comprising GaAs and AlGaAs layers is fabricated on the (100) surface of the semiconductor substrate, the stripe-shaped etching mask extending along the (0171] direction is formed on the laser structure. Then, the wafer is subjected to the gas etching with HC1 gas, AsH3 gas, and H2 gas which are supplied at the same time under the conditions that the AsH3 - 49 partial pressure is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of the AsH3 gas to the HC1 gas is below 0.25, forming the oscillation facet of the laser. Therefore, the oscillation facet that can stand comparison with the cleavage facet is easily formed by the etching process.

While in the above-described fourth embodiment the buried-ridge type semiconductor laser is employed, the production method of the fourth embodiment may be applied to other laser structures.

While in the above-described fourth embodiment the semiconductor substrate with the (100) surface orientation is employed and the laser facet of the (011) plane is formed, the laser facet may be of a (OF-1) plane. Alternatively, a substrate with a surface orientation that is crystal-technologically equal to the (100) surface may be employed. In this case, a laser facet.is formed with a relation to the surface of the substrate which is equal to the relation between the (011) or (01-1) facet and the (100) surface.

A description is given of a method for fabricating a semiconductor laser in accordance with a fifth embodiment of the present invention.

In this fifth embodiment, a semiconductor laser with an oscillation facet of (111)B plane is fabricated. Figure 5 is a perspective view illustrating a ridge structure formed by the HC1 gas etching using a stripe-shaped mask pattern extending along the (011] direction. As already described above, when the semiconductor layer grown on the (100) surface of the GaAs substrate 23 is etched using the stripeshaped mask extending along the (011] direction, the (111)3 plane 26 is exposed on the opposite side walls of the ridge structure. Since the (111)B plane forms about 54 with respect to the (100) surface, it cannot be employed as an oscillation facet of the laser. However, if a plane perpendicular to the (111)B plane is selected as the surface of the semiconductor substrate, the (111)B plane can be employed as the oscillation facet. For example, the (1710) plane is perpendicular to the (111)B plane as shown in figure 6. Therefore, if a semiconductor substrate with a surface orientation crystal-technologically equal to the (1710) plane is employed, a side surface perpendicular to the surface of the substrate is easily formed using the etching method according to the third embodiment of the present invention.

Although in the above-described fifth embodiment the substrate with (110) surface orientation is employed and the laser facet of (111)B plane is formed, a substrate with (110) surface that is crystal-technologically equal to the (110) surface may be employed. In this case, if the above- 51 described etching is carried out using a stripe-shaped mask extending along the <011> direction, a Clll)B plane perpendicular to the (110) surface and crystaltechnologically equal to the (111)B plane is attained, which (111)B plane can be used as an oscillation facet of the laser.

A description is given of a method for fabricating a semiconductor laser in accordance with a sixth embodiment of the present invention.

In this sixth embodiment, a refractive index guide type semiconductor laser with a window structure is fabricated using the etching method of the third embodiment of the present invention. Figures 8(a)-B(h) and 9(a)9(g) are sectional views illustrating process steps for fabricating the semiconductor laser. The GaAs substrate 50 has a (100) surface orientation.

Figures 8(a)-(h) are sectional views perpendicular to the <C711> direction and figures 9(a)-9(g) are sectional views perpendicular to the <011> direction. In the figures, the same reference numerals as those in figure 7 designate the same or corresponding parts. Reference numeral 70 designates a p type GaAs first cap layer and numeral 71 designates a high resistivity Al y Ga,_yAs window - current blocking layer. Reference numerals 72 and 73 designate a p side electrode and an n side electrode, respectively.

Initially, the first cladding layer 51, the active layer 52, the second cladding layer 53, and the p type GaAs first cap layer 70 are successively grown on the (100) GaAs substrate 50 by MOCVD (figures B(a) and 9(a)). Then, the stripe-shaped SiN film 21 is formed on a part of the wafer along the [011] direction, i.e., the resonator length direction (figures B(b) and 9(b)). Using the SiN film 21 as a mask, the wafer is etched under the etching conditions according to the third embodiment of the present invention (figures 8(c) and 9(c)). As shown in figure B(c), the etching is carried out forming a (011) plane to be a resonator facet perpendicular to the (100) surface of the substrate. It is to be desired that the surface cleaning according to the first or second embodiment of the present invention is performed before the etching process. After the etching process, the high resistivity Al y Gai-YAs window - current blocking layer 71 having an energy band gap larger than that of the active layer is grown in the same reaction chamber by conventional MOCVD (figures 8(d) and 9(d)). Figure 10(a) is a perspective view illustrating the wafer just after the MOCVD growth. If the etching and the regrowth are carried out in the same chamber using the method according to the first or second embodiment of the present invention, a favorable regrowth is achieved with no segregation of impurities at the interface between the window layer 71 and the resonatorfacet (figure 8(d)). After removing the Sin film 21 (figures 8(e) and 9(e)), the p type GaAs contact layer 56 is grown on the wafer (figures B(f) and 9(f)). Then, the p side electrode 72 and the n side electrode 73 are formed on the contact layer 56 and on the rear surface of the substrate 50, respectively (figures 8(g) and 9(g)). In this way, a fundamental structure of the refractive index guide type semiconductor laser with the window structure is fabricated in the wafer. Finally, the wafer is divided into chips by cleaving or the like (figure 8(h)).

Figure 10(b) is a perspective view of thus fabricated refractive index guide type semiconductor layer with the window structure. In the figure, the p side and n side electrodes are omitted.

The prior art method for fabricating the semiconductor laser with the window structure provides very poor massproducibility because the window layer is grown on the oscillation facet formed by cleaving. According to the sixth embodiment of the present invention, the semiconductor laser with the window structure is fabricated in a relatively simple process compared to the conventional process. In addition, since the flatness and the cleanliness of the regrowth interface are improved, a highquality refractive index guide type semiconductor laser with

54 window structure is achieved.

While in the above-described sixth embodiment the semiconductor substrate with the (100) surface orientation is employed and the laser facet of the (011) plane is formed, the laser facet may be of a (OH) plane. Alternatively, a substrate with a surface orientation that is crystaltechnologically equal to the (100) surface may be employed. In this case, a laser facet is formed with a relation to the surface of the substrate which is equal to the relation between the (011) or (01-1) facet and the (100) surface.

A description is given of a method for fabricating a semiconductor laser in accordance with a seventh embodiment of the present invention. In this seventh embodiment, the etching method according to the third embodiment of the present invention is applied to the formation of a ridge structure in a method for fabricating a ridge waveguide type semiconductor laser. Figures 11(a)-11(d) are sectional views illustrating process steps in a method for fabricating the ridge waveguide type semiconductor laser. In the figures, the same reference numerals as those in figure 7 designate the same or corresponding parts.

Initially, the n type AIXGal_xAs first cladding layer 51, the active layer 52, the p type A1xGa,_xAs second cladding layer 53, and the p type GaAs first cap layer 70 are successively grown on the n type GaAs Substrate 50 by MOCVD. Then, the stripe-shaped SiN film 21 is formed on a part of the cap layer 70 (figure 11(a)). Using the SiN film 21 as a mask, the wafer is etched down by the etching method described in the third embodiment, forming a ridge structure as shown in figure 11(b). If the stripe of the SiN pattern 21 is in the [011] direction, (111)B planes are exposed on opposite side walls of the ridge. It is to be desired.that the surface cleaning according to the first or second embodiment of the present invention is performed before the etching process. Then, as illustrated in figure 11(c), the n type GaAs current blocking layer 54 and the p type GaAs second cap layer 55 are grown on the second cladding layer 53 contacting the side walls of the ridge in the same reaction chamber by.MOCVD. After removing the SiN film 21, the p type GaAs contact layer 56 is grown by MOCVD as shown in figure 11(d).

To complete the ridge waveguide type semiconductor laser shown in figure 12, p side and n side electrodes 72 and 73 are deposited and the wafer is divided into chips by cleaving or the like.

In this seventh embodiment of the present invention, since the formation of the ridge structure using the gas phase etching method according to the third embodiment of the present invention is combined with the MOCVD selective growth, the complicated process steps, such as wet etching for forming the ridge structure, can be dispensed with, whereby the production process is significantly simplified. If the surface cleaning process according to the first or second embodiment of the present invention is performed before the gas phase etching, an improved regrowth interface is attained, increasing the lift time of the high power semiconductor laser.

Although the ridge structure of the semiconductor laser formed using the HC1 gas etching is also disclosed in Japanese Published Patent Application No. 60-163487, this prior art does not describe the etching conditions. The HC1 gas etching for forming the ridge structure is put to practical use for the first time when the etching conditions described in the third embodiment of the present invention are employed.

A description is given of a method for producing a semiconductor device in accordance with an eighth embodiment of the present invention. Figure 13 illustrates a gas introduction sequence employed in a compound semiconductor etching method according to the eighth embodiment of the present invention. In the figure, reference numeral 120 designates an AsH3 gas supply region, numeral 121 designates an H2 purge region, and numeral 122 designates an HC1 gas supply region.

57 - which ASH3 gas HU gas are supplied so that the supply time of the HU gas is shorter than that of the AsH3 gas and a second etching step in which the supply of the AsH3 gas and the HU gas is halted and the inside of the reactor is purged with hydrogen gas. The first etching step and the second etching step are alternatingly repeated, realizing an one-atomic layer level etching.

A description is given of the principle of the compound semiconductor etching method. As already described in the third embodiment of the present invention, in order to attain a flat etching surface when GaAs is etched by HU gas, the flow rate of AsH3 gas must be precisely controlled. The proper amount of AsH3 gas reduces the escape of AsC13 from the GaAs surface, and a flat etching surface is achieved when the escape of AsC13 and the escape of GaC13 are well-balanced. According to our experiment, the etching rate of GaAs decreases with an increase in the AsH3 flow rate. This is because the excessively supplied AsH3 suppresses the escape of AsC13. Therefore, if the HC1 gas is supplied like a pulse while excessively supplying AsH3, only GaC13 escapes from the GaAs surface, realizing the oneatomic layer level etching. At this time, AsC13 is prevented from escaping from the GaAs surface due to the excessive AsH3 and remains on the surface. When the supply of AsH3 gas is stopped, AsC13 escapes from the GaAs surface.

of AsH3 gas Is stopped, AsC13 escapes from the GaAs surface.

Figure 14 is a graph illustrating a relation between the etching rate and the HC1 gas supply pulse time in the above-described etching method. As shown in the graph, an etching rate of 1 ML/cycle is attained at a specific HC1 pulse time. In this embodiment, the HCI pulse time is 0.75 1.5 sec.. The HC1 pulse time is not restricted thereto because it varies according to the HC1 supply rate.

According to the eighth embodiment of the present invention, the etching controlled at the one-atomic layer level is easily performed. In addition, one cycle of the etching process takes only 4 - 8 seconds, significantly reducing the etching time.

A description is given of an apparatus and a method for producing a semiconductor device in accordance with a ninth embodiment of the present invention. Figure 15 is a schematic diagram illustrating an apparatus for etching a compound semiconductor according to the ninth embodiment of the present invention and figure 16 is a plane view thereof. In the figures, reference numeral 140 designates source gas injectors, numeral 141 designates carrier gas injectors, numeral 142 designates H2 gas injectors, numeral 143 designates a wafer tray, numeral 144 designates a wafer, numeral 145 designates a reaction chamber, numeral 146 designates a susceptor, and numeral 147 designates an exhaust port.

A plurality of H2 gas injectors 142 are disposed above the susceptor 146. The H2 gas emitted from the injectors 142 forms hydrogen curtains 155, whereby the susceptor 146 is divided into four regions 151, 152, 153, and 154. A plurality of source gas injectors 140 are disposed so that source gas or etching gas is applied to the respective regions individually. Since the susceptor 146 has a rotating mechanism, the wafer 144 on the susceptor is successively moved through the regions 151 to 154.

The etching method will be described. In figure 16, AsH3 gas, HU gas, and H2 gas are supplied to the regions 151 and 153 at the same time while only H2 gas is supplied to the regions 152 and 154. As described in the eighth embodiment of the present invention, under the excessive supply of AsH3 gas, only GaC113 escape8 from the GaAs surface and the escape of AsC13 is suppressed. That is, when the wafer 144 is present in the region 151 or 153, only Ga atoms escape from the surface. When the wafer 144 is present in the region 152 or 154, only As atoms escape from the surface. In this way, the one-atomic layer level etching is performed. Since the wafer 144 is moved through the regions 151 to 154 by the rotation of the susceptor 146, the time required for one cycle of the etching process is significantly reduced compared to the conventional etching - method.

A description is given of a method for fabricating a quantum wire structure in accordance with a tenth embodiment of the present invention. Figures 17 and 18 are sectional views illustrating AlGaAs layers and GaAs layers alternatingly grown on a GaAs substrate 23 with a stripeshaped V groove. The GaAs substrate 23 has a (100) surface orientation. In figure 17, the stripe-shaped V groove-is formed along the (0111 direction by the etching method according to the third embodiment of the present invention. In figure 18, the stripe-shaped V groove is formed along the [b-11] direction by a wet etching using a sulfuric acid base solution as an etchant.

As shown in figure 17, when the stripe-shaped V groove is formed along the.[0111 direction, the (111)B planes are exposed on the opposite side surfaces of the groove. Since typical MOCVD growth does not proceeds perpendicularly to the (111)B planes, the growth proceeds forming side surfaces 162 on which no crystal is grown. The crystal growth in the V groove proceeds discontinuously with the crystal growth on the flat surface of the substrate 23. That is, the growth proceeds with a front surface 163 that forms a smaller angle with respect to the (100) surface of the substrate than the angle formed between the (111)B plane and the (100) surface. The orientation of the growth front surface 163 is identified a (311)B plane from the angle.

On the other hand, when the stripe-shaped V groove is formed along the CC7111 direction, the (111)A planes are exposed on the opposite side surfaces of the V groove. Since the growth rate on the (111)A plane is approximately equal to the growth rate on the (100) surface, the growth proceeds uniformly on the surface of the groove and on the flat surface of the substrate 23 as shown in figure 18. This crystal growth does not provide a desired quantum wire structure. Further, it is difficult to form the V groove with the (111)B side surfaces shown in figure 17 by conventional wet etching.

Figures 20(a)-20(d) are sectional views illustrating process steps in a method for fabricating a quantum wire structure according to the tenth embodiment of the present invention, and figure 19 is a sectional view illustrating the quantum wire structure. In the figures, reference numerals 181 and 183 designate AlGaAs layers, numeral 182 designates a GaAs quantum wire, numeral 184 designates a GaAs second cap layer, numeral 185 designates a GaAs first cap layer, and numeral 186 designates an SiN film.

Initially, the AlGaAs layer 181 and the GaAs first cap layer 185 are successively grown on the GaAs substrate 180 by MOCVD (figure 20(a)). Then, an SiN film lB6 is deposited on the first cap layer 185 and patterned to form a stripe- 62 - shaped aperture extending along the (011] direction (figure 20(b)). Using the SiN pattern 186 as a mask, a stripeshaped.V groove with the side surfaces of the (111)B planes is formed by the etching method according to the third embodiment of the present invention (figure 20(c)). Subsequently, in the same reaction chamber, the GaAs quantum wire 182, the AlGaAs layer 183, and the GaAs second cap layer 184 are selectively grown in the V groove (figure 20(d)). The growth of the GaAs quantum wire 182 should be controlled so that the width is in a range from 20 nm to 30 nm, whereby a desired quantum effect is attained. Since the crystal growth proceeds as shown in figure 17 in the V groove with the side surfaces of the (111)B planes, the GaAs quantum wire structure shown in figure 19 is easily formed.

Although in the above-described tenth embodiment the semiconductor substrate with the (100) surface orientation is employed and the stripeshaped V grQove with the side surfaces of the (111)B planes are formed, a semiconductor substrate with a (100) surface orientation that is crystaltechnologically equal to the (100) surface may be employed. In this case, if the same etching process as described above is performed using a mask pattern with a stripe-shaped opening extending along the <011> direction, a stripe-shaped V groove having side surfaces of Clll)B planes that are crystal-technologically equal to the (111)B planes is attained. When this groove is filled with the crystal layers, the same effects as described above are attained.

Figure 21 is a cross-sectional view illustrating a quantum wire structure fabricated by a method according to an eleventh embodiment of the present invention. One of the inventors of the present invention discloses a quantum wire structure and a production method thereof in Japanese Published Patent Application No. 2-335827. This eleventh embodiment of the present invention offers an improved method for fabricating a quantum wire that is structurally the same as that disclosed in the prior application No. 2335827., whereby a high-quality quantum wire structure is attained. In figure 21, reference numeral 190 designates a semi- insulating GaAs substrate. A high-resistivity intrinsic (hereinafter referred to as i type) GaAs layer 191 is disposed on the GaAs substrate 190. An n type AlGaAs spacer layer 192 is disposed on the GaAs layer 191. An n+ type GaAs cap layer 193 is disposed on the AlGaAs spacer layer 192. A quantum wire 194 is buried in the i type GaAs layer 191. An SiN film 195 is disposed on the GaAs cap layer 193. An n type AlGaAs electron supply layer 197 is buried in the GaAs cap layer 193 and the AlGaAs spacer layer 192. An n+ type GaAs cap layer 196 is disposed on the AlGaAs electron supply layer 197.

Figures 22(a)-22(e) are sectional views illustrating a method for fabricating a plurality of quantum wire structures shown in figure 21 on the same substrate. In the figures, the same reference numerals as those in figure 21 designate the same or corresponding parts.

Initially, the i type GaAs layer 191, the i type AlGaAs spacer layer 192, and the n+ type GaAs cap layer 193 are successively grown on the semi-insulating GaAs substrate 190 with a (100) surface orientation by MOCVD. Then, the SiN film 195 is deposited on the n+ type GaAs cap layer 193 and patterned to form a plurality of stripe-shaped openings parallel to each other (figure 22(a)). Each stripe-shaped opening extends along the (011] direction. Using the etching method according to the third embodiment of the present invention, the wafer is selectively etched from portions exposed in the openings of the SiN film 195, forming a plurality of stripe-shaped V grooves (figure 227(b)). Subsequently, in the same reac. tion chamber, the n type AlGaAs electron supply layer 197 and the n+ type GaAs cap layer 196 are selectively grown in the V grooves (figure 22(c)). It is to be desired that the surface cleaning according to the first or second embodiment of the present invention is performed before the etching process. After removing the SiN film 195 (figure 22(d)), the n+ type GaAs cap layer 196 is deposited on the entire surface of the wafer (figure 22(e)).

In this production method, the quantum wire 194 is formed in a very narrow region of the i type GaAs layer 191 opposite the bottom of the V groove. The reason why the quantum wire 194 is formed is described in detail in the prior application No. 2-335827.

According to the eleventh embodiment of the present invention, the quantum wire structure is formed with high precision. In addition, if the surface cleaning according to the first or second embodiment of the present invention is performed before the etching process for forming the V grooves, a high-quality quantum wire structure with no impurity segregation on the regrowth interface is achieved.

While in the above-described eleventh embodiment the cap layer 193 comprises n+ type GaAs, it may comprise i typ GaAs.

Figures 23(a)-23(c) are sectional views illustrating process steps in a method for fabricating a semiconductor laser according to a twelfth embodiment of the present invention.

Initially, there are successively grown on an n type GaAs' substrate 200 by MOCVD an n type GaAs buffer layer 201, an n type AlGaAs cladding layer 202, an undoped GaAs active layer 203, a p type AlGaAs cladding layer 204, an n type GaAs current blocking layer 205, and a p type GaAs contact layer 206. Then, an SiO film 207 is deposited on the entire 66 - surface of the contact layer 206 by sputtering and patterned using conventional photolithography to form a stripe-shaped opening along the (011) direction (figure 23(a)). Figure 24 is a perspective view of the wafer in the step of figure 23(a).

Using the SiO film pattern 207 as a mask, portions of the p type GaAs contact layer 206 and the n type GaAs current blocking layer 205 are selectively etched away, forming a stripe-shaped groove with side walls of (111)B planes (figure 23(b)). These layers 206 and 205 are etched by HC1 gas in the MOCVD reactor. The etching conditions according to the third embodiment of the present invention may be employed for the HC1 gas etching. In addition, it is to be desired that the surface cleaning according to the first or second embodiment of the present invention is performed before the etching process.

Then, a p type AlGaAs cladding layer 208 and a p type GaAs contact layer 209-are successively grown in the groove by MOCVD (figure 23(c)). Since the MOCVD growth does not proceed on the (111)B surfaces, the groove is filled with the crystal layers grown from the bottom of the groove as shown in figure 25, resulting in a flat surface of the wafer (figure 23(c)).

To complete the semiconductor laser, p side and n side electrodes are formed and the wafer is divided into chips by cleaving.

According to the twelfth embodiment of the present invention, the wafer is etched by the HC1 gas etching using the mask pattern with the stripeshaped opening extending along the [011) direction that is different from the conventional one by 900, forming the stripe-shaped groove that provides a current path. Therefore, the crystal growth in the groove proceeds with a flat surface, resulting in a flat surface of the wafer that facilitates the subsequent photolithographic process. In addition, when the laser device is fabricated by junction-down bonding, a compressive stress applied to the active layer is reduced, improving the reliability of the laser device.

In the prior art process steps shown in figures 36(a)36(e)j the p type AlGaAs layer 307 and the p type GaAs contact layer 308 are grown in different crystal growth steps and, therefore, three crystal growth steps are required in the production process. On the other hand, in this twelfth embodiment of the present invention, since the growth of the crystal layer in the groove proceeds parallel to the bottom surface of the groove, even if the p type AlGaAs layer 208 and the p type GaAs contact layer 209 are successively grown in a crystal growth step, the p type GaAs contact layer 209 is grown contacting the p type GaAs contact layer 206. That is, only two crystal growth steps - 68 are required, significantly reducing the production process.

The growths of the p type AlGaAs layer 208 and the p type GaAs contact layer 209 may be separately carried out. That is, after filling the groove with the p type AlGaAs layer 208 and removing the mask pattern 207, the p type GaAs contact layer 209 is grown on the entire surface of the wafer. In this case, the layers 201, 202, 203, 204, and 205 are successively grown on the substrate in the first crystal growth step.

Although in the above-described twelfth embodiment the semiconductor substrate with the (100) surface orientation is employed and the stripeshaped V groove with the side surfaces of the (111)B planes are formed, a semiconductor substrate with a (100) surface orientation that is crystaltechnologically equal to the (100) surface may be employed. In this case, if the same etching process as described above is performed using a mask pattern with a stripe-shaped opening extending along the <011> direction, a stripe-shaped V groove having side surfaces of (111)B planes that are crystal-technologically equal to the (111)B planes is attained. When this groove is filled with the crystal layers, the same effects as described above are attained.

A description is given of a method for fabricating a semiconductor laser in accordance with a thirteenth embodiment of the present invention. In this embodiment, a highly-reliable buried heterojunction semiconductor laser is achieved using AlGaAs. The process steps of this method are illustrated in figures 26(a)-26(e).

Initially, an n type AlGaAs cladding layer 211, an undoped GaAs active layer 212, and a p type AlGaAs cladding layer 213 are successively grown an n type GaAs substrate 210 by MOCVD. A p type GaAs cap layer is grown on the p type AlGaAs cladding layer 213 although it is not shown. Then, an S102 film is deposited on the entire surface of the wafer by sputtering and patterned by conventional photolithography, forming a strips-shaped S102 pattern 214 along the (011] direction (figure 26(a)). Then, the double heterojunction structure is selectively etched using the S102 pattern 214 as a mask, forming a ridge structure as shown in figure 26(b). Preferably, this etching is carried out in the MOCVD reactor using HC1 gas. The ridge structure has opposite side walls of (111)B planes. Before the etching process, the surface cleaning according to the first or second embodiment of the present invention is carried out. In addition, the etching conditions according to the third embodiment of the present invention is employed for the gas etching. After the etching process, an i type GaAs current blocking layer 215 is grown on the substrate 210 contacting the side walls of the ridge structure by MOCVD (figure 26(c)).Thereafter, the Si02 pattern 214 is removed and a P type GaAs contact layer 216 is grown on the entire surface of the wafer (figure 26(d)).

To complete the semiconductor laser, a p side electrode and an n side electrode are formed on the contact layer 216 and on the rear surface of the substrate 210, respectively, and the wafer is divided into chips by cleaving.

When the buried-heterojunction semiconductor laser is fabricated using AlGaAs material, surface states are easily formed on the regrowth interface, and the active layer in the vicinity of the regrowth interface is adversely affected by the surface states, reducing the reliability of the laser. In this thirteenth embodiment of the present invention, however, since the surface cleaning according to the first or second embodiment of the present invention is performed before the etching process, a clean regrowth interface, on which the surface states are not easily formed, is attained, resulting in a highly-reliable AlGaAs buried heterojunction semiconductor laser.

While in the above-described thirteenth embodiment the current blocking layer 215 comprises the high resistivity GaAs layer, it may be of a double-layer structure comprising a p type GaAs layer 217 and an n type GaAs layer 218 as shown in figure 26(e). In this case, a p-n-p-n thyrister current blocking structure is achieved.

A description is given of a fourteenth embodiment of the present invention. Figures 27(a)-27(d) are sectional views illustrating a crystal growth method in accordance with the fourteenth embodiment of the present invention.

Initially, an Si substrate 401 is prepared (figure 27(a)), and a silicon nitride (SiN) film 402 is grown thereon by plasma CVD.

Then, as illustrated in figure 27(c), the SiN film 402 is patterned leaving portions surrounding a region on which a device is to be formed (hereinafter referred to as a device region). Then, the Si substrate 401 is rinsed with a mixture of ammonia water, H202, and H20 (hereinafter referred to as RCA solution). When the Si substrate is rinsed with the RCA solution, contaminations of photoresist and the like remaining on the surface are completely removed and, thereafter, an oxide film of little bonding strength to the clean surface of the Si substrate is formed on the Si substrate. The oxide film is easily removed by annealing the wafer in the MOCVD reactor before the crystal growth.

After the annealing, a GaAs layer 403 having a desired thickness is formed by two-stage growth method (figure 27(d)). More specifically, first of all, a low temperature buffer layer is grown while supplying HC1 gas together with the source gases, i.e., AsH3 gas and trimethylgallium (TMG) (first growth stage). The molar flow rate of HC1 gas to TMG is 0.25. In conventional MOCVD growth, polycrystal is deposited on the insulating film at a low temperature below 500C, resulting in poor selective growth. In this embodiment of the present invention, however, since the small amount of HC1 gas is added during the MOCVD growth, the deposition of polycrystal is completely prevented, resulting in a favorable selective growth. Therefore, when the GaAs layer is grown to a desired thickness at about 7000C after the growth of the low temperature buffer layer, no polycrystal is deposited on the insulating film, and the GaAs layer is selectively grown on the device region.

In the conventional crystal growth method, since the selective growth of the low temperature buffer layer is not favorably carried out, cracks are produced in the buffer layer. In order to avoid this problem, the grooves are formed surrounding the device region to prevent the cracks produced at the edge of the wafer from reaching the device region. In this case, however, since the photoresist used for patterning the grooves is not completely removed from the wafer surface before the subsequent crystal growth process, the rhombic pit is formed due to the remaining photoresist during the high temperature growth process, resulting in cracks produced from the rhombic pit.

According to the fourteenth embodiment of the present invention, after the patterning of the insulating film 402, the Si substrate is rinsed with the RCA solution and then - 73 the GaAs layer is grown by the two-stage growth method. Therefore, a favorable selective growth is performed. The cracks generated from the edge of the wafer are completely stopped by the insulating film, so that no crack is introduced into the device region. In addition, since the GaAs layer is grown on the clean surface of the Si substrate, no rhombic pit is produced.

While in the above-described fourteenth embodiment the GaAs layer is grown on the Si substrate, the same effects as described above are attained when an InP layer is grown an an Si substrate or a GaAs substrate. When the GaAs substrate is employed, it is difficult to sufficiently clean the surface after the formation of the insulating pattern. In the method according to the fourteenth embodiment, however, since the low temperature buffer layer is grown first on the surface of the GaAs substrate differently from the prior art method where the high temperature growth is directly carried out on the GaAs substrate on which the photoresist remains, the rhombic pit caused by the impurities on the substrate is not easily produced and the cracks are sufficiently prevented.

The crystal growth method according to this fourteenth embodiment may be applied to crystal growths on different kind substrates other than mentioned above with the same effects as described above.

- 74 Figure 28 is a graph for explaining a crystal growth method in accordance with a fifteenth embodiment of the present invention. This graph illustrates HC1 flow rate dependence of crystal growth rate when GaAs is grown on a GaAs substrate by MOCVD- When the HC1 flow rate is below 3 sccm, the growth rate is not varied. After the HC1 flow rate exceeds 5 sccm, the growth rate decreases with the increasing HC1 flow rate. This is due to that the etching by the HC1 gas is synchronized with the crystal growth by the source gas. In order to improve the selective growth alone without reducing the uniformity and reproducibility of the MOCVD, it is very important to maintain the HC1 flow rate under a prescribed value. That is, the HC1 flow rate must be set so that the molar flow rate of the HC1 gas to the TMG is lower than 0. 3.

Figure 29 is a graph for explaining the quality of the grown crystal layer affected by the HC1 gas supplied with the source gas during the MOCVD growth. The graph illustrates 4.2 K photoluminescence (PL) spectrums 410 and 411 of AlO.37GaO.63As layers grown on the GaAs substrate. The PL spectrum 410 is attained with the molar flow rate of the HC1 gas to the group III gas (hereinafter referred to as [HC1]/CIIII rate) of 0.25 and the PL spectrum 411 is attained with the [HC1]/CIII] rate of 1.0. When the [HC1]/(IIII rate is 0.25, the PL spectrum 410 shows a good crystallinity equivalent to the crystallinity obtained by ordinary MOCVD growth. Howeverr in the sample grown with the [HC1]/[III] rate of 1.0, the peak intensity of the PL spectrum 411 is reduced to about 1/100 and a peak of light emission due to impurities dominates the peak of the PL spectrum. When the impurity distribution of this sample is observed by SIMS technique, it is found that Cl and 0 are mixed into the crystal. This result shows that the large amount of HC1 gas added during the crystal growth adversely affects the quality of the grown layer.

From the results of the experiment shown in figures 28 and 29, it is discovered for the first time that maintaining the [HC11/(IIII rate lower than 0.3 is very important with respect to the quality, uniformity, and reproducibility of the grown crystal layer.

In a crystal growth on a different kind substrate, such as GaAs on Si, especially when a low temperature buffer layer, is grown while supplying the HC1 gas together with the source gases, the CHC1]/[III] rate below 0. 3 provides a favorable selective growth with an improved quality of the grown layer and no crack.

While in the above-described fourteenth and fifteenth embodiments of the present invention the HC1 gas is supplied at the same time as the source gas, a C12 gas may be supplied in place of the HC1 gas. Also in this case, the same effects as described above are attained.

77

Claims

A method for producing a quantum wire structure comprising:

forming a first semiconductor layer semiconductor substrate with a (lQO) surface orientation; forming an etching mask on said first semiconductor layer,, said etching mask having a stripe-shaped opening extending along a <011> direction; etching said first semiconductor layer by a gas etching using an etching gas selected from HCl gas and C12 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3AS) gas, and a hydrogen gas, which are introduced into a reactor at the same time, under conditions that the partial pressure of said group V gas is in a range from 8 x 10-3 Torr to 0.08 Torr and the flow rate of said group V gas to said etching gas is lower than 2.5, thereby forming a stripe-shaped V groove with side surfaces of (111)B planes; forming a second semiconductor layer having an energy band gap smaller than that of said first semiconductor layer in the vicinity of the bottom of on a 78 said V groove; and forming a third semiconductor layer having an energy band gap larger than that of said second semiconductor layer on said second semiconductor layer.
2. A method for producing quantum wire structures comprising:

growing a first high-resistivity layer comprising a first semiconductor on a semiconductor substratet successively growing a second high-resistivity layer comprising a second semiconductor and having an electron affinity smaller than that of said first semiconductor and a third high-resistivity layer comprising said first semiconductor; forming alternating projections and recesses in said second high resistivity layer so that the cross section of each recess is an inverted triangle, by a gas etching using an etching gas selected from HCl gas and C12 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9ASH2) gas, and trimethylarsine HCH3)3As) gas, and a hydrogen gas, which are introduced into a reactor at the same time, under conditions that the partial pressure of said group V gas is in a range from 8 x 10-3 Torr to 0.08 79 Torr and the flow rate of said group V gas to said etching gas is lower than 2.5; and successively growing a first n type layer comprising said second compound semiconductor and a second n type layer comprising said first compound semiconductor.