JP3470086B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device.
Related to the law, and in particular combined process which combines dry etching and epitaxial growth.

[0002]

2. Description of the Related Art In recent years, in the manufacturing process of semiconductor laser diodes and quantum wire structures, development of a fine structure manufacturing technique that combines etching and regrowth has been active. This is a technique for realizing a desired electronic state by selectively etching a part of a crystal and growing an epitaxial layer electrically and optically different from the surrounding crystal there. In such a process, the development of a technique for controlling the cleanliness of a regrowth interface as well as a technique for forming a desired shape with high controllability has attracted attention as an important issue. Especially with respect to AlGaAs, since Al is a material that is very easily oxidized, the oxide film formed on the surface prevents the desired shape from being obtained, or the regrown interface is contaminated. Problems such as a marked deterioration in crystal quality have arisen, which is an important issue to be solved in device application.

For example, Japanese Patent Publication No. 3-59576 discloses a conventional Al.
The following method is disclosed as an example of the GaAs etching method. That is, when AlGaAs is etched using the reactive dry etching method,
To eliminate the surface oxidation of Al
By forming an aAs protective layer in advance, AlGaAs
It is a method that can prevent the formation of an oxide film on the surface. Reactive dry etching was performed on GaAs
It is reported that good etching of AlGaAs can be achieved only by starting from the protective layer. In addition, AlGaA
When s is gas-etched using HCl gas, Ga
The description that good etching is possible by using the As cap layer is described in JP-A-61-1
It is also made in Japanese Patent No. 84892.

FIG. 34 is a diagram for explaining a vapor phase etching method for a compound semiconductor which is a second conventional example disclosed in Japanese Patent Publication No. 3-55439. In the figure, 2
41 is a reaction tube, 242 is a substrate holder, 243 is a semiconductor substrate, 244 is a resistance heating means, 245 is a bypass pipe,
246 indicates a low temperature region, 247 indicates a high temperature region, and 248 indicates an etching gas introduction port.

In this etching method, the semiconductor substrate 243 is held in the low temperature region 246, where HCl is added to the semiconductor substrate 2
In this method, the semiconductor substrate 243 is moved to the high temperature region 247 after being sufficiently adsorbed on the surface of the substrate 43, held for a certain period of time, and then moved to the low temperature region 246 again as one cycle. According to this method, a temperature of 400
In the low temperature region 246 of about 0 ° C., even if HCl gas is supplied, etching does not occur, and only Cl is adsorbed on the substrate surface. Then, when the semiconductor substrate is moved to a high temperature region 247 of 600 ° C. or higher, Cl adsorbed is GaC.
Since it is desorbed from the semiconductor surface as l ₃ and etching is performed in units of one molecular layer, etching can be performed with good controllability.

FIG. 35 shows, for example, Applied Physics Letters, 55 (1989), pp2715-271, 55, pp. 2715-2717, 1989.
FIG. 7 is a sectional structural view showing a structure of a quantum wire laser which is a third conventional example disclosed in 7). In the figure, 250 is n
⁺ -GaAs substrate, 251 _{n-Al y Ga 1-y} As first cladding layer, 252 is Al _x Ga _1-x As barrier layer,
253 is a GaAs quantum well layer, 254 is Al _x Ga _1-x
As barrier layer, 255 _{p-Al y Ga 1-y} As second cladding layer 256 is p ⁺ -GaAs cap layer 257
Is a Ti / Au electrode, and 258 is a high resistance region by ion implantation. Reference numeral 259 indicates an active region in which quantum wires are formed.

Semiconductor laser according to the third conventional example
Is an n with a V-shaped groove formed⁺-On GaAs substrate 250
N-Al_y Ga_1-y As first cladding layer 251, Al
_x Ga _1-x  As barrier layers 252 and 254 and GaAs
Active layer composed of a metal layer 253, p-Al_y Ga_1-y As
Second cladding layer 255, and P⁺-GaAs cap layer
It is formed by sequentially stacking 256, and p-Al_y Ga
_1-y A part of the As second cladding layer 255 is formed by ion implantation.
Therefore, the current confinement layer 258 is formed by increasing the resistance.

Here, the active layer has a quantum well structure on a normal plane substrate, but a quantum wire structure is formed near the bottom of the V-shaped groove for the following reason.

In the figure, the semiconductor main surface is the (100) surface, and the V-shaped groove is formed in the [0/11] direction by the usual photolithography process and wet etching technique. Therefore, the side surface of the V-shaped groove is the (111) A surface. Under typical MOCVD growth conditions, the growth rate on the (100) plane is almost equal to the growth rate on the (111) A plane, so that the layers grow parallel to each other along the V-shaped groove as shown in FIG. Take the form of growth. At this time, the tip of the V-shaped bottom is slightly rounded, so it is partially (100)
The surface is exposed, and in a very narrow region of the tip of the V-shaped bottom, the film grows in the direction perpendicular to the (100) plane, and the film thickness becomes thicker than that of the V-shaped side surface. In this way, the GaAs quantum well layer forms a crescent-shaped quantum wire 259 at the V-shaped bottom.

FIG. 33 shows, for example, Japanese Journal of Applied Physics, 1991, volume 30, L9.
Pages 04-906 (Japanese Journal of Applied
FIG. 9 is a perspective view showing an example of a structure of a high-power laser having a window structure on a laser oscillation end face which is a fourth conventional example disclosed in Physics, Vol.30, (1991), pp.L904-L906). In the figure, 231 is a p-GaAs substrate, 232 is n-Ga.
As current blocking layer, 233 is p-Al _0.33 Ga _0.67 A
s clad layer, 244 is a p-Al _0.08 Ga _0.92 As active layer, 235 is an n-Al _0.33 Ga _0.67 As clad layer, 2
36 is an n-GaAs contact layer. Further, 237 is a (110) end face formed by cleavage, and 238 is an undoped Al _0.4 Ga _0.6 As formed on the cleaved end face 237.
It is a window layer.

Next, the window structure adopted in the conventional high-power laser will be described. In the AlGaAs-based high-power laser, many surface levels are formed at the oscillation end face of the laser. Due to the influence of this surface level, the band gap is equivalently reduced in the vicinity of the end face as compared with the central part of the laser. Therefore, for the wavelength of the laser light, the region near the end face becomes an absorption region, and the local heat generation in the absorption region increases as the light output increases. Since the band gap shrinks as the temperature rises, the absorption of laser light further increases, and positive feedback that causes a temperature rise is applied, which eventually leads to melt fracture. This phenomenon is called optical damage and is a serious problem in AlGaAs high-power lasers. The window structure is provided for the purpose of reducing the optical absorption near the end face and preventing the above optical damage by providing a region having a band gap larger than the oscillation wavelength of the laser in the region near the laser oscillation end face.

In the above conventional high power laser, the window structure is
The following steps are performed in forming the structure. Well
Without combining normal wet etching and LPE growth
To produce a laser structure. That is, the p-GaAs substrate 23
Crystal growth of the n-GaAs current blocking layer 232 on
After passing through the current block layer 232 in the central part of the device,
A stripe-shaped V groove reaching 231 is formed. this
Then, p-Al on the wafer _0.33Ga_0.67As clad layer 2
33, p-Al_0.08Ga_0.92As active layer 244, nA
l_0.33Ga_0.67As clad layer 235, and n-GaA
The s contact layer 236 is sequentially crystal-grown. Next wafer
After polishing to a desired thickness,
Cleave into bars. Cavity length for typical high power lasers
Is 300 to 600 μm. Next, the cleaved wafer
The energy bar of the lasing laser light is
A material with a large air gap is grown by MOCVD.
It

In this conventional example, the laser oscillation wavelength is 830.
Since it is nm and is about 1.49 eV in terms of energy, an undoped Al _0.4 Ga _0.6 As layer 238 having a band gap of about 1.93 eV is used as the window layer. Next, electrodes are formed, and finally the end face of the window layer is coated, and then the chips are separated to complete a laser chip. The Japanese Journal of Applied Physics, 1991, Volume 30, L904-L90
It is reported on page 6 that by adopting a window structure, optical damage was suppressed and high output and long life could be achieved.

Further, FIG. 36 shows IEEE Journal of Quantum Electronics, 1987, 23, 72.
Page 0 (IEEE J. of Quantum Elections Vol.23 (198
7), p. 720) are sectional process drawings showing a method of manufacturing a semiconductor laser which is a fifth conventional example, using the method shown in FIG. In the figure, 300 is an n-GaAs substrate, 301 is an n-GaAs buffer layer, 302 is an n-AlGaAs cladding layer, 303 is an undoped GaAs active layer, 304
Is a p-AlGaAs cladding layer, 305 is n-GaAs
Current block layer, 306 is SiO ₂ film, 307 is p-A
The 1GaAs buried layer and 308 are p-GaAs contact layers.

Next, the manufacturing method will be described. First,
The n-GaAs buffer layers 301, n are formed on the n-GaAs substrate 300 whose main surface is the (100) plane by MOCVD.
-AlGaAs cladding layer 302, undoped GaAs
After the crystal growth of the active layer 303, the p-AlGaAs cladding layer 304, and the n-GaAs current blocking layer 305 in order, a SiO film 306 is formed on the surface of the current blocking layer 305 by sputtering, and this is subjected to a normal photoengraving process or the like. Patterning is used to form stripe-shaped openings (FIG. 36 (a)). The stripe direction of the opening is [0/1
1].

Next, using a tartaric acid type etching solution,
Etching the GaAs current blocking layer 305,
A groove is formed as shown in 6 (b). Here, in this wet etching, the n-GaAs current blocking layer 3 is formed on the bottom of the groove.
Leave 05 slightly. This is the exposed p-AlGaAs when the entire GaAs current blocking layer is etched.
This is because the cladding layer 304 oxidizes in air and in an aqueous solution and adversely affects the crystals grown on it, so that this is prevented. The (111) A plane appears on the side surface of the groove.

Next, the wafer is set in the reaction tube of the MOCVD chamber, and HCl and AsH ₃ are flown into the reaction tube to remove the remaining n-GaAs current blocking layer 305 by vapor phase etching (FIG. 36 (c)). ).

Next, following the vapor phase etching process, the p-AlGaAs cladding layer 307 is selectively grown by MOCVD in the groove in the reaction tube without exposing the wafer to air. At this time, as shown in FIG. 36 (d), the surface is not filled so as to be flat. This is because, as shown in FIG. 37, growth starts from both the (111) A plane on the side surface and the (100) plane on the bottom surface, and
This is because the (111) B plane having an angle of about 54 ° with respect to the (100) surface is formed from the position where the O film 306 is in contact, and a convex portion is formed on the wafer as shown in this figure.

Finally, the SiO film 306 is removed with an HF-based etching solution, and then the p-GaAs contact layer 308 is grown again by MOCVD. As shown in FIG. 36 (e),
Even if the p-GaAs contact layer is grown thick, the convex portions on the surface do not become flat.

By the way, the crystal growth technique on a heterogeneous substrate is
For example, it is a key technology for realizing more advanced information processing means such as fusion of a Si electronic device and a compound semiconductor light emitting device, etc., and many research institutions are actively conducting research. In particular, GaAs growth technology on Si substrate is strongly desired to be established due to its wide range of application. However, due to the difference in thermal expansion coefficient between GaAs and Si, Ga
There remains an unsolved problem that a large stress remains in the As layer, resulting in cracks in the GaAs layer.

FIG. 38 shows, for example, US Pat. No. 5,145,793.
No. 6, which is a sixth conventional example, disclosed in Japanese Patent No.
FIG. 6 is a cross-sectional structure diagram for explaining a method of suppressing crack generation in the s crystal growth method. In the figure, 501 is S
i substrate, 502 is a boron nitride film (hereinafter referred to as BN film), 503 is a first GaAs layer, 505 is a second GaAs layer, 506 is a third GaAs layer, and 504 is a mesa groove.

First, as shown in FIG. 38A, a first Ga having a thickness of 2 μm or less is formed on the first main surface of the Si substrate 501.
An As layer 503 is formed by a so-called two-step growth method, and then B is formed on the second main surface of the Si substrate 501 at room temperature.
An N film 502 is formed. Here, the two-step growth method is 50
A low temperature buffer layer of about 100 to 400 angstroms is formed at a low temperature of 0 ° C. or lower, and then the temperature is raised to a temperature of about 700 ° C. suitable for GaAs growth to obtain a Ga of a desired thickness.
This is a method for growing an As layer, and is GaAs on a Si substrate.
This method is widely used for growth. The use of the two-step growth method has the effect of suppressing the three-dimensional growth of GaAs and obtaining a high quality epitaxial growth layer.

Next, as shown in FIG. 38 (b), the first G
A mesa groove 504 is formed so as to surround a portion of the aAs layer 503 corresponding to the device formation region. The mesa groove 504 can be easily formed by ordinary photolithography and wet etching.

Next, after the wafer on which the mesa groove 504 is formed is heated to about 700 to 800 ° C. (FIG. 38 (c)),
As shown in FIG. 38 (d), the second GaAs layer 505 and the third GaAs layer which will be the active layers of the device are formed on the wafer.
Layers 506 are sequentially formed by a conventional MOCVD method.
In this crystal growth, the Si substrate 501 exposed in the mesa groove portion
Since a natural oxide film is formed on the surface, GaAs
The crystal is not grown, and the GaAs layer is selectively grown.

In the conventional example, after this, the first Ga
The GaAs layer around the mesa groove 504 provided after the formation of the As layer 503 is selectively removed to form a mesa groove 507 wider than the mesa groove 504, as shown in FIG. In the growth process of the second and third GaAs layers, the reaction gas flying to the mesa groove portion is not deposited on the Si substrate,
It is consumed for the growth of GaAs around the mesa groove. For this reason, the growth layer becomes thicker in the peripheral portion of the mesa groove, and the edge portion sharply rises. In this excitement,
Since mechanical stress concentrates, cracks will occur from this part. The mesa groove 507 is formed by selectively removing such a raised portion.

The BN film 502 is formed on the second main surface of the Si substrate in this conventional example in order to suppress the warp of the wafer.

Next, the effect of this conventional example will be described.
As shown in FIG. 40, the occurrence of cracks in the GaAs growth layer on the Si substrate and the thickness of the GaAs layer are closely related.

That is, cracks start to occur when the thickness of the GaAs layer is 3 μm or more, and the number of cracks increases as the thickness of the GaAs layer increases. Examination of these crack occurrences revealed that most of them originated from abnormal growth at the wafer edge. Therefore, in this conventional example, first, a first GaAs layer 503 having a thickness of 2 μm or less in which almost no cracks are generated is first grown, and then a mesa groove 504 is formed so as to surround a portion to be a device region.
The second GaAs layer 505 and the third GaAs layer 506, which are the active regions of the device, are formed. With this configuration, cracks from the wafer edge propagate to the mesa groove 504 but do not propagate to the area inside the mesa groove 504, and the number of cracks in the device region can be suppressed.

[0029]

Next, the first conventional example and
AlGa disclosed in Japanese Patent Publication No. 3-59576
The problems in the As etching method will be explained.
It 30 and 31 show AlG in the first conventional example.
Performed to confirm the effect of the etching method of aAs.
FIG. 3 is a cross-sectional structure diagram for explaining the sample structure of the experiment
It In these figures, 1 is a regrown GaAs layer, 2 is A
l_x Ga_1-x  As layer, 23 is GaAs substrate, 211 is
It is a GaAs cap layer. No. 1 shown in FIGS.
30 (a)-
(c) and the steps of FIGS. 31 (a)-(c)
It was First, as the first crystal growth step,
Is formed on the GaAs substrate 23 as shown in FIG.
_x Ga_1-x MO the As layer 2 and the GaAs cap layer 211.
It was continuously grown by the CVD method. Meanwhile, the second sun
In pull, as shown in FIG. 31 (a), on the GaAs substrate 23
To Al _x Ga_1-x  Only the As layer 2 is formed by the MOCVD method.
Grew up. The thickness of each layer is Al_xGa_1-x As layer 2 is 2
μm, and the GaAs cap layer 211 is 0.1 μm.
After this, take the above two types of samples once from the chamber.
It was taken out and stored in the air for several days. In the next step, H
Using the method of gas etching using Cl gas, FIG.
As shown in 0 (b) and FIG. 31 (b), 1 μm etch
30C in the same chamber.
And as shown in FIG. 31 (c), the conventional MOCVD method is used.
Regrown GaAs layer 1 was grown to 2 μm.

FIG. 32 shows Al _x G of the above two types of samples.
The results of the impurity analysis at the interface between the a _1-x As layer 2 and the regrown GaAs layer 1, that is, the vicinity of the regrown interface, using the SIMS analysis method are shown. In the figure, 1 is regrowth Ga
As layer, 2 is an Al _x Ga _1-x As layer, and 3 is a regrowth interface. FIG. 32 (a) shows S of the first sample shown in FIG.
The IMS analysis result and FIG. 32 (b) show the SIMS analysis result of the second sample shown in FIG. 31, respectively. As shown in the figure, segregation of oxygen (O) and chlorine (Cl) was observed at the regrowth interface in both two types of samples. When the dislocation densities of the regrown GaAs layers were examined for the two types of samples, the second sample was 5 × 10 ⁸ pieces / cm ² , and the first sample was 5 × 10 ⁵ pieces / cm ² .

The above results are interpreted as follows. In the second sample that started etching from the surface-oxidized Al _x Ga _1-x As layer 2, the oxide film on the surface and chlorine were combined in the etching process, and adhered to and remained on the wafer surface as etching products and re-growth. It is considered that segregation occurred at the interface 3. Further, the segregation of oxygen and chlorine on the regrown interface 3 causes the crystal quality of the regrown GaAs layer 1 to be significantly deteriorated.

On the other hand, in the first sample provided with the GaAs cap layer 211, the GaAs cap layer 211 prevents Al from forming.
Oxidation of _x Ga _1-x As layer 2 surface been suppressed, segregation of oxygen and chlorine at the regrowth interface 3 has been reduced to a low level compared with the second sample, improved by adopting a cap structure The effect was confirmed. However, segregation of oxygen and chlorine still occurs at the regrown interface, and the dislocation density of the regrown GaAs layer is 1 × 10 ⁴ / cm ² as compared with the typical dislocation density required for compound semiconductor devices. It was deteriorated by more than one digit. This result shows that even a slight oxide film on the surface of the GaAs cap layer causes accumulation of oxygen and chlorine at the regrown interface 3.

That is, it is difficult to obtain a clean etching of AlGaAs only by adopting the GaAs cap structure, and only the technique disclosed in Japanese Patent Publication No. 3-59576 provides a clean etching and a high quality regrown GaAs layer. It was difficult to obtain.

Next, problems in the conventional vapor phase etching method for compound semiconductors shown as the second conventional example will be described. Since the compound semiconductor vapor phase etching method in the second conventional example is configured as described above, the movement of the wafer must be repeated between the high temperature region and the low temperature region, and the substrate temperature must be a certain temperature. Since it needs to be held for a certain period of time until it becomes, it takes several minutes for one cycle of etching, and the etching rate is extremely slow, which is not a practical process. Further Ga
There is a problem that it is difficult to control the desorption of As and Ga from the As surface independently, and it is difficult to perform smooth etching.

Next, problems with the conventional quantum wire laser shown as the third conventional example will be described. Since the quantum wire laser in the third conventional example is configured as described above, it has the following problems. That is, there is a problem that the quantum wires forming the active region of the laser cannot be formed with good controllability. In the third conventional example, (11
1) The structure is such that the laser structure is embedded in the V-shaped groove formed by the A-plane, and the crescent-shaped quantum wire is formed only in a very narrow region at the V-shaped bottom. However, as described above, under the growth conditions of the typical MOCVD method, (111) A
Since the growth rate on the plane is almost equal to the growth rate on the (100) plane, a quantum well structure is formed on the V-shaped surface, and a thick crescent-shaped quantum wire is formed continuously to this quantum well structure. Therefore, the electronic state of the active region is a composite electronic state of quantum wells and quantum wires, and the laser oscillation mode is also multimode. Furthermore, since the quantum wire has a structure coupled to the quantum well, it is difficult to independently derive the characteristics of the quantum wire. Therefore, the third conventional example has a problem that it is difficult to form quantum wires having the same characteristics with good controllability and reproducibility.

Next, the problem with the conventional high-power laser shown as the fourth conventional example will be described. The high-power laser in the fourth conventional example is configured as described above, and after the crystal growth step constituting the basic structure of the laser is completed, the wafer is polished to a desired thickness, and then the resonator length is equivalent to After cleaving into a bar shape having a width corresponding to the following, a window layer is grown on the portion corresponding to the cavity end face of the cleaved wafer by MOCVD method, then electrodes are formed, and finally the window layer end face is coated. It is manufactured by a complicated process of separating chips. Normally, in the manufacturing process of a semiconductor laser, in order to secure mass productivity and reproducibility, electrodes are formed in a wafer state. That is, the method shown in the fourth conventional example in which a window layer is formed in a portion corresponding to the resonator end face of a wafer cleaved in a bar shape having a width corresponding to the resonator length is extremely poor in mass productivity and is industrially difficult. Is unlikely to be a useful manufacturing method. Further, when the window layer is formed by MOCVD after the cavity end face is formed by cleavage, the cavity end face is immediately oxidized to form a surface level as long as the cleavage is performed in air. It is difficult to obtain the desired effect even if the window layer is formed on the cavity end face where the surface level has already been formed, and in order to obtain the desired effect, the steps from cleavage to window layer growth must be performed with an inert gas. There was a problem that it had to be performed in a medium or vacuum.

The reason why the fourth conventional example is constructed by using such complicated steps will be described below. The cavity end surface of the laser is also a reflection end surface of the laser light and needs to be formed as an optically extremely flat surface. Furthermore, it must be a plane perpendicular to the cavity direction. As a result, a conventional manufacturing method has been proposed in which the main surface of the semiconductor is the (100) surface and the cleavage plane perpendicular to the (100) surface is the resonator end surface, and it has been established as a general manufacturing method. However, as semiconductor lasers have become more powerful and multifunctional, it has become strongly desired to establish a technique for forming a laser cavity end face in a wafer state. For example, a reactive ion etching method (RIE method) or the like is required. An end face forming method using a dry etching method is being developed. However, although vertical etching is possible with the current RIE method, there is a problem that physical damage due to collision of ions deteriorates the crystal quality of the end face of the resonator. Furthermore, it is difficult to secure the flatness of the same level as that of the cleaved surface, and the end face forming technique by the RIE method has not been established yet. For the above-mentioned reason, in the existing technology, the laser oscillation end face must be formed by cleavage. Therefore, the method of manufacturing a high-power laser having an end face window structure is similar to the fourth conventional example, in that after the wafer is cleaved, the window is cut. This is a complicated manufacturing method of forming layers.

Next, problems in the conventional method for manufacturing a semiconductor laser shown as the fifth conventional example will be described.
Since the semiconductor laser manufacturing method of the fifth conventional example is configured as described above, there is a problem in that a convex portion is formed on the surface, and photolithography cannot be performed in the process after crystal growth, for example, patterning of the upper electrode. In addition, when the semiconductor laser manufactured by this method is assembled as a junction-down, that is, when the p-GaAs contact layer side is assembled on the heat sink as the contact surface with the heat sink, compressive stress is applied to the active layer. However, there is a problem in that it affects the reliability of the laser.

Next, problems in the conventional crystal growth method shown as the sixth conventional example will be described. Conventional Si
Since the GaAs crystal growth method on the substrate is configured as described above, it has the following problems. FIG. 39 is a diagram for explaining the problems of the conventional GaAs crystal growth method on the Si substrate. In the figure, 510 is a GaAs layer,
Reference numeral 511 indicates a crack. According to our detailed experiments, most of the cracks in the GaAs layer are generated from the wafer edge as described in the section of the related art. Due to the mesa structure in this conventional example, the cracks generated at the wafer edge are almost the same. It was confirmed that all were divided by the mesa groove 504 and did not penetrate into the device area. However, I faced the problem that a dozen or more cracks were generated in the 5 cm × 5 cm mesa groove region and could not be completely suppressed. When the cause of such a crack was investigated in detail, it became clear that the crack originated from the diamond-shaped pit shown in FIG. 39 (b). Furthermore, the diamond-shaped pits are the first GaAs
It was also confirmed that it was generated from the interface between the 503 layer and the second GaAs layer 505.

The reason why the diamond-shaped pits are generated is explained as follows. That is, the first GaAs layer 503
After the growth, the mesa groove 504 is formed by photolithography and wet etching, but it is considered that the resist applied at this time is not completely removed and remains as an impurity on the wafer surface, causing pits.
Generally, it is more difficult to clean the surface of the GaAs layer than the Si substrate, and the Ga is once contaminated by resist coating or the like.
It is extremely difficult to clean the As layer. However, in order to block the propagation of cracks generated from the wafer edge, it is necessary to isolate the device region from the wafer edge by the mesa groove 504 and the like.

On the other hand, as a solution to the above problems, GaA on a Si substrate patterned in advance with an insulating film is used.
Although s growth was also attempted, a new problem occurred that polycrystals were deposited on the insulating film during the growth of the low temperature buffer layer. In general, it is difficult to perform good selective growth in a temperature range of 500 ° C. or lower where a low temperature buffer layer is grown, and a polycrystal is deposited on the insulating film. When a GaAs layer is continuously grown on this polycrystal at a temperature of about 700 ° C., a new polycrystal grows. As a result, the crystals on the entire surface of the wafer are connected, and only the area patterned by the insulating film is isolated. It cannot be turned into Therefore, the crack generated from the wafer edge propagates through the polycrystal on the insulating film and penetrates into the device area.

For the above reasons, Ga on the Si substrate is
In As growth, in order to suppress the propagation of cracks from the wafer edge, the structure of this conventional example must be adopted, resulting in the formation of diamond-shaped pits, which makes it impossible to completely suppress cracks. There was a point.

The present invention has been made to solve the above problems, and in a method of manufacturing a semiconductor device in which gas etching, which is one method of dry etching, and crystal growth by MOCVD are combined, AlGaAs is used.
It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can perform the clean etching, and in which impurities are not segregated at the regrowth interface.

Another object of the present invention is to obtain a smooth etching surface which is comparable to the cleavage surface when dry-etching AlGaAs using a chlorine-based etching gas.

It is another object of the present invention to provide a method of etching a compound semiconductor which can be controlled in units of one atomic layer and which can provide a smooth etching surface, and a manufacturing apparatus suitable for performing this etching.

Another object of the present invention is to provide a method for manufacturing a quantum wire structure which is extremely uniformly controlled.

Further, according to the present invention, the mirror is perpendicular to the resonator of the laser, is extremely flat optically, and has excellent specularity.
Another object of the present invention is to provide a method for manufacturing a semiconductor laser that can realize a cavity end face without physical damage by etching, and further provide a method for manufacturing a high-power laser having a window structure to which this method is applied.

Further, according to the present invention, the surface after embedded growth can be made flat, the manufacturing process after the crystal growth step can be facilitated, and a semiconductor laser having high reliability can be manufactured even when assembled by junction down. It is an object to obtain a laser manufacturing method.

Another object of the present invention is to provide a crystal growth method capable of obtaining good selective growth even at a low temperature of 500 ° C. or lower on a substrate patterned by an insulating film, and further using this technique, It is an object of the present invention to obtain a crystal growth method capable of completely suppressing the occurrence of cracks in crystal growth on a heterogeneous substrate.

[0050]

A method of manufacturing a semiconductor device according to the present invention is directed to a compound semiconductor containing Al as a constituent element.
The first step of continuously forming a compound semiconductor protective layer containing no Al on the body , the second step of forming a selective mask of an insulating film on the compound semiconductor protective layer, and the second step are completed. A third step of immersing the semiconductor wafer in an ammonium sulfide solution, a fourth step of performing dry etching using a chlorine-based gas in the reaction tube, and a microstructure manufactured by the fourth step in the reaction tube Is embedded in the compound semiconductor layer by using the MOCVD method.

[0051] The method of manufacturing a semiconductor device according to the present invention, the first to form a compound semiconductor protective layer containing no Al continuously in compound semiconductors on containing as a constituent element Al
In the reaction tube, a second step of forming a selective smear by an insulating film on the compound semiconductor protective layer, a third step of removing the surface oxide film of the compound semiconductor protective layer in the reaction tube, The fourth step of performing dry etching using a chlorine-based gas and the fine structure produced by the fourth step in the reaction tube are subjected to MOCV.
A fifth step of embedding a compound semiconductor layer by using the method of D.

In the method of manufacturing a semiconductor device according to the present invention, the compound semiconductor containing Al as a constituent element is A
l _x Ga _1-x As (0 ≦ x ≦ 1) and the fourth
Dry etching using chlorine gas in the process
Rows that have by supplying chlorine-based etching gas and the group V gas and the hydrogen gas at the same time, using HCl gas or Cl ₂ gas as the chlorine-based etching gas, arsine (AsH ₃₎ as a group V gas gas, tertiary Either a butyl arsine (C ₄ H ₉ AsH ₂ ) gas or a trimethyl arsine ((CH ₃ ) ₃ As) gas is used, and the partial pressure of the group V gas is 8 × 10 ⁻³ Torr or more. 08T
and orr following a row of <br/> Umono by the ratio of the group V gas flow rate to the etching gas flow rate was 0.25 to 2.5.

[0053]

[0054]

[0055]

[0056]

[0057]

[Action] In the method of manufacturing a semiconductor device according to the invention, to continue with the compound semiconductor containing as a constituent element Al to form a compound semiconductor protective layer containing no Al, selection mask by an insulating film on the protective layer after forming the, by immersing the semiconductor wafer in the ammonium sulfide solution, then subjected to dry etching using a chlorine-based gas in the reaction tube, the technique of MOCVD microstructure produced by the above dry etching process in the reaction tube Since the compound semiconductor layer is used for filling, a good regrowth interface without segregation of impurities can be obtained, and the crystal quality of the regrowth layer can be improved.

In the method of manufacturing a semiconductor device according to the present invention, the compound semiconductor containing Al as a constituent element.
Continuous to form a compound semiconductor protective layer that does not contain Al, after forming a selective mask by an insulating film on the protective layer, and set the semiconductor wafer in the reaction tube, the surface of the protective layer in the reaction tube After removing the oxide film, dry etching is performed in the reaction tube using a chlorine-based gas, and the fine structure formed by the dry etching step in the reaction tube is embedded with the compound semiconductor layer using the MOCVD method. Therefore, a good regrowth interface without segregation of impurities can be obtained, and the crystal quality of the regrowth layer can be improved.

Further, in the method for manufacturing a semiconductor device according to the present invention, the compound semiconductor containing Al as a constituent element is used.
The conductor is Al _x Ga _1-x As (0 ≦ x ≦ 1), and
Dry etching using a chlorine-based gas uses a gas etching method that is performed by simultaneously supplying a chlorine-based etching gas, a group V gas, and a hydrogen gas, and uses HCl gas or Cl ₂ gas as the chlorine-based etching gas. Any of arsine (AsH ₃ ) gas, tert-butylarsine (C ₄ H ₉ AsH ₂ ) gas, or trimethylarsine ((CH ₃ ) ₃ As) gas is used as the group V gas, and the group V gas is used. Gas partial pressure is 8 × 10 ^-3 Tor
and r least 0.08Torr less, the ratio of the group V gas flow rate with respect to the upper Symbol etching gas flow rate less than 0.25 2.
Since 5 so as to line Nau below, with very smooth etching surface can be obtained, it is possible to prevent damage to the etched surface.

[0060]

[0061]

[0062]

[0063]

[0064]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. 1 is a cross-sectional process diagram showing a method of manufacturing a semiconductor device according to a first embodiment of the present invention, in which 23 is a GaAs substrate and 2 is Ga.
AlGaAs layer grown on As substrate 23, 11
Is a GaAs cap layer formed on the AlGaAs layer 2 by successive crystal growth of the AlGaAs layer 2. 1
2 is an oxide film formed on the surface of the GaAs layer 11, 21 is S
An iN film pattern, 13 is a sulfur film, and 1 is a regrown GaAs layer.

Next, the steps of the method for manufacturing the semiconductor device according to the present embodiment will be described.

First, as the first crystal growth step, the Al _x Ga _1-x As layer 2 and the GaAs cap layer 11 were grown on the GaAs substrate 23 by the MOCVD method. The thickness of each layer is 2 μm for the Al _x Ga _1-x As layer and 0.1 μm for the GaAs cap layer. The sample was removed once from the chamber and stored in air for several days. During this storage, a slight oxide film 12 is formed on the surface of the GaAs layer 11 of the sample. This state is shown in Fig. 1 (a). Next, as shown in Fig. 1 (b), SiN of the desired shape was formed on the sample surface.
The film pattern 21 is formed. Next, the sample is immersed in an ammonium sulfide solution. In this example, a (NH ₄ ) ₂ S solution was used as an ammonium sulfide solution and immersed at 60 ° C. for 3 hours. By this step, the portion of the oxide film 12 on the surface of the GaAs layer 11 which is not covered with the SiN film pattern 21 is removed by etching, and the sulfur film 13 is formed as shown in FIG. 1 (c). Next, the wafer was set in a MOCVD chamber and heat-treated at a temperature of 450 ° C. for 30 minutes in a hydrogen atmosphere. Next, AsH ₃ , HCl and H
As shown in FIG. 1 (d), using the mixed gas of 2 as shown in FIG.
Etching is performed to a depth of 1 μm using the film pattern 21 as an etching mask, and then Ga in the same chamber is continued.
As layer 1 was grown.

FIG. 2 shows the results of the impurity analysis in the vicinity of the regrowth interface (cross section taken along the line II-II in FIG. 1 (e)) of the sample manufactured according to the above-mentioned steps, using the SIMS analysis method. In the figure, 1 is a regrown GaAs layer, 2 is Al _x G
The a _1-x As layer 3 is a regrowth interface. As shown in the figure, in the sample manufactured by the manufacturing method of this embodiment,
Segregation of oxygen (O) and chlorine (Cl) to the regrown interface 3 was not observed, and the dislocation density of the regrown GaAs layer was improved to 1 × 10 ⁴ dislocations / cm ⁻² . As shown in FIG. 29 (a), the segregation of impurities at the regrowth interface could not be completely suppressed only by providing the GaAs cap layer in the conventional technique. It was possible to improve the cleanliness of the regrown interface and the crystal quality of the regrown GaAs layer by applying ammonium sulfide treatment as the treatment.

Regarding the effect of the ammonium sulfide treatment,
Applied Physics Vol. 58, No. 9, 1989, 134
It is disclosed on pages 0-1344. That is, the oxide film on the GaAs surface is etched and removed by the ammonium sulfide treatment, and then sulfur atoms are adsorbed on the GaAs surface first layer, which has a surface protecting function. Therefore, due to the sulfur film, GaA
The surface is protected and new surface oxidation can be prevented.

Further, for example, in Japanese Unexamined Patent Publication No. 10683/1992, the surface oxide film is removed by treating the surface of GaAs or AlGaAs with ammonium sulfide before crystal growth on GaAs or AlGaAs. It is described that the quality of the crystal layer on which crystals are grown is improved by suppressing various surface oxidations.

However, in order to grow a high quality GaAs layer on GaAs protected by sulfur, it is necessary to remove the sulfur film by some means before the growth. According to an experiment conducted by the inventor of the present application, it is clear that the sulfur atoms on the GaAs surface are not completely removed only by thermal cleaning by raising the temperature before the MOCVD growth, and segregate at the regrowth interface to deteriorate the crystal quality of the regrowth layer. Became. On the other hand, an effective method for removing the sulfur film, which is a surface protective film, has not been reported so far.

As described in the section of the problem to be solved by the invention, it is extremely important that the surface before etching is not oxidized in order to clean the regrowth interface in the regrowth after vapor phase etching. Is. Ammonium sulfide treatment is a pretreatment method suitable for this purpose, but has a problem that the sulfur film cannot be completely removed as described above. The inventors of the present application found that HCl vapor-phase etching is extremely effective for removing the sulfur film as a method for solving this problem, and further, the objective effect was obtained only by combining ammonium sulfide treatment and HCl vapor-phase etching. It was confirmed that when re-growing after vapor phase etching, the effect of making the re-grown interface clean can be obtained.

AlGa vapor-phase-etched as described above
In MOCVD regrowth on As, the use of the cap GaAs layer alone is extremely insufficient for cleaning the regrowth interface. This indicates that even slight oxidation of the surface of the cap layer hinders the etching and adversely affects it, and cleaning of the surface of the cap GaAs layer is important. The effect of ammonium sulfide treatment, which is one method of surface cleaning, can be confirmed as a practical surface treatment method only when it is combined with HCl vapor phase etching as in the present embodiment, and HCl vapor phase etching and MOCVD growth are performed. We were able to improve the sophistication of the combined process.

In the above embodiment, the wafer on which the sulfur film 13 is formed is set in the MOCVD chamber and heat-treated in a hydrogen atmosphere. However, this heat treatment does not necessarily have to be performed in a hydrogen atmosphere. In addition, this heat treatment can also serve as a wafer temperature raising step in the reaction furnace.

Further, in the above-mentioned embodiment, the compound semiconductor containing aluminum as a constituent element is AlGaAs, and the compound semiconductor layer containing no aluminum and the compound semiconductor layer re-grown which are continuously grown on this are Ga.
Although the case of As is shown, the present invention can be applied to other compound semiconductors.

Embodiment 2. Next, a method of manufacturing a semiconductor device according to the second embodiment of the present invention will be described. Book second
In this embodiment, the GaAs protective layer is continuously formed on AlGaAs and a selective mask made of an insulating film is formed on the protective layer, which is the same as the first embodiment. Instead of performing the treatment, the surface oxide film of the protective layer is removed by another cleaning method in the reaction tube, and subsequently, etching is performed by using a chlorine-based gas in the reaction tube, and the reaction is further performed. The fine structure produced by the above etching in the tube is filled with the compound semiconductor layer by using the MOCVD method.

In the above first embodiment, it was described that ammonium sulfide treatment is effective as a method for cleaning the GaAs cap layer. However, as in the second embodiment, M
Even if the GaAs surface is cleaned by another cleaning method prior to growth in the OCVD chamber, the regrowth interface can be made clean when regrowth is performed after vapor phase etching, as in the first embodiment. ..
As another cleaning method described above, it was confirmed that the same effect can be obtained by cleaning by irradiation with ultraviolet rays or cleaning by using the reducing action of the oxide film by hydrogen plasma.

Also in this embodiment, the compound semiconductor containing aluminum as a constituent element is AlGaAs, and the compound semiconductor layer containing no aluminum and the compound semiconductor layer regrown on which GaAs is continuously grown are GaAs. However, it goes without saying that the present invention can be applied to other compound semiconductors.

Embodiment 3. Next, a method of manufacturing a semiconductor device according to the third embodiment of the present invention will be described. Book Third
The method of manufacturing a semiconductor device according to the embodiment of the present invention is performed accurately in order to obtain a smoother etching surface in vapor phase etching of a compound semiconductor, which is also performed in the method of manufacturing a semiconductor device according to the first and second embodiments. It provides a controlled etching condition. The vapor phase etching method in the method of manufacturing the semiconductor device according to the third embodiment was developed by the following experiment.

For the gas phase etching, a gas etching method was used in which AsH ₃ gas, H ₂ gas and HCl gas were simultaneously supplied into the chamber. The etching temperature is 750 ° C., the etching pressure is 10 Torr, and H
The state of the etched surface when the AsH ₃ gas flow rate was variously changed with respect to the Cl gas flow rate was evaluated in detail.

The sample used for the etching experiment is A
The structure is such that a GaAs cap layer is provided on l _x Ga _1-x As (x = 0.48), and the thickness of each layer is 2 μm for the AlGaAs layer and 0.1 μm for the GaAs cap layer. Etching was performed from the GaAs cap layer, and the surface condition after etching about 1 μm was evaluated using a differential interference microscope.

As a result of this experiment, when the AsH ₃ gas flow rate with respect to the HCl gas flow rate exceeds a certain amount, the etching surface is roughened and smooth etching cannot be performed.
It was also found that a smooth etching surface cannot be obtained even if the AsH ₃ gas flow rate is less than a certain amount. That is, by simultaneously supplying AsH ₃ gas, H ₂ gas, and HCl gas into the chamber, GaAs or AlGaA
When gas etching s, in order to obtain a smooth etching surface, it is necessary to optimize and strictly control the flow rates of AsH ₃ gas and HCl gas supplied to the wafer. This result is interpreted as follows. Since the AlGaAs surface is etched smoothly, As chloride (AsC) from the surface
1 ₃ ), Ga chloride (such as GaCl ₃ ) and Al chloride (such as AlCl ₃ ) need to be uniformly released.
On the other hand, the vaporization temperatures of As chloride, Ga chloride, and Al chloride are different (AsCl ₃ ; 130 ° C., GaCl
₃ ; 201 ° C., AlCl ₃ ; 180 ° C.) It is not easy to evenly remove each chloride from the surface.
AsCl from the surface of the substrate by adding moderate AsH ₃
It is considered that the elimination of ₃ is suppressed and the elimination of each chloride is balanced. For the above reason, in order to obtain a smooth etching surface, As for the HCl gas flow rate
It is necessary to optimize the H ₃ gas flow rate.

FIG. 3A shows an etching temperature of 750 ° C.
Etching pressure is 10 Torr, 10% HCl gas flow rate is 80 sccm, and total gas flow rate is 2.5 slm.
As, in the case of changing the AsH ₃ gas flow rate of 20%, shows the relationship between the dislocation density of the AsH ₃ gas flow rate and GaAs regrown layer (EDP), FIG. 3 (b) AsH ₃ in the same conditions It is a figure which shows the relationship between the gas flow rate and the oxygen concentration (IO) and chlorine concentration (ICl) of the etching surface. From this experimental result, the AsH ₃ gas partial pressure (the value obtained by dividing the AsH ₃ gas flow rate by the total gas flow rate and multiplying it by the reactor internal pressure) was 0.
AsH ₃ for 016 Torr and HCl gas flow rate
The optimum etching condition is when the gas flow rate ratio is 0.5, and the AsH ₃ gas partial pressure is 8 × 10 ⁻³ Torr or more.
It was clarified that a smooth etching surface can be obtained only under the conditions of 08 Torr or less and the AsH ₃ gas flow rate ratio to the HCl gas flow rate of 2.5 or less. Further, it has been clarified that this etching method does not cause damage to the etching surface, which is a problem in the normal RIE method. It is considered that this is because the etching occurs purely by a chemical reaction.

As described above, in this embodiment, Al _x Ga is used.
_{In a} method of manufacturing a semiconductor device including a step of vapor-phase etching _1-x As (0 ≦ x ≦ 1), gas etching performed by simultaneously supplying HCl gas, AsH ₃ gas, and hydrogen gas is performed. AsH ₃ gas partial pressure is 8 × 10 ⁻³ Torr or more and 0.0
8 Torr or less and As for gas flow rate of HCl
Since the H ₃ gas flow rate ratio is set to 2.5 or less for etching, a smooth etching surface can be obtained, and
It is also possible to prevent damage to the etching surface.

In the above embodiment, the gas etching is carried out by using HCl gas as an etching gas and AsH ₃ gas as a group V gas. However, Cl ₂ gas is used as an etching gas and tertiary butyl arsine is used as a group V gas. (C ₄ H ₉ AsH ₂ ) or trimethylarsine ((CH ₃ ) ₃ As) may be used. Even if these gases are used, the etching chemical reaction is exactly the same, so the partial pressure of the group V gas is 8 × 10 ⁻³ Tor.
By performing the etching with r to 0.08 Torr or less and the ratio of the group V gas flow rate to the etching gas flow rate of 2.5 or less, the same effect as in the above embodiment can be obtained.

Furthermore, by combining the etching method according to the present embodiment with the surface cleaning method performed by the method for manufacturing a semiconductor device according to the first or second embodiment, segregation of impurities on the etching surface can be suppressed, When the regrowth is performed, the crystal quality of the regrowth layer becomes extremely good.

Fourth Embodiment Next, a method of manufacturing a semiconductor laser according to the fourth embodiment of the present invention will be described. Figure 4
FIG. 9 is a diagram for explaining a relationship between a mask pattern forming direction and an etching shape when etching is performed by the etching method shown in the third embodiment. In the figure, 21 is a stripe-shaped SiN film pattern, 22
Is a GaAs cap layer, 2 is an AlGaAs layer, and 23 is G
It is an aAs substrate.

FIG. 4A shows (100) of the GaAs substrate 23.
The AlGaAs layer 2 and the GaAs cap layer 22 are continuously crystal-grown on the surface, and the stripe-shaped SiN film pattern 21 is formed on the cap layer 22.
Here, the etching shape by vapor phase etching is different between when the SiN film pattern 21 is patterned so that its stripe direction is the [0/11] direction and when it is patterned so as to be the [011] direction. Figure 4
(b) shows the patterning of the SiN film 21 [0/11]
FIG. 4C shows the etching shape when the etching is performed after performing the etching in the [011] direction, and FIG. 4C shows the etching shape when performing the etching after performing the patterning of the SiN film 21 in the [011] direction.

When stripes are formed in the [0/11] direction as shown in FIG. 4B, the etching shape is (0
The cross-sectional shape is composed of the (11) surface 24 and the (311) surface 25. On the other hand, when stripes are formed in the [011] direction, the etching shape is the cross-sectional shape formed by the (111) B surface 26. As summarized in Table 1, the etching shape by HCl vapor phase etching is clearly different from the etching shape by normal wet etching.

[0089]

[Table 1] Here, by using the etching method according to the third embodiment as the HCl vapor phase etching, the flatness of the side surface exposed by the etching is extremely good, and is comparable to the cleavage surface, and the AlGaAs layer 2 on the side surface is And Ga
No step was formed at the interface of the As cap layer 22.

The method of manufacturing the semiconductor laser according to the fourth embodiment utilizes the characteristics of the etching shape by the etching method according to the third embodiment. That is, when etching is performed using the stripe pattern in the [0/11] direction as a mask, the fact that the (011) plane 24 perpendicular to the (100) plane is partly exposed is used.
This (011) plane is used as the oscillation end face of the laser.

FIG. 7 is a perspective view showing an example of a semiconductor laser manufactured by using the method for manufacturing a semiconductor laser according to the fourth embodiment. In the figure, 50 is an n-GaAs substrate and 51 is n-Al. _x Ga _1-x As first cladding layer,
52 an active layer, 53 _{p-Al x Ga 1-x} As second cladding layer 54 is n-GaAs current blocking layer, the 55 p
-GaAs second cap layer, 56 is a p-GaAs contact layer, and 57 is a light emitting end face.

The semiconductor laser shown in FIG. 7 was manufactured by the following steps. First, a crystal structure of a ridge-embedded laser is formed on a (100) GaAs substrate 50 by a method combining ordinary MOCVD growth and wet etching. Since the manufacturing process of the crystal structure of such a ridge-embedded laser is well known, its detailed description is omitted.

At this time, the resonator direction (ridge stripe direction) is set to the [011] direction. Next, mask the part that will be the resonator of the laser as an insulating film,
Etching is performed using the method shown in the third embodiment. As described above, according to the present etching method, the resonator end face 57 becomes the (011) face which is perpendicular to the (100) face.
The laser oscillation end face can be easily formed. It was confirmed that the obtained resonator end face was extremely smooth and was not damaged by etching, so that it was comparable to the resonator end face and the cleavage face.

Thus, according to this embodiment, (100)
After forming a crystal structure of a ridge-embedded laser made of GaAs and AlGaAs on a semiconductor substrate, a stripe-shaped etching mask having a longitudinal direction in the [0/11] direction is formed on the crystal structure of the laser diode structure, and H
Cl gas, a gas etching performed by supplying AsH ₃ gas, and hydrogen gas simultaneously, AsH ₃
The gas partial pressure is 8 × 10 ⁻³ Torr or more and 0.08 Torr or less, and the AsH ₃ gas flow rate ratio to the HCl gas flow rate is 0.
Since the oscillation end face of the laser diode is formed by performing etching under the condition of 25 or less, it is possible to easily form the laser oscillation end face comparable to the cleavage end face by etching.

Although the basic structure of the laser is the ridge buried type in the above embodiment, it goes without saying that another laser structure may be used.

In the above embodiment, the substrate having the (100) face as the main surface is used and the (011) face is formed as the laser end face. However, the laser end face is (0/1/1). ) Surface may be formed. In addition, a substrate whose principal surface is a crystallographically equivalent plane to the (100) plane is used, and the (100) plane and (01
It is also possible to form a surface having a relationship equivalent to the relationship with the 1) surface or the (0/1/1) surface.

Embodiment 5. Next, a method of manufacturing a semiconductor laser according to the fifth embodiment of the present invention will be described. The semiconductor laser manufacturing method according to the fifth embodiment is (111)
A semiconductor laser having a B-plane as an oscillation end face is manufactured. FIG. 5 is a perspective view showing an etching shape when HCl vapor-phase etching is performed using a stripe pattern in the [011] direction as a mask. As already mentioned, GaAs
When the semiconductor layer crystal-grown on the (100) main surface of the substrate 23 is etched using the stripe pattern in the [011] direction as a mask, the (111) B surface 26 is exposed on the etched side surface along the stripe. To do. (1
11) The angle θ of the B surface with respect to the (100) main surface is about 54 °
Therefore, the laser oscillation end face cannot be used as it is. However, if the main surface of the semiconductor substrate is selected in advance so that the (111) B surface becomes a vertical surface, (111)
It is possible to construct a laser with the B-plane as the oscillation end face.
As shown in FIG. 6, the plane perpendicular to the (111) B plane is, for example, the (1/10) plane, and if it is used on a semiconductor substrate whose principal plane is a plane that is crystallographically equivalent to this plane, By using the etching method according to the third embodiment, it is possible to form a side surface perpendicular to the main surface of the substrate. As described above, for example, the crystal structure of the laser structure is formed on the GaAs substrate having the (1/10) plane as the main surface, and then the portion to be the resonator of the laser is masked with the insulating film, The laser oscillation end face can be easily formed by etching using the method shown in the third embodiment.

In the above embodiment, the substrate having the (1/10) plane as the main surface is used and the (111) B plane is formed as the laser end surface.
If a substrate having a {110} plane that is crystallographically equivalent to the (0) plane is used as a principal plane and etching is performed in the same manner as in the above embodiment using a stripe pattern having a <011> direction as a longitudinal mask, A {111} B plane that is crystallographically equivalent to the (111) B plane perpendicular to the plane is obtained, and this can be used as the laser cavity end face.

Sixth Embodiment Next, a method of manufacturing a semiconductor laser according to the sixth embodiment of the present invention will be described. This manufacturing method utilizes the characteristics of the etching method shown in the third embodiment to manufacture a windowed refractive index guide type semiconductor laser. 8 and 9 are cross-sectional process diagrams illustrating the outline of the manufacturing method. The GaAs substrate 50 has (100) as its main surface.

FIG. 8 is a sectional view as seen from the <0/11> direction, and FIG. 9 is a sectional view as seen from the <011> direction. In the figure, the same reference numerals as those in FIG. 7 denote the same or corresponding parts,
70 is p-GaAs first cap layer, 71 is high resistance Al
_y Ga _1-y As window / block layer, 72 p-electrode, 73
Is the n-electrode.

The steps of the method for manufacturing the semiconductor laser according to this embodiment will be described below. First, the first clad layer 51, the active layer 52, the second clad layer 53, and the p-GaAs first cap layer 70 are formed on the (100) GaAs substrate 50 by MO.
The layers are sequentially formed by the CVD method (FIGS. 8 (a) and 9 (a)).
Next, the SiN film is used as a selection mask for the ridge formation by [01
1] direction as the resonator direction (Fig. 8 (b), Fig. 9)
(b)). Next, etching is performed by the method shown in the third embodiment (FIGS. 8 (c) and 9 (c)). As described above, the portion to be the cavity end face is etched so that the (011) plane, that is, the plane perpendicular to the principal surface of the substrate is formed as shown in FIG. 8 (c). Here, it is desirable to carry out the surface cleaning shown in the first or second embodiment prior to the etching. After performing the above etching, the band gap is larger than that of the active layer under normal MOCVD growth conditions in the same chamber.
To grow high-resistance Al _y Ga _1-y As blocking layer 71 (FIG. 8 (d), the FIG. 9 (d)). FIG. 10A is a perspective view showing a state when this step is completed. At this time, if etching and regrowth are performed in the same chamber by using the method shown in the first or second embodiment, good buried growth can be performed without segregation of impurities at the interface between the window layer and the cavity end face. Is. Next, the SiN film 21 is removed (FIGS. 8 (e) and 9 (e)), and after the p-GaAs contact layer 56 is grown (FIGS. 8 (f) and 9 (f)), the p-electrode 72 is formed. , N-electrode 73
Are formed (FIGS. 8 (g) and 9 (g)). Through the above steps, the basic structure of the windowed refractive index guide type semiconductor laser can be manufactured in a wafer state. Finally, the chip is separated by cleavage or the like to complete a laser chip (FIG. 8).
(h)). A perspective view of the completed index-guided semiconductor laser with window is shown in FIG. 10 (b) (electrodes are omitted).

As described above, the conventional semiconductor laser having the end face window structure has been manufactured by a method having extremely poor mass productivity, in which the oscillation end face is once formed by cleavage and then the window layer is grown on the oscillation end face. According to the sixth embodiment, not only a laser having a window structure can be easily obtained, but also a regrowth interface is in a good state, so that a high-quality index guided semiconductor laser with a window can be obtained. it can.

In the above embodiment, the substrate having the (100) plane as the main surface is used and the (011) plane is formed as the laser end face. However, the laser end face is (0/1/1) ) Surface may be formed. In addition, a substrate whose principal surface is a crystallographically equivalent plane to the (100) plane is used, and the (100) plane and (01
It is also possible to form a surface having a relationship equivalent to the relationship with the 1) surface or the (0/1/1) surface.

Seventh Embodiment Next, a method of manufacturing a semiconductor laser according to the seventh embodiment of the present invention will be described. The method for manufacturing a semiconductor laser according to the seventh embodiment is the same as the above third embodiment.
The ridge waveguide type semiconductor laser is manufactured by applying the etching method of the above embodiment to the etching for forming the ridge. FIG. 11 is a cross-sectional view showing the main steps of the method of manufacturing the ridge waveguide type semiconductor laser according to the seventh embodiment. In the figure, the same symbols as in FIG. 7 are the same or corresponding parts.

The steps of the method for manufacturing the semiconductor laser according to the present embodiment will be described below. First, as shown in FIG. 11 (a), n
N-Al _x Ga _{1 -x} As _1st on the -GaAs substrate 50
Cladding layer 51, active layer 52, p-Al _x Ga _1-x A
s second cladding layer 53, p-GaAs first cap layer 7
0s are sequentially formed by the MOCVD method, the SiN film 21 is formed thereon, and the stripes are patterned. Next, as shown in FIG. 11B, ridge etching is performed by the method shown in the third embodiment to form a ridge. If the stripe direction of the SiN film pattern 21 is the [011] direction, a ridge whose side surface is the (111) B surface is formed.
Here, it is desirable to perform the surface cleaning shown in the first or second embodiment prior to the ridge etching.
Next, as shown in FIG. 11C, the n-GaAs current blocking layer 54 and the p-GaAs second cap layer 55 are embedded and grown by MOCVD in the same chamber as in the step of FIG. 11B. Next, as shown in FIG. 11 (d), after removing the SiN film 21, the p-GaAs contact layer 56 is MO-doped.
It grows by the CVD method, and the basic structure of the laser is completed.

FIG. 12 shows the p-electrode 72 and the n-electrode 7.
FIG. 3 is a perspective view showing an outline of a structure of a ridge wave type laser completed by forming chips 3 and then dividing into chips by cleavage or the like.

In the seventh embodiment, since the ridge formation by vapor phase etching and the MOCVD selective growth shown in the third embodiment are combined, a complicated process such as ridge formation by wet etching is not required, It is possible to greatly simplify the process. Further, if the surface cleaning shown in the first or second embodiment is performed prior to the ridge etching, the regrowth interface also becomes in a good state, so that there is an effect that the life of a high-power laser can be particularly improved.

The semiconductor laser ridge is formed by HCl.
The gas etching using gas is described in, for example, Japanese Patent Application Laid-Open No. 60-163487, but there is no description about the etching conditions in this publication, and the ridge forming of gas etching using HCl gas is performed. The application can be realized only by using the etching method according to the third embodiment.

Eighth Embodiment Next, a method of manufacturing a semiconductor device according to the eighth embodiment of the present invention will be described. FIG.
FIG. 21 is a diagram showing a gas introduction sequence in a compound semiconductor etching method which is a semiconductor device manufacturing method according to the eighth embodiment. In the figure, 120 is an AsH ₃ supply region, 121 is an H ₂ purge region, and 122 is an HCl supply region.

As shown in the figure, this etching method uses AsH.
At the same time that the ₃ gas is introduced, the HCl gas is introduced in a pulsed manner for a time shorter than the AsH ₃ gas introduction time.
And the second etching step of interrupting the introduction of the AsH ₃ gas and the HCl gas and purging the inside of the reaction tube with hydrogen gas. The first etching step and the second etching step are By repeating the process periodically, etching can be performed in units of one atomic layer.

Next, the compound semiconductor of the eighth embodiment
The principle of the etching method will be described. Third embodiment
As described in the above section, for example, using HCl gas, Ga
To obtain a smooth etching surface when etching As
AsH₃ It is necessary to optimize the flow rate. This is suitable
Degree AsH₃ AsCl from the GaAs surface by supply ₃ 
Desorption is suppressed, and AsCl₃ And GaCl₃ Desorption of
Because a smooth etching is obtained when lanced.
It According to our experiments, AsH₃ As the flow rate increases
Confirm that the GaAs etching rate decreases
Was done. This is excessive AsH₃ Is AsCl₃ Suppress the detachment of
It is to control. Therefore excessive AsH₃ Introduce
When HCl gas is introduced in a pulsed manner from a GaAs substrate
GaCl from the surface₃ Only desorption occurs selectively, 1 atomic layer
Can be etched. At this time AsCl₃ Is excessive
AsH₃ Desorption from the GaAs surface is suppressed by
Remains on the surface. Next, AsH₃ When the supply of
AsCl₃ Desorbs from the GaAs surface. The above two steps
By repeating the process, the etch controlled in units of one atomic layer
Can ching.

FIG. 14 shows the etching rate and HCl when etching is performed using the above etching method.
It is the result of examining the relationship with the gas supply pulse time. 1 ML / c at a certain HCl pulse time as shown
It was confirmed that it had an etching rate of Cycle. In this embodiment, the specific pulse time is 0.75.
Although ~ 1.5 seconds is shown, this time is not limited to this time because it depends on the amount of HCl supplied.

As described above, according to the eighth embodiment, 1
Controlled etching can be easily performed on an atomic layer basis, and the time required for one cycle is 4 to 8 seconds, which is significantly shorter than that of the conventional atomic layer controlled etching method.

Ninth Embodiment Next, a semiconductor device manufacturing apparatus and a semiconductor device manufacturing method using this apparatus according to a ninth embodiment of the present invention will be described. FIG. 15 is a sectional structural view showing an outline of a compound semiconductor etching apparatus which is a semiconductor device manufacturing apparatus according to a ninth embodiment of the present invention, and FIG. 16 is a top view of the apparatus. In the figure, 1
Reference numeral 40 is a source gas injector, 141 is a carrier gas injector, 142 is an H ₂ gas injector, 143 is a wafer tray, 144 is a wafer, 145 is a reaction chamber, 146 is a susceptor, and 147 is an exhaust port.

First, the structure of this etching apparatus will be described. A plurality of H ₂ gas injectors 142 are arranged immediately above the susceptor, and the hydrogen curtain 15 formed by the H ₂ gas ejected from the injectors 142 is used.
5, the susceptor 146 is divided into a plurality of regions. In this embodiment, there are four areas 151, 152, 153.
It is divided into 154. Raw material gas injector 140
Are arranged so that the source gas or the etching gas can be independently introduced into the divided regions. The susceptor 146 has a rotating mechanism, and the wafer 144 is configured so that the susceptor 146 can be sequentially moved in the plurality of divided regions as the susceptor 146 rotates.

Next, the etching method will be described. For example simultaneously supplying AsH ₃ gas and HCl gas and H ₂ gas in the region 151 and 153 in FIG. 16, the region 152 and 154 and supplies the H ₂ gas. As described in Example 8 above, under the excessive supply of AsH ₃ , only GaCl ₃ is desorbed from the GaAs surface, and AsC
Desorption of l ₃ is suppressed. That is, the wafer 144 is in the area 15
1 or in the region 153, only Ga is desorbed, and in the region 152 or 154, As is released.
Can be selectively removed, and controlled etching can be performed in units of one atomic layer. Further, since the wafer is configured to move in a plurality of divided regions by the rotation of the susceptor, the time required for one cycle of etching can be greatly reduced as compared with the conventional etching method.

Embodiment 10. FIG. Next, a method of manufacturing the quantum wire structure according to the tenth embodiment of the present invention will be described.
17 and 18, a V-shaped groove is formed in a GaAs substrate 23, and an AlGaAs / GaAs multilayer structure 161 is formed on the V-shaped groove.
It is a figure which shows the growth form inside a V-shaped groove at the time of forming. Here, the main surface of the GaAs substrate 23 is the (100) plane, and the V-shaped groove is formed in the [011] direction in FIG. 17 by the method shown in the third embodiment, and in FIG. 18, [0/11].
Direction were formed by sulfuric acid-based wet etching. When the V-shaped groove in the [011] direction is formed as shown in FIG. 17, the side surface of the V-shaped surface is the (111) B surface. Under typical growth conditions of MOCVD, (11
1) Since there is no growth rate in the direction perpendicular to the B plane, V
The character side surface forms an ungrown surface 162. It was revealed that the growth which does not have continuity with the outside of the V-shape occurs inside the V-shape, and the growth front has a growth front 163 on the surface slightly shallower than the (111) B plane. This growth front 1
The surface orientation of 63 was identified from that angle (311)
It was confirmed that it was the B side.

On the other hand, as shown in FIG. 18, when a V-shaped groove is formed in the [0/11] direction, the side surface of the V-shaped groove is (111) A.
It becomes a face. Since the growth rate on the (111) A plane is almost equal to the growth rate on the (100) plane, the growth inside the V-shape and the outside outside the V-shape are continuous as shown in FIG. Growth progresses in parallel with. As described in the description of the problem of the conventional example shown in FIG. 32, it is difficult to obtain a good quantum wire by using such a growth mode. Further, the form of the V-shaped groove having the (111) B plane on its side surface as shown in FIG. 17 was difficult by ordinary wet etching.

FIG. 19 is a sectional view showing the structure of a quantum wire manufactured by the method for manufacturing a quantum wire according to the tenth embodiment of the present invention, and FIG. 20 is a sectional view showing the manufacturing process thereof. In the figure, 181, 183 are AlGaAs layers, 1
Reference numeral 82 is a GaAs quantum wire, 184 is a GaAs second cap layer, 185 is a GaAs first cap layer, and 186 is Si.
It is an N film.

Next, the steps will be described. First GaA
The AlGaAs layer 181 and the GaAs first layer are formed on the s substrate 180.
The cap layer 185 is sequentially formed by the MOCVD method (FIG. 20 (a)). Next, a SiN film 186 to be a selection mask
To form. At this time, the opening of the SiN film is formed so that the [011] direction becomes the longitudinal direction (FIG. 20 (b)).
). Then, by the method shown in the third embodiment, the side surface (1
11) Form a V-shaped groove composed of the B side (see FIG. 20).
(c)) Subsequently, the GaAs quantum wires 182, the AlGaAs layer 183, and the GaAs second cap layer 184 are selectively grown in the V-shaped groove in the same chamber. Where GaAs
The quantum wire 182 controls the amount of crystal growth so that the width thereof is, for example, about 20 to 30 nm so that a desired quantum effect can be obtained. V with (111) B side
Since the inside of the groove grows as shown in FIG.
A GaAs quantum wire as shown in (3) can be easily obtained.

As described above, in this embodiment, the AlGaAs layer is formed on the GaAs substrate having the (100) plane as the main surface,
A SiN film pattern having a stripe-shaped opening having a [011] direction as a longitudinal direction is formed on the AlGaAs layer,
Using this as a mask, the AlGaAs layer is etched by the method shown in the third embodiment to form a V-shaped groove composed of the (111) B plane, and the V composed of the (111) B plane is formed. Since the GaAs layer is crystal-grown near the bottom of the V-shaped groove and the AlGaAs layer is subsequently crystal-grown to fill the groove, the quantum wire can be formed with good controllability.

In the above embodiment, the substrate having the (100) plane as the main surface was used and the V-shaped groove having the (111) B plane as the side surface was formed.
If a substrate having a {100} plane, which is crystallographically equivalent to the (00) plane, as a main surface is used and a pattern having a stripe-shaped opening having a <011> direction as a longitudinal direction is used as a mask, the same etching as in the above-described embodiment is performed. , A V-shaped groove having a {111} B plane as a side surface, which is crystallographically equivalent to the (111) B plane, is obtained, and by embedding this groove, the same effect as that of the above-mentioned embodiment can be obtained. Is.

Eleventh Embodiment FIG. 21 shows the eleventh aspect of the present invention.
FIG. 6 is a cross-sectional view showing a quantum wire structure manufactured by the method for manufacturing a quantum wire structure according to the example of FIG. One of the inventors of the present application has previously made an invention relating to a semiconductor device, a quantum wire called a manufacturing method thereof, and a manufacturing method thereof (Japanese Patent Application No. Hei.
-335827). The method of manufacturing the quantum wire structure according to the eleventh embodiment is structurally described in the above-mentioned Japanese Patent Application No. 2-33582.
The method for producing the same quantum wire structure as that shown in FIG. 7 is improved so that a higher quality quantum wire can be obtained. In the figure, 190 is a semi-insulating GaAs substrate, 191 is a high resistance (hereinafter referred to as i-) GaAs layer, 1
92 is an i-AlGaAs spacer layer, 193 is n ⁺ -G
aAs cap layer, 194 quantum wires, 195 SiN
Film, 196 is n ⁺ -GaAs cap layer, 197 is n-
This is an AlGaAs electron supply layer.

Next, the manufacturing process will be described. 22 is a cross-sectional process diagram showing a method for producing a quantum wire structure in which a plurality of the structures shown in FIG. 21 are formed on the same substrate. In the figure, the same symbols as in FIG. 21 are the same or corresponding parts. First, a semi-insulating GaAs substrate 190 whose surface is the (100) plane
An i-GaAs layer 191, an i-AlGaAs spacer layer 192, and an n ⁺ -GaAs cap layer 193 are provided on the MOCV.
Crystal growth is sequentially performed by the D method, and a SiN film 195 is further formed on the n ⁺ -GaAs cap layer 193.
The film 195 is patterned to form a plurality of stripe-shaped openings parallel to each other (FIG. 22 (a)). At this time Si
The stripe-shaped openings of the N film are formed so that the [011] direction is the longitudinal direction. Next, using the etching method shown in the third embodiment, as shown in FIG.
A V-shaped groove is formed, and subsequently, the n-AlGaAs electron supply layer 197 and the n ⁺ -GaAs are formed in the same chamber.
A cap layer 196 is selectively grown inside the V-shaped groove (FIG. 22).
(c)). At this time, it is desirable to perform surface cleaning by the method used in the method for manufacturing a semiconductor device according to the first embodiment or the second embodiment before etching the V-shaped groove. Next, after removing the SiN film 195 as shown in FIG. 22D, n ⁺ -G is removed as shown in FIG.
An aAs cap layer 196 is formed on the entire surface of the wafer.

In the quantum wire structure manufactured by the above method, the i-in a very narrow region near the bottom (apex) of the V-shaped groove.
Quantum wires 194 are selectively formed in the GaAs layer. The reason why the quantum wire 194 is formed in such a structure is as described in detail in Japanese Patent Application No. 2-335827.

According to the eleventh embodiment, unlike the conventional method for manufacturing a quantum wire by combining wet etching and regrowth, the quantum wire can be formed with high accuracy, and the above-described first method is used before the V-shaped groove is etched. By performing the surface cleaning by the method used in the method of manufacturing a semiconductor device according to the first embodiment or the second embodiment, a good quality quantum wire in which impurities are not segregated at the regrowth interface can be obtained.

In the eleventh embodiment described above, n ⁺ -GaAs is used as the cap layer 193, but i-GaAs is used instead of n ⁺ -GaAs.
May be used.

Twelfth Embodiment Next explained is a method for manufacturing a semiconductor laser according to the twelfth embodiment of the invention. FIG. 23 is a sectional process view showing the method for manufacturing the semiconductor laser according to the twelfth embodiment of the present invention. In the figure, 2
00 is an n-GaAs substrate, 201 is an n-GaAs buffer layer, 202 is an n-AlGaAs cladding layer, 203 is an undoped GaAs active layer, and 204 is p-AlGaAs.
Clad layer, 205 is an n-GaAs current blocking layer, 2
Reference numeral 06 is a p-GaAs contact layer, and 207 is a SiO ₂ film pattern.

First, the MOCV is formed on the n-GaAs substrate 200.
N-GaAs buffer layer 201, n-AlG by D method
aAs clad layer 202, undoped GaAs active layer 2
03, p-AlGaAs cladding layer 204, n-GaA
s current blocking layer 205 and p-GaAs contact
The layer 206 is sequentially grown. Next, the sputtering
A SiO film 207 is formed on the tact layer 206, and a normal copy is formed.
SiO using true plate ₂ Pattern the film 207,
As shown in 23 (a), a striped opening is formed.
It Here, the stripe direction of the opening is the [011] direction.
is there. FIG. 24 shows the strike formed by the process shown in FIG.
A perspective view for more clearly showing the shape of the lip-shaped opening.
is there. Next, for example, HCl gas is added in the MOCVD reaction tube.
By gas etching used, p-GaAs contact
The layer 206 and the n-GaAs current blocking layer 205 are
Touch. The side surface of this groove is the (111) B surface.
The etching shown in the third embodiment is used as this etching.
It goes without saying that the etching method can be used.
Yes. Further, in etching, the first embodiment or the first embodiment
The method used in the method of manufacturing a semiconductor device according to the second embodiment
It is desirable to further perform surface cleaning. Next
P-AlGaAs clad layer 20 by MOCVD
8, p-GaAs contact layer 209 is grown sequentially.
In this growth, the (111) B plane, which is the side surface, does not grow.
As shown in Fig. 25, the groove is
It is buried by growth and the surface is flat as shown in Fig. 23 (c).
Buried in the hood.

After that, the SiO film 207 is removed, a p-side electrode is formed on the front surface of the wafer, an n-side electrode is formed on the rear surface of the substrate, and the semiconductor laser is completed by dividing into chips by cleavage or the like.

As described above, according to the twelfth embodiment,
A stripe-shaped groove for forming a current path is formed by gas etching using a chlorine-based gas with a pattern having a stripe-shaped opening having a [011] direction different from the conventional direction by 90 ° as a longitudinal direction. By doing so, the groove can be embedded so that the surface becomes flat, the photoengraving process after the crystal growth process can be facilitated, and when the laser is assembled by the junction down, the compressive stress is generated in the active layer. This can be prevented and reliability can be improved.

Further, in this embodiment, since the buried layer is filled in order from the bottom surface of the groove, even if the p-GaAs contact layer 209 is grown continuously to the buried growth of the p-AlGaAs layer 208, the p-GaAs contact layer 209 is grown. Layer 20
Therefore, it is not necessary to grow the p-GaAs contact layer 306 in a crystal growth step different from the buried growth step as in the conventional example of FIG. 33, and the crystal growth step is performed twice. Therefore, the process can be shortened. The p-AlGaAs layer 20
8 and the p-GaAs contact layer 209 are not continuously formed by one crystal growth, but the p-AlGaAs layer 2
After burying 08, the selective growth mask pattern 207 is removed, and the p-GaAs contact layer 20 is formed on the entire surface of the wafer.
9 may be crystal-grown. In this case, not only the p-GaAs contact layer 206 but also the n-GaAs current block layer 205 may be crystal-grown in the first crystal growth step as in the conventional example of FIG.

In the above embodiment, the substrate having the (100) plane as the main surface was used and the groove having the (111) B plane as the side surface was formed. If a substrate having an engineering-equivalent {100} plane as the main surface is used and the same etching as that in the above-mentioned embodiment is carried out using a pattern having a stripe-shaped opening having the <011> direction as the longitudinal direction as a mask, (111) B A groove having a {111} B plane as a side surface, which is crystallographically equivalent to the plane, can be obtained, and by embedding this groove, the same effect as that of the above-described embodiment can be obtained.

Thirteenth Embodiment Next explained is a method for manufacturing a semiconductor laser according to the thirteenth embodiment of the invention. This embodiment is intended to obtain a highly reliable buried heterostructure semiconductor laser made of an AlGaAs material. Figure 2
6 (a) to 6 (d) are sectional process drawings showing a method for manufacturing a semiconductor laser according to a thirteenth embodiment of the present invention. In the figure,
210 is an n-GaAs substrate, 211 is n-AlGaAs
Clad layer, 212 is an undoped GaAs active layer, 21
3 is a p-AlGaAs cladding layer, 214 is a SiO ₂ film pattern, 215 is an i-GaAs current blocking layer, 21
6 is a p-GaAs contact layer.

Next, the manufacturing process will be described. First n-
N-AlG is formed on the GaAs substrate 210 by MOCVD.
aAs clad layer 211, undoped GaAs active layer 2
12, p-AlGaAs clad layer 213 is sequentially crystallized
Lengthen. Although not shown, p-AlGaAs
A p-GaAs cap layer is crystal-grown on the doped layer 213.
It Next, an SiO film 214 is formed on the wafer by sputtering.
Film and SiO using normal photoengraving₂Pattern the membrane 207
And strip it into stripes as shown in Fig. 26 (a).
Form a pattern. Here is the strike of pattern 214
The direction is the [011] direction. Next, MOCVD reaction tube
Inside, for example, by gas etching using HCl gas.
As shown in FIG. 26 (b), the double hetero structure is
Etching-molded into a shape. The side wall of this ridge is (11
1) Side B. At this time, when etching,
Manufacturing method of semiconductor device according to first embodiment or second embodiment
Surface cleaning is performed by the method used in the method. In addition,
As this etching, the etching shown in the third embodiment is performed.
It goes without saying that the Gug method can be used. Eh
I-GaA by MOCVD method following the ching process.
The s-current blocking layer 215 was crystal-grown and shown in FIG. 26 (c).
So that the ridge is embedded. After that, SiO ₂Membrane pattern
The wafer 214 is removed and, as shown in FIG.
A p-GaAs contact layer is crystal-grown on the entire surface.

Thereafter, a p-side electrode is formed on the front surface of the contact layer 216 and an n-side electrode is formed on the rear surface of the substrate 210, and the semiconductor laser is completed by dividing into chip units by cleavage or the like.

Since an interface state is likely to be formed at the regrowth interface in the AlGaAs material, a so-called buried hetero structure laser in which a double hetero structure including an active layer is etched in a ridge shape and then embedded in a current block layer is used. When manufactured, there was a problem that the re-growth interface portion of the active layer was significantly deteriorated and the reliability was extremely low.
In this embodiment, during etching, the surface of the regrown interface can be made clean by performing surface cleaning by the method used in the method for manufacturing a semiconductor device according to the first embodiment or the second embodiment. It is possible to make it difficult to form the positions, and it is possible to improve the reliability of the embedded heterolaser made of an AlGaAs material.

In the above embodiment, the current blocking layer is composed of the high resistance GaAs layer.
As in the modified example shown in FIG. 26E, the p-GaAs layer 21
7 and an n-GaAs layer 218 having a two-layer structure, and pnp
You may make it comprise the electric current blocking structure by an n thyristor.

Fourteenth Embodiment Hereinafter, the fourteenth aspect of the present invention
An example of the above will be described with reference to the drawings. FIG. 27 shows the first of the present invention.
4 is a process diagram showing a crystal growth method according to the fourth embodiment, in which 401 is a Si substrate, 402 is a silicon nitride film (hereinafter referred to as SiN film), and 403 is GaAs.
It is a layer.

The steps will be described below. First, FIG. 27 (a)
On the Si substrate 401 shown in FIG.
The iN film 402 is formed by, for example, the plasma CVD method.

Next, as shown in FIG. 27 (c), the Si
A pattern is formed so that the N film 402 surrounds the device manufacturing region.
Give training. Next, this substrate is treated with ammonia water and H.₂O₂
And H ₂ Cleaning with a mixed solution of O (hereinafter referred to as RCA cleaning solution)
To do. When a Si substrate is cleaned with an RCA cleaning solution, the substrate
Contamination due to resist remaining on the surface is completely removed.
After forming a clean Si surface, a weakly bonded oxide film is formed.
Is made. The oxide film is heated in a MOCVD reactor before it is grown.
It is easily removed by the treatment.

Next, after heat treatment is performed to clean the Si surface, as shown in FIG. 27D, a GaAs layer 403 is formed to a desired thickness by the 21st growth method. Here, the low temperature buffer layer is formed by using AsH ₃ gas as a raw material,
And trimethylgallium (TMG) together with HCl gas at the same time. In this embodiment, the molar flow ratio of HCl gas to TMG is 0.25.
So that In normal MOCVD growth,
In the temperature range of 500 ° C. or lower, polycrystal is deposited on the insulating film and good selective growth cannot be obtained. On the other hand, by introducing a slight amount of HCl gas during the growth as in this example. , Polycrystal precipitation was completely suppressed, and good selective growth was obtained. As a result, after the low temperature buffer layer was formed, it was suitable for the growth of GaAs.
When a GaAs layer having a desired thickness was grown at a temperature of about 00 ° C., no polycrystal was deposited on the insulating film, and the GaAs layer could be grown only on the portion not patterned by the insulating film.

As described in the section of the problem to be solved by the invention, it is difficult to satisfactorily selectively grow the low temperature buffer layer in the conventional technique, and as a result, cracks cannot be suppressed. was there. Therefore, it was confirmed that the measures to prevent the propagation of cracks by the mesa groove described in the conventional example were adopted and the effect was achieved. In this case, the diamond-shaped pits were formed by performing high temperature growth with the resist remaining on the wafer. Occurred, and cracks started from the diamond-shaped pits as starting points, so cracks were not completely suppressed.

In the fourteenth embodiment, after the insulating film is patterned, the Si substrate is cleaned by RCA.
Since the cleaning was performed and then the GaAs layer was grown by the above-described method, good selective growth could be performed. All the cracks generated from the edge of the wafer were blocked by the insulating film, and the cracks did not propagate to the device region at all. Furthermore, since the selective growth region can be formed on a sufficiently cleaned Si substrate, the diamond-shaped pits as in the conventional example do not occur, and the diamond-shaped pits also cause cracks. I was able to suppress it completely.

In the fourteenth embodiment, S
The case where GaAs is grown on the i substrate has been described, but the case where InP is grown on the Si substrate or GaA is used.
It was confirmed that the same effect was obtained even when InP was grown on the s substrate. Here, when the substrate is GaAs, it is difficult to sufficiently clean the surface of the substrate after forming the insulating film pattern. However, in the present invention, unlike the conventional method in which high temperature growth is directly performed on the GaAs layer where the resist remains on the surface, this Ga that is not sufficiently clean is used.
Since the low-temperature buffer layer is first formed on the As substrate, diamond-shaped pits caused by impurities on the substrate are unlikely to occur and cracks can be sufficiently suppressed.

Further, it can be easily inferred that the same effect as shown in the fourteenth embodiment can be obtained by using the present technique for the crystal growth on other kinds of substrates.

Fifteenth Embodiment FIG. 28 shows the first of the present invention.
FIG. 6 is a diagram for explaining a crystal growth method according to the fifth example. This graph shows MOCV of GaAs on a GaAs substrate.
It shows changes in the growth rate due to the addition of HCl gas during crystal growth during D growth.

As shown in the figure, in the region where the HCl flow rate is 3 sccm or less, the growth rate hardly changes, while the H
It was confirmed that when the Cl gas flow rate was 5 sccm or more, the growth rate decreased as the HCl gas flow rate increased. This is H
This reflects that the etching action by Cl gas occurs at the same time as the growth action by material gas. From this figure, it can be confirmed that it is extremely important to set the HCl gas flow rate to a certain amount or less in order to improve only the selective growth property without impairing the uniformity and reproducibility by MOCVD. That is, it is extremely important to set the HCl gas flow rate such that the molar flow rate ratio of HCl gas to TMG is approximately 0.3 or less.

FIG. 29 shows the results of examining the influence on the crystal quality by supplying HCl gas at the same time during MOCVD growth. Al0.37 grown on a GaAs substrate was examined.
4 shows a photoluminescence (PL) spectrum of a Ga0.63As layer at 4.2K. In the figure, 41
0 is the case where the HCl flow rate is the growth rate when the molar flow rate ratio of the HCl gas to the group III gas ([HCl] / [III]) is 0.25, and 411 is the case where the growth rate is 1.0. P of Al0.37Ga0.63As growth layer at 4.2K
L spectra are shown respectively. As shown in the figure, when [HCl] / [III] is set to 0.25, PL
The spectrum showed good crystallinity equivalent to that of ordinary MCOVD growth, whereas the PL peak intensity was about 1/10 in the sample grown by setting [HCl] / [III] to 1.
It decreased to 0, and the behavior of the impurity emission peak was dominant. When the impurity analysis of this sample was examined by the SIMS method, it was revealed that Cl and O were mixed in the crystal. This result shows that the crystal quality was deteriorated by adding a large amount of HCl gas.

As described above, from the results of the experiments shown in FIGS. 28 and 29, it is preferable to suppress [HCl] / [III] to 0.3 or less in terms of crystal quality, uniformity and reproducibility. It was first shown to be extremely important.

Although the crystal quality when GaAs or AlGaAs is grown on the GaAs substrate has been described in the above embodiment, it is particularly low temperature buffer layer when growing on a different substrate such as GaAs on Si substrate. When HCl gas is supplied at the same time when growing, [HCl] /
It was also confirmed that by setting [III] to 0.3 or less, excellent crystal quality and good selective growth capable of preventing crack generation can be obtained.

In the fourteenth and fifteenth embodiments,
Although the case where the HCl gas is caused to flow at the same time as the material gas is shown, the Cl ₂ gas may be caused to flow instead of the HCl gas, and the same effect as that of each of the above-described embodiments is obtained.

[0153]

As it is evident from the foregoing description, according to the method of manufacturing a semiconductor device according to the present invention, to form a compound semiconductor protective layer containing no Al was continued with the compound semiconductor containing as a constituent element Al, the protecting After forming a selective mask with an insulating film on the layer, the semiconductor wafer is dipped in an ammonium sulfide solution, and then a chlorine-based gas is used to dry the semiconductor wafer in the reaction tube.
Performs Lee etching, the gong in the reaction tube
(B) MOC of the fine structure produced by the etching process
Since the compound semiconductor layer is embedded by using the VD method, a good regrowth interface without segregation of impurities can be obtained, and the crystal quality of the regrowth layer can be improved.

[0154] Further, according to the method of manufacturing a semiconductor device according to the present invention, the compound semiconductor containing as a constituent element Al
Continuous to form a compound semiconductor protective layer that does not contain Al,
After forming a selection mask by an insulating film on the protective layer,
A semiconductor wafer is set in a reaction tube, the surface oxide film of the protective layer is removed in the reaction tube, dry etching is then performed in the reaction tube using a chlorine-based gas, and the dry etching process is performed in the reaction tube. Since the fine structure thus formed is filled with the compound semiconductor layer by using the MOCVD method, a good regrowth interface without segregation of impurities can be obtained, and the crystal quality of the regrowth layer can be improved.

Further, according to the method of manufacturing a semiconductor device of the present invention, a compound semiconductor containing Al as a constituent element is formed.
The body is Al _x Ga _1-x As (0 ≦ x ≦ 1) and the salt is
Dry etching using an elemental gas uses a gas etching method that is performed by simultaneously supplying a chlorine-based etching gas, a group V gas, and a hydrogen gas, and uses HCl gas or Cl ₂ gas as the chlorine-based etching gas. ,
Any one of arsine (AsH ₃ ) gas, tert-butyl arsine (C ₄ H ₉ AsH ₂ ) gas, or trimethylarsine ((CH ₃ ) ₃ As) gas is used as the group V gas, and the group V gas is used. 2. The partial pressure is set to 8 × 10 ⁻³ Torr or more and 0.08 Torr or less, and the ratio of the group V gas flow rate to the etching gas flow rate is 0.25 or more.2.
Since 5 so as to line Nau below, with very smooth etching surface can be obtained, there is an effect that it is possible to prevent damage to the etched surface.

[0156]

[0157]

[0158]

[0159]

[Brief description of drawings]

FIG. 1 is a diagram illustrating a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing measurement results of impurity analysis for explaining the effect of the compound semiconductor etching method in the first example of the present invention.

FIG. 3 is a drawing for explaining the manufacturing method of the semiconductor device according to the third embodiment of the present invention.

FIG. 4 is a drawing for explaining the manufacturing method of the semiconductor laser according to the fourth embodiment of the present invention.

FIG. 5 is a drawing for explaining the manufacturing method of the semiconductor laser according to the fifth embodiment of the present invention.

FIG. 6 is a drawing for explaining the manufacturing method of the semiconductor laser according to the fifth embodiment of the present invention.

FIG. 7 is a diagram showing an example of a semiconductor laser manufactured by the method for manufacturing a semiconductor laser according to the fourth embodiment of the present invention.

FIG. 8 is a sectional process view showing a method of manufacturing a refractive index guide type semiconductor laser with a window according to a sixth embodiment of the present invention.

FIG. 9 is a sectional process view showing the method of manufacturing the index-guided semiconductor laser with window according to the sixth embodiment of the present invention.

FIG. 10 is a perspective view for explaining a method for manufacturing a refractive index guide type semiconductor laser with a window according to another embodiment of the present invention.

FIG. 11 is a sectional process drawing showing the method of manufacturing the ridge type semiconductor laser according to the seventh embodiment of the present invention.

FIG. 12 is a perspective view showing an example of a ridge type semiconductor laser manufactured by a method for manufacturing a ridge type semiconductor laser according to a seventh embodiment of the present invention.

FIG. 13 is a gas introduction sequence diagram for explaining a method for manufacturing a semiconductor device according to an eighth embodiment of the present invention.

FIG. 14 is a diagram showing an etching rate for explaining a method for manufacturing a semiconductor device according to an eighth embodiment of the present invention.

FIG. 15 is a sectional structural view showing an outline of a semiconductor device manufacturing apparatus according to a ninth embodiment of the present invention.

FIG. 16 is a top view showing the outline of a semiconductor device manufacturing apparatus according to a ninth embodiment of the present invention.

FIG. 17 is a drawing for explaining the manufacturing method of the quantum wire structure according to the tenth embodiment of the present invention.

FIG. 18 is a drawing for explaining the manufacturing method of the quantum wire structure according to the tenth embodiment of the present invention.

FIG. 19 is a drawing for explaining the manufacturing method of the quantum wire structure according to the tenth embodiment of the present invention.

FIG. 20 is a drawing for explaining the manufacturing method of the quantum wire structure according to the tenth embodiment of the present invention.

FIG. 21 is a drawing for explaining the manufacturing method of the quantum wire structure according to the eleventh embodiment of the present invention.

FIG. 22 is a drawing for explaining the manufacturing method of the quantum wire structure according to the eleventh embodiment of the present invention.

FIG. 23 is a sectional process drawing showing the method of manufacturing the semiconductor laser according to the twelfth embodiment of the present invention.

FIG. 24 is a perspective view for explaining the method for manufacturing the semiconductor laser according to the twelfth embodiment of the present invention.

FIG. 25 is a diagram showing a state of embedded crystal growth in a method for manufacturing a semiconductor laser according to a twelfth embodiment of the present invention.

FIG. 26 is a drawing for explaining the manufacturing method of the semiconductor laser according to the thirteenth embodiment of the present invention.

FIG. 27 is a sectional process drawing for explaining the crystal growing method according to the fourteenth embodiment of the present invention.

FIG. 28 is a diagram showing the relationship between the growth rate and the HCl flow rate for explaining the crystal growth method according to the fifteenth embodiment of the present invention.

FIG. 29 is a diagram showing a photoluminescence spectrum at 4.2 K for explaining the crystal growth method according to the fifteenth embodiment of the present invention.

FIG. 30 is a cross-sectional structure diagram for explaining problems in a conventional method of etching a compound semiconductor.

FIG. 31 is a cross-sectional structure diagram for explaining problems of a conventional compound semiconductor etching method.

FIG. 32 is a diagram showing an impurity analysis result for explaining a problem of the conventional compound semiconductor etching method.

FIG. 33 is a perspective view for explaining a structure of a conventional semiconductor laser having a window structure.

FIG. 34 is a diagram for explaining a conventional compound semiconductor etching method.

FIG. 35 is a diagram for explaining a problem of a quantum wire in a conventional quantum wire laser.

FIG. 36 is a sectional process diagram showing the conventional method for manufacturing a semiconductor laser.

FIG. 37 is a diagram showing a state of embedded crystal growth in a conventional semiconductor laser manufacturing method.

FIG. 38 is a sectional process diagram for explaining an example of the conventional GaAs growth method on a Si substrate.

FIG. 39 is a diagram for explaining a problem of a conventional GaAs growth method on a Si substrate.

FIG. 40 is a diagram showing the relationship between the occurrence of cracks in the GaAs growth layer on the Si substrate and the thickness of the GaAs layer.

[Explanation of symbols]

1 regrown GaAs layer, 2 Al_x Ga_1-x As layer, 3
  Regrowth interface, 11 GaAs cap layer, 12 oxidation
Film, 13 sulfur film, 21 SiN film pattern, 23 G
aAs substrate, 24 (011) plane, 25 (311)
Plane, 26 (111) B plane, 50 n-GaAs substrate,
51 n-Al_x Ga_1-x As first clad layer, 52
Active layer, 53 p-Al_x Ga_1-x  As second clad
Layer, 54n-GaAs current blocking layer, 55p-Ga
As layer, 56 p-GaAs contact layer, 57 light emission
End face, 70 p-GaAs layer, 71 High resistance Al_y Ga
_1-y As window / block layer, 72 p-electrode, 73 n-
Electrode, 120 AsH₃Supply area, 121 H2 purge
Area, 122 HCl supply area, 140 source gas in
Injector, 141 carrier gas injector, 142
  H2 gas injector, 143 wafer tray, 14
4 wafers, 145 reaction chambers, 146 susceptors
147 exhaust port, 161 GaAs / AlGaAs
Multiple layers, 162 ungrown surface, 163 growth front, 1
81 AlGaAs layer, 182 GaAs quantum wire, 1
83 AlGaAs layer, 184 GaAs cap layer,
185 GaAs cap layer, 186 SiN film, 191
  i-GaAs layer, 192 i-AlGaAs spacer
Layer, 193 n⁺-GaAs cap layer, 194 quantum
Fine wire, 195 SiN film, 196 n⁺-GaAs
Layer, 197 n-AlGaAs electron supply layer, 200
  n-GaAs substrate, 201 n-GaAs layer, 202
  n-AlGaAs cladding layer, 203 undoped G
aAs layer, 204 p-AlGaAs cladding layer, 20
5 n-GaAs current blocking layer, 206 p-GaA
s contact layer, 207 SiO₂Membrane, 208 p-A
lGaAs embedded layer, 209 p-GaAs embedded
Layer, 401 Si substrate, 402 SiN substrate 403 Ga
As layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tatsuya Kimura 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corp. Optical and Microwave Device Research Laboratory (56) Reference JP-A-2-192119 (JP, JP, 192119) A) JP-A-4-145622 (JP, A) JP-A-5-259568 (JP, A) JP-A-4-211187 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) ) H01S 5/00-5/50 H01L 21/306

Claims (5)

(57) [Claims] 1. A compound containing Al as a constituent element semiconductors
The first step of continuously forming an Al-free compound semiconductor protective layer on the top, the second step of forming a selective mask of an insulating film on the compound semiconductor protective layer, and the second step are completed. The third step of immersing the semiconductor wafer in an ammonium sulfide solution, the fourth step of performing dry etching using a chlorine-based gas in the reaction tube, and the fine structure created by the fourth step in the reaction tube are performed. A fifth step of burying with a compound semiconductor layer by using a MOCVD method. 2. A compound containing Al as a constituent element semiconductors
A first step of continuously forming a compound semiconductor protective layer containing no Al on the upper surface, a second step of forming a selective mask of an insulating film on the compound semiconductor protective layer, and the compound semiconductor protective layer in a reaction tube. Created by the third step of removing the surface oxide film of the layer, the fourth step of performing dry etching using a chlorine-based gas in the reaction tube, and the fourth step of the reaction tube. And a fifth step of burying the formed fine structure with a compound semiconductor layer by using a MOCVD method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the compound semiconductor containing Al as a constituent element is AlGaAs, and the compound semiconductor protective layer is GaAs. 4. A compound half containing Al as a constituent element.
The conductor is Al _x Ga _1-x As (0 ≦ x ≦ 1) and the dry etch using the chlorine-based gas in the fourth step is performed.
Quenching the rows that have by supplying a chlorine-based etching gas and the group V gas and hydrogen gas simultaneously, using HCl gas or Cl ₂ gas as the chlorine-based etching gas, a group V gas selected from arsine (AsH ₃₎ Gas, tert-butylarsine (C ₄ H ₉ AsH ₂ ) gas, or trimethylarsine ((CH ₃ ) ₃ As) gas, and the partial pressure of the group V gas is 8 × 10 ⁻³ Torr. 0.08T or more
and orr less, with respect to the upper Symbol etching gas flow rate of a semiconductor device according to claim 1 or 2, wherein the row of <br/> Ukoto by the ratio of the group V gas flow rate set to 0.25 to 2.5 Production method. 5. HCl as the chlorine-based etching gas
5. The method of manufacturing a semiconductor device according to claim 4, wherein gas and arsine (AsH ₃ ) gas are used as the group V gas.