GB2288678A

GB2288678A - Memory including voltage pumping circuit

Info

Publication number: GB2288678A
Application number: GB9511378A
Authority: GB
Inventors: Do-Chan Choi; Dong-Soojun; Yong-Sik Seok; Chan-Sok Park; Young-Gwon Choi; Dong-Jae Lee
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1991-11-07
Filing date: 1992-11-09
Publication date: 1995-10-25
Anticipated expiration: 2012-11-09
Also published as: GB2288678B; GB9511378D0

Abstract

A circuit for pumping a supply voltage for use in a semiconductor memory using a low supply voltage includes a voltage pumping circuit 300 for generating at an initial power-up state a first output voltage Vpp being substantially identical to the supply voltage, and pumping up the output voltage to a second output voltage Vpp higher than the first output voltage Vpp prior to or upon the semiconductor memory being enabled in response to pulses output from an oscillator 100. Further aspects relate to the voltage pumping circuits and to semiconductor memory devices. A detailed circuit is described (Figs 3A - 3C) using MOS transistors. In a further embodiment (Fig 4), which is described in detail (figs 5A - 5D), the output from the voltage pumping circuit (60) is fed via a transistor (M) under control of a control circuit (70). In a further embodiment (Fig 6) a pumping circuit (500) producing a raised voltage Vpp has an active kicker (600) for compensating for dropping of the raised voltage Vpp, a detector (700) for detecting the level of the raised Vpp and campers (800, 900) for preventing the raised voltage Vpp from being raised over a given level. Details are described of MOS circuits of the pumping circuit (500, Figs 7A and 7B), the active kicker (600, Fig 7C), the detector (700, Fig 7E) and the campers (800, 900, Figs 7F - 7H). <IMAGE>

Description

VOLTAGE PUMPING CIRCUITS The present invention relates to voltage pumping circuits, and is concerned particularly, although not exclusively, with circuits for supplying a voltage to semiconductor memory devices of high complexity that require a low level source voltage.

The complexity of semiconductor memory devices has rapidly increased, so that memory devices with a capacity of several tens of mega bits (Mbit) are fabricated to design rules of 1-micron (micrometer) or less. Such semiconductor memory devices mostly comprise a plurality of CMOS elements, where the operating voltage is applied across thin dielectric films.

As the complexity increases, the space between the CMOS elements or signal lines is reduced together with the thickness of the dielectric films, so that it is required to lower the level of the operating voltage. For example, memory devices of the order of 64Mbit usually have an operating voltage of 1.5V.

However, if the operating voltage of the memory device is only lowered without considering other conditions, the voltage dropping caused by the threshold voltage of the MOS transistors and the resistances of signal lines during the transmission of data signals often makes it impossible to read and write data. In order to resolve this problem, an externally applied source voltage is amplified within the chip of the memory device. Such amplifying means is usually a called pumping circuit, bootstrapping circuit or voltageraising circuit, and in the present application is referred to as a pumping circuit.

Referring to Figure 1A of the accompanying diagrammatic drawings for illustrating a conventional pumping circuit, enable clock pulses are applied through a drive circuit 1, 2 to one electrode of a pumping capacitor 3, which provides at the other electrode a pumped voltage Vpp increased by coupling to a level greater than that of the voltage applied to the one electrode.

Although this pumping circuit has a simple structure, there is no means provided for stabilizing the output of the pumping capacitor 3 and therefore its operational reliability decreases in memory devices of high complexity with a low operating voltage. Moreover it is difficult to adjust the timing of the enable clock pulses.

In order to improve the pumping circuit of Figure 1A, there has been proposed another voltage pumping circuit (see IEEE JOURNAL OF SOLID STATE CIRCUIT, VOL.24, NO .3, JUNE 1989) as shown in Figure 1B of the accompanying diagrammatic drawings. In Figure 1B, PHB represents a word line precharge signal, 1 and 4?2 clock signals to enable row address signals, and OSC an oscillator signal. When the chip is enabled on standby, i.e. precharging before and after performing a read/write operation, the word line precharge signal PHB goes to Vpp level. In the operational mode of the chip, the signal 4 > PHB is supplied with ground voltage level (0V).

As shown in Figure 1B, if the word line precharge signal 4 > PHB is dropped from Vpp level to 0V, the clock signals 4 > 1 and 2 are raised to Vcc level. Then the clock signal 1 causes the coupling effect of capacitors C1 and C2 to raise the voltages of the signal lines G1 and G2 to Vcc level or more, while the clock signal 2 causes the coupling effect of capacitors C3 and C4 to raise the voltages of the signal lines G3 and G4 to Vpp level greater than Vcc level. Thereafter the raised voltages of the signal lines G1 and G2 are dropped to 0V by the clock signal < > 2. The voltages of the signal lines G3 and G4 are the output Vpp. If the chip changes state from operational mode to standby, the word line precharge signal PHB is applied with Vpp level and therefore the output of the circuit of Figure 1B has Vcc level. The voltage of Vpp level is produced only when a given row address signal is applied as an active signal.

The circuit of Figure 1B resolves the problems associated with the unstable voltage of Vpp and the precise timing of the input signal, but results in other problems. Namely, the additional circuit means for generating the word line precharge signal PHB and clock signals 1 and 4?2 are required, making it difficult to obtain a chip of high complexity. Moreover, the voltage Vpp is output when the row address signal is applied active, enabling the clock signals 4?1 and < > 2, thereby degrading the operational speed of the chip.

Additionally, the circuit of Figure 1B shows low value of the voltage pumping efficiency in semiconductor memory devices of the order of 16Mbit or 64Mbit.

Figure 1C of the accompanying diagrammatic drawings shows another conventional voltage pumping circuit, which has been proposed by Yoshinobu Nakakome, et al of the Japanese Hitachi Company in an article entitled "An Experimental 1.5-V 64Mbit DRAM", IEEE Journal of Solid State Circuits, Vol.26, No.4, April 1991, pp.465-472. This article discloses a word line driver circuit for preventing the word line voltage from being dropped by the threshold voltage of an access transistor. As shown in Figure 1C, the word line driver produces a pumped voltage V of 2Vcc level by the feedback operation of charge pump circuits CP1 and CP2 even when the chip is in a low operation voltage. This circuit has the following problems.

First, the capacitance of the capacitor C connected to the node VCH becomes so great that the area of the chip is increased. When a voltage of "high" level is transferred to a selected word line, charge sharing occurs between the capacitor C and the capacitance component CWL of the word line. This relationship may be expressed by the following Eq. (1): CCH x VCH = (CWL + CCH) x VWL VWL = [CCH / (CWL + CCH)] X VCH .... (Eq. 1) From the Eq. 1, it is preferable for the voltage VWL of the word line to equal the pumped voltage v To this end, the capacitance C should have a value great enough to ignore the capacitance CWL. After charge sharing is effected, the voltage dropping of the node VCH should be small to secure stable operation of the circuit in the next cycle. Hence, the capacitance C should be great.

Second, in order to make the voltage of the selected word line "high", the voltage pumping circuit is kept working to charge the node VCH, thus increasing the power consumption of the chip. Moreover, the continuous working of the voltage pumping circuit of Figure 1C may excessively increase the voltage of the node V, to destroy the adjacent transistors.

Preferred embodiments of the present invention aim to provide a voltage pumping circuit for raising the level of an externally applied voltage within a semiconductor memory device of high complexity with a low power consumption.

It is another aim to provide a voltage pumping circuit for raising the level of an externally applied voltage that enables a semiconductor memory device of high complexity to work at a high speed with a low power consumption.

It is a further aim to provide a voltage compensation circuit that immediately compensates for dropping of the output voltage of a voltage pumping circuit conventionally used in a semiconductor memory device of high complexity with a low power consumption.

It is still another aim to provide a voltage compensation circuit that continuously raises the source voltage to a given level to improve the working efficiency of a semiconductor memory chip of high complexity.

It is a further aim to provide a voltage pumping circuit that raises the level of an externally applied voltage within a semiconductor memory chip without increasing the chip size.

It is a further aim to provide a voltage pumping circuit that reduces the power consumption of a semiconductor memory device of high complexity.

According to one aspect of the present invention, a voltage pumping means used in a semiconductor memory device with an oscillator for generating pulses of a given waveform comprises an input means for responding to the pulses of the oscillator, voltage pumping means for producing a voltage raised to a given level in response to an output signal of the input means, and bias means for transforming the output signal of the voltage pumping means to a source voltage level of a chip while powering the chip.

According to another aspect of the present invention, a semiconductor memory device with a voltage pumping node for receiving a voltage raised to a given level over an operating source voltage of the chip is provided with a voltage compensation circuit, which comprises an input means for receiving an enable signal, voltage pumping means for generating a raised voltage in response to the transition of an output signal of the input means, and output means for transferring the raised voltage of the voltage pumping means, wherein a voltage drop of the voltage pumping node is immediately compensated in active operation of the chip such as enabling and testing of the chip. In this case, the enable signal may represent various signals according to the operational modes of the chip and may be generated by a row address strobe (RAS) signal or column address strobe (CAS) signal.

According to a further aspect of the present invention, a semiconductor memory device with circuits using a raised voltage over a source voltage comprises a voltage pumping node connected with said circuits, a voltage pumping circuit for generating a pumping voltage of a given level during powering of the chip, isolation means for transferring the pumping voltage to the voltage pumping node, an active kicker for compensating for dropping of the pumping voltage in response to an output signal of said circuits, a detector for producing a detection signal in response to the voltage level of the voltage pumping node to feed it back at least to the voltage pumping circuit, and a clamper for dropping the raised voltage by the raised amount in response to the detection signal. The pumping voltage produced by the voltage pumping circuit may be precharged to the source voltage level, while the raised voltage may be precharged to a level dropped by the threshold voltage of an isolation transistor from the source voltage. The voltage pumping circuit and active kicker may receive the source voltage as an input signal. The active kicker may transfer the raised voltage through another isolation transistor to the raised voltage using circuits, which isolation transistor transfers an internally prepared pumping voltage as the raised voltage to the raised voltage using circuits.

According to another aspect of the present invention, there is provided a semiconductor memory device arranged to be powered by a supply voltage, and comprising an oscillator for generating pulses, and a voltage pumping circuit for generating at an initial power-up state a first output voltage which is substantially identical to said supply voltage, and pumping an output voltage up to a second output voltage prior to or upon the semiconductor memory device being enabled in response to pulses output from said oscillator, said second output voltage being higher than said first output voltage.

A semiconductor memory device as above may further comprise a detector for detecting variation of the output of said voltage pumping circuit, whereby said voltage pumping circuit operates to control the pumping operation thereof in response to the detection so as to maintain the output at said second output voltage.

Preferably, said voltage pumping circuit comprises: input means operating in response to the pulses output from said oscillator; voltage pumping means for generating said second output voltage in response to the output of said input means; and bias means for forcing at the initial power-up state the output of said voltage pumping circuit into said first output voltage.

Preferably, said input means receive the pulses output from said oscillator to generate a pair of complementary signals.

A semiconductor memory device as above may further comprise driving means for amplifying the output signals of said input means.

Preferably, said voltage pumping means comprise a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to the output signals of said driving means.

A semiconductor memory device as above may further comprise first and second transmission transistors for providing said second output voltage to an output terminal by means of a charge sharing occurring through channels thereof, gates and selected first terminals of the channels of said first and second transmission transistors being respectively coupled to the second electrodes of said capacitors.

Preferably, said first and second transmission transistors are alternatively turned-on and turned-off in response to the complementary signals output from said input means.

Preferably, said bias means comprise: a first bias circuit for providing the supply voltage to said first terminals of the channels of said first and second transmission transistors; and a second bias circuit for providing the supply voltage to the gates of said first and second transmission transistors.

Preferably, said first and second bias circuits in association with each other provide the output terminal with said first output voltage at the initial power-up state.

According to a further aspect of the present invention, there is provided a voltage pumping circuit being provided with a supply voltage, and an oscillator for generating pulses, and comprising: input means operating in response to pulses generated by said oscillator; voltage pumping means for pumping up the output of said input means to generate a pumped voltage in response to the output of said input means; and bias means for providing an output terminal of said voltage pumping means with the supply voltage.

A voltage pumping circuit as above may further comprise a detector for detecting variation of the output voltage of said voltage pumping circuit, whereby said voltage pumping circuit operates to control the pumping operation thereof in response to the detection so as to maintain the output voltage at said pumped voltage.

Preferably, said voltage pumping means comprise a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to the output signals of said input means.

A voltage pumping circuit as above may further comprise first and second diode-connected transmission transistors for providing the output voltage of said voltage pumping means to an output terminal by means of a charge sharing occurring through channels thereof, gates and selected first terminals of the channels of said first and second transmission transistors being respectively coupled to the second electrodes of said capacitors.

Preferably, said first and second diode-connected transmission transistors are alternatively turned-on and turned-off in response to the complementary signals output from said input means.

Preferably, said bias means provide the first terminal of the channel of said first and second diode-connected transmission transistors with the supply voltage.

According to another aspect of the present invention, there is provided a voltage pumping circuit in a semiconductor memory device having an oscillator for generating pulses, the circuit comprising: input means operating in response to pulses output from said oscillator; driver means for amplifying the output signals of said input means; voltage pumping means comprising a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to the output signals of said driver means; bias means for forcing at an initial power-up state the output voltage of said voltage pumping means to the supply voltage level; and transmission means coupled to the output of said voltage pumping means, for generating a pumped voltage.

A voltage pumping circuit as above may further comprise a detector for detecting variation of the output of said voltage pumping circuit, whereby said voltage pumping circuit operates to control the pumping operation thereof in response to the detection so as to maintain the output voltage at said pumped voltage.

According to a further aspect of the present invention, there is provided a voltage pumping circuit for a semiconductor memory device, the circuit having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied, and comprising: input means for receiving an enable signal input; voltage pumping means for generating said pumped voltage in response to the output of said input means; and output means for supplying the pumped voltage of said voltage pumping means; whereby if said pumped voltage decreases during an active operation mode of the semiconductor memory device such as an enable mode or a test mode of the semiconductor memory device, said pumped voltage is compensated by the lowered voltage.

A voltage pumping circuit as above may further comprise precharge means for precharging the output of said voltage pumping means to the supply voltage during disable of the voltage pumping circuit, so as to increase voltage pumping efficiency of said voltage pumping means.

Preferably, said voltage pumping circuit is enabled only for the active operation mode of the semiconductor memory device.

Preferably, said voltage pumping means comprise at least one voltage pumping capacitor responsive to the output of said input means.

Preferably, said precharge means comprise: at least one voltage pumping capacitor responsive to the output of said input means; and a plurality of pull-up transistors coupled between the voltage pumping capacitor and the pumped voltage output; whereby an initial output voltage of said voltage pumping means is precharged to the supply voltage through the pull-up transistors during a nonactive operation mode of the semiconductor memory device.

Preferably, said enable signal is a signal generated in association with row or column address strobe signals, or a signal generated upon a power-up of the semiconductor memory device.

According to another aspect of the present invention, there is provided a voltage pumping circuit for a semiconductor memory device, the circuit having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied, and comprising: input means for receiving an enable signal input; voltage pumping means for generating said pumped voltage in response to the output of said input means; precharge means coupled to the output of said input means, for precharging the output of said voltage pumping means to the supply voltage during a non-active operation mode of the semiconductor memory device; output means for supplying the pumped voltage of said voltage pumping means during an active operation mode of the semiconductor memory device; and output control means for controlling operation of said output means in response to the output of said input means.

Preferably, said voltage pumping means comprise: a driver circuit coupled to the output of said input means; and a first voltage pumping capacitor having first and second electrodes, the first electrode being coupled to the output of said driver circuit.

Preferably, said precharge means comprise: a second voltage pumping capacitor having first and second electrodes, the first electrode being coupled to the output of said input means; a first pull-up transistor with a gate connected to the supply voltage and a channel connected between the supply voltage and the second electrode of said second voltage pumping capacitor; a second pull-up transistor with a gate connected to the output of said voltage pumping means and a channel connected between the supply voltage and the second electrode of said second voltage pumping capacitor; a third pull-up transistor with a gate connected to the supply voltage and a channel connected between the supply voltage and the output of said voltage pumping means; and a fourth pull-up transistor with a gate connected to the second electrode of said second voltage pumping capacitor and a channel connected between the supply voltage and the output of said voltage pumping means.

Preferably, said output control means comprise: a third voltage pumping capacitor having first and second electrodes, the first electrode being connected to the output of said input means, and the second electrode being connected to a control terminal of said output means; a fourth voltage pumping capacitor having first and second electrodes, the first electrode being connected to the output of said input means; a fifth pull-up transistor with a gate connected to the supply voltage and a channel connected between the supply voltage and the second electrode of said fourth voltage pumping capacitor; and a sixth pull-up transistor with a gate connected to the second electrode of said fourth voltage pumping capacitor and a channel connected between the second electrode of said third voltage pumping capacitor and the supply voltage.

Preferably, said enable signal is a signal generated in association with row or column address strobe signals, or a signal generated upon power-up of the semiconductor memory device.

According to a further aspect of the present invention, there is provided a voltage pumping circuit for a semiconductor memory device, the circuit comprising: an input node for sensing transition of an enable signal input, for compensating for a voltage drop of a pumped voltage output from the voltage pumping circuit, comprising: voltage pumping means for generating said pumped voltage in response to transition of the enable signal input at said input node; precharge means coupled to said input node, for precharging the output of said voltage pumping means to a supply voltage during a non-active operation mode of the semiconductor memory device; output means for supplying the pumped voltage of said voltage pumping means during an active operation mode of the semiconductor memory device; and output control means for controlling operation of said output means in response to the enable signal input at the input node.

According to a further aspect of the present invention, there is provided a semiconductor memory device having electrical circuitry provided with a pumped voltage higher than a supply voltage, the device comprising: a voltage pumping node coupled to the circuitry; voltage pumping means for pumping up a voltage for a power-up cycle of the semiconductor memory device, to generate the pumped voltage; isolation means for supplying the pumped voltage to said voltage pumping node in response to the pumped voltage; active kicker means for compensating for a voltage drop of the pumped voltage in response to the signal output from the circuitry; detecting means for feeding-back a sensing signal indicative of variation of the pumped voltage to said voltage pumping means; and clamping means for receiving the sensing signal to clamp the pumped voltage to compensate for a voltage pull-up of the pumped voltage.

Preferably, said voltage pumping means comprise: an oscillator for generating a pumping clock in response to states of the supply voltage and the sensing signal; and first and second charge pumps having first and second pumping nodes, said first and second charge pumps each operating complementarily in response to the pumping clock.

Preferably, said isolation means comprise: a first isolation transistor with a gate connected to the first pumping node and a channel connected between the first pumping node and the voltage pumping node; and a second isolation transistor with a gate connected to the second pumping node and a channel connected between the second pumping node and the voltage pumping node.

A semiconductor memory device as above may further comprise precharge means for precharging the output of said first and second pumping nodes to a predetermined voltage.

A semiconductor memory device as above may further comprise means for precharging a voltage at the voltage pumping node to a predetermined voltage.

Preferably, said active kicker means comprise: a logic combination circuit for receiving signals from the circuitry; a kicking node; a pre-kicker for setting a voltage at the kicking node to a first level when the output of the logic combination circuit is at a first state; a kicking driver converting the voltage at the kicking node from said first level to a second level when the output of the logic combination circuit is at a second state; and a third isolation transistor with a channel connected between the kicking node and the voltage pumping node, said third isolation transistor operating in response to the voltage at the kicking node.

Preferably, said clamping means comprise a DC current path controllable by the sensing signal, disposed in series between the pumped voltage and the supply voltage.

Preferably, said clamping means comprise a DC current path disposed in series between the pumped voltage and the supply voltage.

According to another aspect of the present invention, there is provided a voltage pumping circuit including voltage pumping means for supplying a pumped voltage to electrical circuitry and comprising: first switching means connected between said voltage pumping means and the electrical circuitry, for supplying the pumped voltage to the electrical circuitry in response to the pumped voltage; and second switching means comprising voltage kicking means, connected between input and output terminals of the electrical circuitry, for supplying a kicked voltage output from the voltage kicking means to the electrical circuitry in response to the output of the electrical circuitry.

Preferably, said first switching means comprise an insulated gate field effect MOS transistor with a gate connected to the pumped voltage and a channel connected between the pumped voltage and the electrical circuitry.

Preferably, said second switching means comprise an insulated gate field effect MOS transistor with a gate connected to the kicked voltage and a channel connected between the kicked voltage and the pumped voltage.

According to a further aspect of the present invention, there is provided a semiconductor memory device including: a plurality of memory cells; a plurality of word lines coupled to the memory cells; a plurality of bit lines in pairs coupled to the memory cells; a plurality of input/output lines coupled to the bit lines; a plurality of sense amplifiers coupled to the bit line pairs, for amplifying a voltage difference between the bit lines in each pair; a plurality of isolation gates coupled between the bit lines and the input/output lines; and a plurality of word line drivers for selecting the word lines: said semiconductor memory device further comprising: a voltage pumping node coupled to electrical circuitry to which a pumped voltage is provided; a voltage pumping circuit for generating the pumped voltage for a power-up cycle of the semiconductor memory device; isolation means for supplying the pumped voltage to said voltage pumping node in response to the pumped voltage; active kicker means for compensating for a voltage drop of the pumped voltage in response to the signal output from the electrical circuitry; detecting means for feeding-back a sensing signal indicative of variation of the pumped voltage to said voltage pumping means; and clamping means for receiving the sensing signal to clamp the pumped voltage by compensating for a voltage pull-up of the pumped voltage.

Preferably, said voltage pumping means comprise: an oscillator for generating a pumping clock in response to states of a supply voltage and the sensing signal; and first and second charge pumps having first and second pumping nodes, said first and second charge pumps each operating complementarily in response to the pumping clock.

A semiconductor memory device as above may further comprise means for precharging a voltage at the first and second pumping nodes to a predetermined voltage.

Preferably, said clamping means comprise: a first clamping circuit for supplying a first voltage to the voltage pumping node if the supply voltage is identical to the first voltage; and a second clamping circuit for supplying a second voltage higher than the first voltage to the voltage pumping node if the supply voltage is identical to the second voltage.

The invention extends to a semiconductor memory device provided with a voltage pumping circuit according to any of the preceding aspects of the invention.

For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying diagrammatic drawings, in which: Figure 2 is a block diagram illustrating an embodiment of a voltage pumping circuit according to the present invention; Figure 3A is a circuit diagram showing a specific embodiment of the circuit of Figure 2; Figure 3B is a timing diagram showing an example of operation of the circuit as shown in Figure 3A; Figure 3C is a circuit showing another specific embodiment of the circuit Figure 2; Figure 4 is a block diagram illustrating a second embodiment of a voltage pumping circuit according to the present invention; Figure 5A is a circuit showing a specific embodiment of the circuit of Figure 4; Figure 5B is a timing diagram showing an example of operation of the circuit as shown in Figure SA; Figure SC is a circuit showing another specific embodiment of the circuit Figure 4; Figure 5D is a circuit showing a further specific embodiment of the circuit of Figure 4; Figure 6 is a block diagram illustrating a third embodiment of a voltage pumping circuit according to the present invention; Figure 7A is a circuit showing a structural embodiment of the pumping circuit of Figure 6; Figure 7B is a circuit showing a specific embodiment of the pumping circuit of Figure 7A; Figure 7C is a circuit showing a specific embodiment of an active kicker of the circuit of Figure 6; Figure 7D is a timing diagram illustrating an example of operation of the active kicker of Figure 7C; Figure 7E is a circuit showing an embodiment of a detector of Figure 6; Figure 7F to 7H are circuits showing an embodiment of a clamper of Figure 6; and Figure 8 is a timing diagram illustrating an example of operation of the circuit of Figure 6.

There will now be described three examples for applying principles according to the present invention, but it will be readily appreciated by those skilled in the art that further examples or embodiments of the present invention may be obtained without departing from the gist of the present invention.

EXAMPLE 1 Referring to Figure 2, an oscillator control clock signal is generated simultaneously with powering a chip in order to drive an oscillator 100 when a detector (not shown) detects that voltage Vpp is not at a given level. The oscillator 100 generates a pulse signal whose voltage is amplified through a driver circuit 200. The amplified pulse signal is transferred to a voltage pumping circuit 300 to produce a given raised voltage Vpp. A bias circuit 400 precharges the output terminal of the voltage pumping circuit 300 with the level of a source voltage Vcc simultaneously with powering the chip. The driver circuit 200 is to improve the efficiency of the generation and voltage raising of the voltage Vpp.

A preferred embodiment of the circuit of Figure 2 is shown in Figure 3A. Input circuit 1115 comprises a NOR-gate 13 and NAND-gate 14. The output signal of the input circuit is voltage-amplified through a driver circuit 2128. The output signals of the driver circuit are connected to the capacitors C1, C2, C3, C4 of a voltage raising circuit. The capacitors C2 and C3 are respectively connected to the channels of first and second transfer transistors M1 and M2. The electrodes of the capacitors C2 and C3 facing towards the channels of the transfer transistors M1 and M2 are supplied with the source voltage Vcc from a first bias circuit 3134. The gates of the first and second transfer transistors M1 and M2 are supplied with the source voltage Vcc from a second bias circuit 3538.

The operation of the circuit of Figure 3A is now specifically described with reference to Figure 3B. It should be noted that the voltage Vpp is continuously pumped regardless of the output phase of the oscillator being "high" or "low". In addition, the inverters 25, 26 and capacitor C1 disposed between the output terminal of the NOR-gate 13 and the gate of the first transfer transistor M1, the inverters 27, 28 and capacitor C4 between the inverter 15 connected to the output terminal of the NAND-gate 14 and the gate of the second transfer transistor M2, and the second bias circuit 3538 are to maximize the efficiency of the voltage pumping circuit. When the chip is powered up, the nodes N1 and N2 are initialized or precharged with the source voltage level (Vcc: precisely speaking, this will be Vcc-Vth level, but may be accomplished at Vcc level by replacing the components of the first bias circuit 3134 with P-type MOS transistors). If the oscillator works as shown in Figure 3B, the nodes N1 and N2 have opposite phases triggered from Vcc level to 2Vcc level (this is accomplished by the coupling effect of the capacitors C2 and C3). The nodes N3 and N4 are also triggered from Vcc level to 2Vcc level by the coupling effect of the capacitors C1 and C4. Accordingly the voltage Vpp is gradually raised from the initial Vcc level to 2Vcc level by the charge sharing through the first and second transfer transistors M1 and M2, as shown in Figure 3B. In this case, since the NOR-gate 13 and inverter 15 have opposite output phases, the turning-on operations of the first and second transfer transistors M1 and M2 are oppositely performed, continuously pumping the voltage Vpp to 2Vcc level. In addition, since the gates of the first and second transfer transistors M1 and M2 are continuously supplied with the voltage Vcc by the second bias circuit 3538, the channels of the first and second transfer transistors M1 and M2 are fully turned on when the node N1 or N2 is at 2Vcc level, thus further improving the pumping efficiency of the voltage Vpp. Further the voltage Vpp is generated at a given level, i.e. 2Vcc before enabling of the chip, thereby achieving high speed operation of the chip. In the case of the circuit as shown in Figure 3A, a high raised voltage is obtained even at a considerably low operating source voltage Vcc of the chip, so that the Vpp voltage has a value of 4.5V or more with a Vcc voltage of 3V.

The circuit of Figure 3C is similar to the circuit of Figure 3A except that the first and second transfer transistors M10 and M20 are diodeconnected. Comparing Figure 3C with Figure 3A, there are eliminated the inverters 25, 26 and capacitor C1 connected to the gate of the first transfer transistor M1, the inverters 27, 28 and capacitor C4 connected to the gate of the second transfer transistor M2, and the second bias circuit 3538. The operational characteristics of Figure 3C are similar to Figure 3A. The voltage of the node N10 or N20 is raised to 2Vcc level to turn on the first or second transfer transistor M10 or M20, thus raising the Vpp voltage to a given level.

The circuit of Figure 3C is so simple as to be suitably used in a chip of high complexity. The technical concept as shown in Figure 2 may be realized in a variety of embodiments in addition to the circuits of Figures 3A and 3C.

For example, the input circuit may take any form provided it should make logically different responses to the output waveform of the oscillator, and the first and second bias circuits may also take any form provided they supply Vcc (or Vcc-Vth) voltage.

EXAMPLE 2 Referring to Figure 4, an enable signal is applied to a source voltage precharge circuit 50 and the control circuit 70 of an output circuit M. The Vpp signal is transferred from the channel of the output circuit M to the output terminal of the voltage pumping circuit (i.e. Vpp voltage generator) provided on a chip. The source voltage precharge circuit 50, which is to improve the efficiency of the voltage pumping circuit 60, causes the voltage pumping circuit 60 to pump the output voltage to a given level, and initially precharges the voltage pumping circuit 60 with the source voltage Vcc when the circuit of Figure 4 is disabled. The control circuit 70 controls the output circuit M to perform an output operation only when the raised voltage Vpp applied to the chip is dropped. The output circuit also serves to prevent the raised voltage Vpp (i.e. the voltage generated by the voltage pumping circuit provided in the chip) from flowing in reverse into the voltage pumping circuit when the circuit of Figure 4 is disabled. In this example, the output circuit M consists of an N-type MOS transistor, but may take any other form to transfer the raised voltage Vpp.

There are shown specific embodiments of the circuit of Figure 4 in Figures SA, SC and SD. The circuits of Figures SA, 5C and SD have different input circuits according to the kind of the enable signal or the operational mode of the chip. Namely, the active operation of the chip has a variety of modes such as data read/write, chip test, etc., and accordingly the enable signal is set variously. Hence, the circuits of Figures 5A, 5C and SD are to compensate for the voltage drop occurring in each active operation.

The circuit of Figure 5A comprises an input circuit 10A for supplying an enable signal, source voltage precharge circuit 50 connected to receive the output signal of the input circuit 10A, voltage pumping circuit 60 connected to receive the output signal of the input circuit 10A for raising the output signal voltage of the source voltage precharge circuit 60, output circuit M7 for transferring the raised voltage of the voltage pumping circuit 60, and output control circuit 70 for controlling the operation of the output circuit M7. The inverters 61, 62,...,66 are suitably used for effective connection of the circuit elements. The input circuit 10A consists of a NAND-gate 71 with two inputs respectively receiving two enable signals PTRST and PRD, NOR-gate 74 with one input receiving the enable signal PRD via an inverter 73 and other input receiving the output signal of the NAND-gate 71 via an inverter 72, and inverter 75 connected to the output of the NOR-gate 74.

The source voltage precharge circuit 60 comprises a first voltage pumping capacitor C1, first pull-up transistor M1, second pull-up transistor M2, third pull-up transistor M4 and fourth pull-up transistor M3. One electrode of the capacitor C1 is connected to receive the output signal of the input circuit 10A via inverters 61, 62, 63. The first pull-up transistor M1 has a gate connected with the source voltage Vcc and a channel between the source voltage and the other electrode of the first capacitor C1. The second pull-up transistor M2 has a gate connected with an output node N6 and a channel between the source voltage and the other electrode of the first capacitor C1. The third pull-up transistor M4 has a gate connected with the voltage source Vcc and a channel between the voltage source and output node N6. The fourth pull-up transistor M3 has a gate connected with the other electrode of the first capacitor C1 and a channel between the voltage source and output node N6.

The voltage pumping circuit 60 consists of a second voltage pumping capacitor C2 with one input connected to receive the output signal of the input circuit 10A via inverters 64, 65 and driver circuit 77, 78 for improving the voltage pumping efficiency. The output control circuit 60 consists of a third pumping capacitor C3 with one electrode connected to receive the output signal of the input circuit 10A via inverters 64, 65, fourth pumping capacitor C4 with one electrode connected to receive the output signal of the input circuit 10A via an inverter 66, fifth pull-up transistor M5 with a gate connected to the source voltage Vcc and a channel between the source voltage and the other electrode of the fourth capacitor C4, and sixth pull-up transistor M6 with a gate connected to the other electrode of the fourth capacitor C4.

A channel of the sixth pull-up transistor M6 has one end connected with the source voltage and the other end connected commonly with the other electrode of the third capacitor C3 and the control terminal of the output circuit M7.

The output node N6 of the voltage pumping circuit 60 transfers the raised voltage Vpp and is fed back to the control terminal of the second pull-up transistor M2. The enable signals PTRST and PRD perform transition respectively when the column and row address signals are produced as active signals.

The operational characteristics of the circuit of Figure 5A are described with reference to the timing diagram of Figure 5B. The enable signals PTRST and PRD are produced in "low" state as shown in Figure SB when they do not perform a transition (or the chip is not in active operation). The timing diagram of Figure 5B represents the operations after the circuit of Figure 5A is activated. When the circuit of Figure SA is disabled, the nodes N6 and N4 are all precharged with the source voltage Vcc. The node N1 for receiving the output signal of the input circuit 10A is precharged with ground voltage, the node N5 of the source voltage precharge circuit 50 with 2Vcc, and the output node N6 of the voltage pumping circuit 60 with the source voltage. The node N4 is precharged with Vcc connected to the control terminal of the output circuit M7 which is disabled. Thereafter the chip is activated, while the node N5 of the source voltage precharge circuit 50 is precharged with the source voltage and the output node N6 of the voltage pumping circuit 60 with 2Vcc.

The node N3 of the output control circuit 60 is precharged with Vcc and the node N4 with 2Vcc applied to the control terminal of the output circuit M7.

When the enable signal PRD is firstly raised to "high" level (the enable signal PRD is produced delayed after a row address strobe signal (RAS) is produced as an active signal), the voltage level of the node N1 is changed to "low", and accordingly the node N5 to 2Vcc and the nodes N6 and N4 to Vcc.

In this case, the node N6 is at full-Vcc voltage level supplied through the third pull-up transistor M3 which is fully turned on by the node N5 at 2Vcc voltage level, so that it is pumped fully to 2Vcc level when the node N1 performs transition to "high" level. Meanwhile, the output circuit M7 is turned off, which indicates that the chip is activated to apply the Vpp voltage to the components of the chip (i.e. components such as word line driver, data output driver, etc.). Then if the enable signal PTRST transits to "high" level (in this case, the enable signal PRD keeps "high" level), the node N1 takes "high" level causing the nodes N5, N6, N4 respectively to have Vcc, 2Vcc and 2Vcc.

The Vpp voltage is used as the operating voltage of the chip, thus suffering a voltage drop. At this time, the output circuit M7, whose control terminal is applied with 2Vcc and channel is charged with 2Vcc at one end, is turned on to quickly compensate for the voltage drop of the Vpp voltage. Thus the components of the chip using Vpp as the operating voltage keep stable operations, and the operational speed is not slowed down. Then if the enable signal PTRST becomes "low", the node N1 again takes "low" level, causing the node NS to have 2Vcc level and the nodes N6 and N4 to have Vcc level, so that the Vpp voltage is prevented from flowing in reverse through the output circuit M7. Further, if the enable signal PRD becomes low, each component is precharged with the initial value and thereafter the dropping of the Vpp voltage is properly compensated. In Figure SB, the interval Q in which the Vpp voltage is substantially compensated may be properly adjusted according to the characteristics of the chip by controlling the time of the enabling signal or providing the voltage pumping circuit with a delay circuit.

The circuit of Figure 5C is similar to that of Figure SA except for the enable signals input to the input circuit 10B and the construction of the logic gate thereof. The enable signal PXIE is to control the raised voltage Vpp of the voltage pumping circuit to be applied to a given word line, and the enable signal PDPX is produced when the RAS performs transition or a given address is decoded performing transition. The input circuit 10B consists of a first NAND-gate 81 and NOR-gate 82 each with two inputs respectively receiving the two enable signals PXIE and PDPX and a second NAND-gate 84 for receiving the output of the NOR-gate 82 via an inverter 83. The node N1 for receiving the output signal of the input circuit 10B is precharged with "high" level as in the case of Figure SA, and the other circuits also work as in the circuit of Figure 5A. The enable signals PXIE and PDPX are clock signals widely applied to a variety of the operational modes of a dynamic RAM.

The circuit of Figure SD has an additional enable signal PFTE of the input circuit 10C, as compared to the circuit of Figure SC. Hence the NANDgate 88 for receiving the enable signal PFTE has three inputs and one output.

The enable signal PFTE is enabled when a memory chip performs a test mode.

The circuit of Figure SD also works in the same manner as that of Figure SC, and the node N1 is precharged with "high" level.

The circuits of Figures SA, Sc and SD have different uses according to the operational modes of the chip and therefore may all be provided on a chip.

Of course, various modifications to the circuits may be made without departing the spirit of the present invention.

EXAMPLE 3 The voltage pumping means of Figure 6 comprises a pumping circuit 500 for producing a raised voltage Vpp, active kicker 600 for compensating for the dropping of the raised voltage Vpp, detector 700 for detecting the level of the raised voltage Vpp, and first and second clamper 800 and 900 for preventing the raised voltage Vpp from being raised over a given level.

The pumping circuit 500 comprises, as shown in Figure 7A, an oscillator 110 for generating pumping clock pulses 4 > PP in response to the level detection signal 4 > DET of the detector 700, charge pump 130 for producing the raised voltage Vpp in response to the pumping clock pulses 4)PP, first precharge circuit 160 for precharging the pumping node of the output of the charge pump 130 with Vcc before pumping operation, isolation transistors 141, 142 for transferring the voltage of the pumping node to the Vpp node 180, and second precharge circuit 170 for precharging the gates of the isolation transistors 141, 142 with Vcc before pumping operation.

Referring to Figure 7B for specifically illustrating the circuit of Figure 7A, the charge pump 130 comprises a first charge pump circuit 130a driven at "high" state of the pumping clock pulses 4)PUP and second charge pump circuit 130b driven at "low" state of the pumping clock pulses PP. The first precharge circuit 160 consists of two transmission gates 161 and 162 connected in latch configuration between the source voltage Vcc and the first and second pumping nodes 165 and 166. Likewise the second precharge circuit 170 consists of two transmission gates 171 and 172 performing latching operation to provide the gates of the isolation transistors 141 and 142 with the source voltage Vcc. The isolation transistors 141 and 142 which consist of NMOS transistors in the present embodiment transfer the voltages of the first and second pumping nodes 165 and 166 to the Vpp node 180. The first and second precharge circuits 160 and 170 work to simultaneously raise the voltages of the pumping nodes 165 and 166 and the gates of the isolation transistors 141 and 142 from the Vce level. The pumping clock pulses 4XPP are adjusted in pulse width by means of inverters 113, 114 and changed by NAND gate 115 to first pumping clock pulses bPPa supplied to the first and second pumping MOS capacitors 131 and 132 of the first charge pump circuit 130a which are respectively connected with the gate and drain of the first isolation transistor 141. Further the pumping clock pulses Q > PP are adjusted in pulse width by means of the inverters 113, 114 and changed by NANDgate 116 to second pumping clock pulses 4 > PPb supplied via inverter 135 to third and fourth MOS capacitors of the second charge pump circuit 130b which are respectively connected with the drain and gate of the second isolation transistor 142. Thus, in the case of the pumping clock pulses 4 > PP being low, the first and second pumping MOS capacitors 131 and 132 work to charge the Vpp node 180 with 2Vcc, while in the case of the pumping clock pulses PP being high the third and fourth pumping MOS capacitors 133 and 134 work to raise further the voltage level of the Vpp node 180 that has been already charged with 2Vcc by means of the first charge pump circuit 130a.

The pumping circuit 500 supplies the raised voltage Vpp through the first and second isolation transistors 141 and 142 to the word line driver or bit line separation gate, and therefore does not require a separate capacitor as in the conventional circuit as shown in Figure 1. Moreover the raised voltage Vpp is supplied, already prepared, to the separation gate of a bit line, so that the N-type and P-type sense amplifiers may be commonly employed and there is no need to provide an additional circuit for raising the voltage applied to the separation gate as in the conventional circuit. This contributes to the reduction of the chip size. If the level of the source voltage Vcc applied to the NAND-gate to drive the oscillator is not raised over a given value (i.e. it is not in the operating state), the pumping circuit 500 does not work and therefore the operating and standby current of the chip is not substantially increased, thus reducing the power consumption needed for pumping.

The active kicker 600 is to compensate for the dropping of the raised voltage Vpp that is caused by the raised voltage Vpp of the pumping circuit 500 being repeatedly supplied to the word line driver or separation gate (the gate of the transistor for transferring data between data lines). As shown in Figure 7C, the active kicker 600 comprises an exclusive OR (XOR) circuit 210 for receiving the clock pulses Pxie, Pdpx and source voltage Vcc, pre-kicker 220 operated at the output of the XOR circuit 210 being "low", and kicking driver 230 operated at the output of the XOR circuit 210 being "high". The signals Pxie and Pdpx are used to drive selected word lines of a memory array.

In the pre-kicker 220, the output of the XOR circuit 210 is supplied to the first node 201 which in turn is connected with the second node 202 via three cascaded inverters 221, 222, 223 and a kicking capacitor 224. Between the second and third nodes 202 and 203 there are arranged two NMOS transistors 226 and 227 with their gates cross-coupled and their drains connected to the source voltage. The two transistors are to precharge the third node 203 with full Vcc by employing the voltage of the second node 202.

Between the first and third nodes 201 and 203 there are connected in series four inverters 231, 232, 233, 234 and second kicking capacitor 235. The first node 201 is connected with the fourth node 204 via inverter 239 and third kicking capacitor 241. The fourth node 204 is charged with Vcc-Vth level by means of the NMOS transistor 238 connected to the source voltage Vcc. Also the fourth node 204 is connected with the gate of a precharge NMOS transistor 237 with the drain connected to the source voltage. The source of the NMOS transistor 237 is connected with the fifth node 205. Between the inverter 232 and fifth node 205 is connected fourth kicking capacitor 236. The Vpp node 180 is connected with the source of the third isolation transistor 240 whose gate and drain are respectively connected to the fifth and third nodes 205 and 203.

Referring to Figure 7D based on Figure 7C, when the first node 201 connected with the output of the XOR circuit 210 is in "low" state, the three inverters 221, 222, 223 and first kicking capacitor 224 connected in series with the first node 201 work to raise voltage level of the second node 202 from Vcc-Vth (precharged by means of the NMOS transistor 225) to 2Vcc-Vth.

This causes the NMOS transistors 226 and 227 to charge the third node 203 with full Vcc level. Since the voltage level of the fourth node 204 is raised from Vcc-Vth to 2Vcc-Vth during the first node 201 being in "low" state, the fifth node 205 is charged with full Vcc level via the NMOS transistor 237.

Thereafter, when the voltage level of the first node 201 becomes "high", the voltage level of the third node 203 is raised from Vcc level to 2Vcc level by the operation of the fourth kicking capacitor 236. Likewise the fourth kicking capacitor 236 works to raise the voltage level of the fifth node 205 from Vcc level to 2Vcc level. Thus the isolation transistor 240 supplies 2Vcc to the Vpp node 180. In this active kicker 200, the source voltage Vcc is one input to the XOR circuit 210 and therefore will not drive the circuit below a given level as in the pumping circuit 500. In addition, since the signals Pxie and Pdpx are produced from the circuit using the raised voltage Vpp (e.g. the word line driver), the dropping of the raised voltage Vpp may be compensated by means of the above procedure. The number of the active kickers is proportional to that of the circuits using the raised voltage Vpp.

Referring to Figure 7E, the raised voltage Vpp is applied to the gate of NMOS transistor 310 and its level is detected. Hence, the threshold voltage of the NMOS transistor 310 connected between the source voltage and detection node 301 should be set to the value that turns on or off the transistor according to the gate voltage being over or below 2Vcc, assuming the raised voltage Vpp is 2Vcc. Methods for setting the threshold voltage of the NMOS transistor are well-known in this art and therefore not described. Between the detection node 301 and ground voltage Vss is arranged an NMOS transistor 320 with a gate connected to a reference voltage Vref. Assuming that a constant resistance between the detection node 301 and ground voltage Vss

Referring to Figure 7F, there are shown first and second dampers 800 and 900 for preventing the voltage Vpp from being raised to an undesirable level. These serve to pull the excessively raised voltage Vpp down to the source voltage Vcc in order to prevent destruction of the components when the level of the raised voltage Vpp exceeds a given value. Namely, as shown in Figure 7F, when the level of the raised voltage Vpp increases, the detector 700 produces a clamp signal 4 > CLMP of low state applied to the gate of the PMOS transistor 410, so that the excessively raised voltage Vpp is discharged via the channels of the cascaded NMOS transistors 420, 430 and PMOS transistor 410 to the source voltage terminal. In this case, the raised voltage Vpp is dropped through the NMOS transistor 430 by about Vcc+Vth. The circuit of Figure 7G uses the cascaded NMOS transistors 510, 520 and PMOS transistor 530 to discharge the raised voltage Vpp without using the signal bCLMP as in Figure 7F. Of course, the raised voltage Vpp is dropped through the NMOS transistor 520 by Vcc+Vth. The pull-down level of the raised voltage is determined by the number (n) of the NMOS transistors cascaded between the Vpp terminal and Vcc terminal to contribute to the voltage dropping. The circuits of Figures 7F and 7G show the case of n=1. If there are used n cascaded NMOS transistors to contribute to the voltage dropping, the raised voltage Vpp will be dropped by Vcc+Vth.

In Figure 7H, the clamper 800 includes two clamper circuits arranged between the Vcc and Vpp terminals. The clamper circuit 1 has the same structure as the circuit of Figure 7F and the clamper circuit 2 is similar to the circuit of Figure 7G while eliminating the PMOS transistor 530 whose gate is grounded in Figure 7G. Assuming that the threshold voltages of the NMOS transistors 420, 520, 510 are respectively Vthl, Vth2, Vth3 (in this case, the relationship between the threshold voltages is assumed Vthl < Vth2 + Vth3), the clamper circuit 1 works in the same manner as the circuit of Figure 7F.

In the clamper circuit 2, if the voltage level of the node C has the value of Vcc+Vth2, the NMOS transistor 520 is turned on, and if the voltage level of the Vpp terminal has the value of Vcc+Vth2+Vth3 or more, the NMOS transistor 510 is turned on, so that a current path is formed between the Vcc and Vpp terminals to discharge the voltage. Thus, in Figure 7H, until the voltage level of the Vcc terminal comes to be within the range of Vcc+Vth2 to Vcc+Vth2+Vth3, the clamper circuit 1 uses the clamp signal 4?CLUMP to adjust the voltage level of the Vpp terminal as desired, and the voltage level of the Vpp terminal exceeding the value of Vcc+Vth2+Vth3, the clamper circuit 2 turns on the NMOS transistors 520 and 510 to discharge the voltage to the Vpp terminal. Hence, the voltage level of the Vpp terminal may be adjusted to have any value between Vcc+Vth2+Vth3 and Vcc+Vthl.

Hereinafter, the operation of the above circuit is described with reference to Figure 8, where arrow lines show the relationship between signals.

Before supplying the source voltage Vcc (low state), the output of the inverter 112 of the pumping circuit 500 is low and therefore the pumping clock pulses PP are kept "high". Supplying the source voltage, the first and second pumping nodes 165 and 166 and the gates of the first and second isolation transistors 141 and 142 are precharged with the source voltage Vcc by means of the first and second precharge circuits 160 170. This in turn precharges the Vpp node 180 with Vcc-Vth. The oscillator periodically produces the pumping clock pulses PP. Then the first and second pumping clock pulses PPa and 4 > PPb that complementarily work in response to the pumping clock pulses Q > PP cause the first and second pumping nodes 165 and 166 and the gates of the first and second isolation transistors 141 and 142 to have the voltage level of 2Vcc. Consequently the voltage of the Vpp node 180 is raised to 2Vcc. This raised voltage Vpp of 2Vcc is dropped due to charge sharing when supplied to the word lines, separation gates, etc. (see 801 and 802 in Figure 8). In order to compensate for this voltage dropping, there is used the active kicker 200 of Figure 5, whose operation has been described with reference to Figure 5B. Meanwhile, if the raised voltage Vpp is excessively raised owing to excessive pumping, the clamp signal CLMP becomes low in Figure 7E. This causes the level of the raised voltage Vpp to be dropped by Vcc+Vth (see 803 in Figure 8). When the clamp signal CLMP is low, the detection signal DET is also low. This causes the pumping clock pulses 4 > PP to be kept high as in the initial disabled state.

Thus the pumping circuit 500 no longer performs the pumping operation, so that the level of the raised voltage Vpp may be excessively dropped (see 804 in Figure 8). However, in this case, the detection signal 4 > DET is made high to restart the pumping operation.

As described above, the active kicker 600 compensates for the dropping of the raised voltage Vpp, the detector 700 keeps the present Vpp level stable, and the dampers 800 and 900 prevent the raised voltage Vpp from being excessively raised. Furthermore, the pumping circuit 500 of Figure 7B and the active kicker 600 of Figure 7C are used to supply the raised voltage to the bit line isolation transistors without using capacitors as in the conventional circuit of Figure 1C, so that the N-channel and P-channel sense amplifiers may be commonly used, thus reducing the chip size. In addition, the pumping circuit 500 works only with receiving the source voltage Vcc, thereby reducing the power consumption of the chip.

Various modifications and embodiments of the circuits described above with reference to the attached drawings may be obtained without departing from the scope of the inventive concept.

Thus, embodiments of the present invention may provide a voltage pumping circuit used in a semiconductor memory device of high complexity, whereby the source voltage may be raised and maintained to be suitably adapted to the components of the device.

The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

1. A semiconductor memory device arranged to be powered by a supply voltage, and comprising an oscillator for generating pulses, and a voltage pumping circuit for generating at an initial power-up state a first output voltage which is substantially identical to said supply voltage, and pumping an output voltage up to a second output voltage prior to or upon the semiconductor memory device being enabled in response to pulses output from said oscillator, said second output voltage being higher than said first output voltage.

2. A semiconductor memory device as claimed in claim 1, further comprising a detector for detecting variation of the output of said voltage pumping circuit, whereby said voltage pumping circuit operates to control the pumping operation thereof in response to the detection so as to maintain the output at said second output voltage.

3. A semiconductor memory device as claimed in claim 1 or 2, wherein said voltage pumping circuit comprises: input means operating in response to the pulses output from said oscillator; voltage pumping means for generating said second output voltage in response to the output of said input means; and bias means for forcing at the initial power-up state the output of said voltage pumping circuit into said first output voltage.

4. A semiconductor memory device as claimed in claim 3, wherein said input means receive the pulses output from said oscillator to generate a pair of complementary signals.

5. A semiconductor memory device as claimed in claim 3 or 4, further comprising driving means for amplifying the output signals of said input means.

6. A semiconductor memory device as claimed in claim 5, wherein said voltage pumping means comprise a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to the output signals of said driving means.

7. A semiconductor memory device as claimed in any of the preceding claims, further comprising first and second transmission transistors for providing said second output voltage to an output terminal by means of a charge sharing occurring through channels thereof, gates and selected first terminals of the channels of said first and second transmission transistors being respectively coupled to the second electrodes of said capacitors.

8. A semiconductor memory device as claimed in claims 4 and 7, wherein said first and second transmission transistors are alternatively turned-on and turned-off in response to the complementary signals output from said input means.

9. A semiconductor memory device as claimed in claim 8 or claims 3 and 7, wherein said bias means comprise: a first bias circuit for providing the supply voltage to said first terminals of the channels of said first and second transmission transistors; and a second bias circuit for providing the supply voltage to the gates of said first and second transmission transistors.

10. A semiconductor memory device as claimed in claim 9, wherein said first and second bias circuits in association with each other provide the output terminal with said first output voltage at the initial power-up state.

11. A voltage pumping circuit being provided with a supply voltage, and an oscillator for generating pulses, and comprising: input means operating in responsive to pulses generated by said oscillator; voltage pumping means for pumping up the output of said input means to generate a pumped voltage in response to the output of said input means; and bias means for providing an output terminal of said voltage pumping means with the supply voltage.

12. A voltage pumping circuit as claimed in claim 11, further comprising a detector for detecting variation of the output voltage of said voltage pumping circuit, whereby said voltage pumping circuit operates to control the pumping operation thereof in response to the detection so as to maintain the output voltage at said pumped voltage.

13. A voltage pumping circuit as claimed in claim 11 or 12, wherein said input means receive the pulses output from said oscillator to generate a pair of complementary signals.

14. A voltage pumping circuit as claimed in claim 11, 12 or 13, wherein said voltage pumping means comprise a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to the output signals of said input means.

15. A voltage pumping circuit as claimed in claim 14, further comprising first and second diode-connected transmission transistors for providing the output voltage of said voltage pumping means to an output terminal by means of a charge sharing occurring through channels thereof, gates and selected first terminals of the channels of said first and second transmission transistors being respectively coupled to the second electrodes of said capacitors.

16. A voltage pumping circuit as claimed in claim 13 and 15, wherein said first and second diode-connected transmission transistors are alternatively turned-on and turned-off in response to the complementary signals output from said input means.

17. Voltage pumping circuit as claimed in claim 15 or 16, wherein said bias means provide the first terminal of the channel of said first and second diodeconnected transmission transistors with the supply voltage.

18. A voltage pumping circuit in a semiconductor memory device having an oscillator for generating pulses, the circuit comprising: input means operating in response to pulses output from said oscillator; driver means for amplifying the output signals of said input means; voltage pumping means comprising a plurality of capacitors each having first and second electrodes, said first electrodes being respectively coupled to the output signals of said driver means; bias means for forcing at an initial power-up state the output voltage of said voltage pumping means to the supply voltage level; and transmission means coupled to the output of said voltage pumping means, for generating a pumped voltage.

19. A voltage pumping circuit as claimed in claim 18, wherein said input means receive the pulses output from said oscillator to generate a pair of complementary signals.

20. A voltage pumping circuit as claimed in claim 18 or 19, further comprising a detector for detecting variation of the output of said voltage pumping circuit, whereby said voltage pumping circuit operates to control the pumping operation thereof in response to the detection so as to maintain the output voltage at said pumped voltage.

21. A voltage pumping circuit for a semiconductor memory device, the circuit having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied, and comprising: input means for receiving an enable signal input; voltage pumping means for generating said pumped voltage in response to the output of said input means; and output means for supplying the pumped voltage of said voltage pumping means; whereby if said pumped voltage decreases during an active operation mode of the semiconductor memory device such as an enable mode or a test mode of the semiconductor memory device, said pumped voltage is compensated by the lowered voltage.

22. A voltage pumping circuit as claimed in claim 21, further comprising precharge means for precharging the output of said voltage pumping means to the supply voltage during disable of the voltage pumping circuit, so as to increase voltage pumping efficiency of said voltage pumping means.

23. A voltage pumping circuit as claimed in claim 21 or 22, wherein said voltage pumping circuit is enabled only for the active operation mode of the semiconductor memory device.

24. A voltage pumping circuit as claimed in claim 21, 22 or 23, wherein said voltage pumping means comprise at least one voltage pumping capacitor responsive to the output of said input means.

25. A voltage pumping circuit as claimed in claim 22 or claim 23 or 24 as appendant thereto, wherein said precharge means comprise: at least one voltage pumping capacitor responsive to the output of said input means; and a plurality of pull-up transistors coupled between the voltage pumping capacitor and the pumped voltage output; whereby an initial output voltage of said voltage pumping means is precharged to the supply voltage through the pull-up transistors during a nonactive operation mode of the semiconductor memory device.

26. A voltage pumping circuit as claimed in any of claims 21 to 25, wherein said enable signal is a signal generated in association with row or column address strobe signals, or a signal generated upon a power-up of the semiconductor memory device.

27. A voltage pumping circuit for a semiconductor memory device, the circuit having a voltage pumping node to which a pumped voltage higher than a supply voltage is applied, and comprising: input means for receiving an enable signal input; voltage pumping means for generating said pumped voltage in response to the output of said input means; precharge means coupled to the output of said input means, for precharging the output of said voltage pumping means to the supply voltage during a non-active operation mode of the semiconductor memory device; output means for supplying the pumped voltage of said voltage pumping means during an active operation mode of the semiconductor memory device; and output control means for controlling operation of said output means in response to the output of said input means.

28. A voltage pumping circuit as claimed in claim 27, wherein said voltage pumping means comprise: a driver circuit coupled to the output of said input means; and a first voltage pumping capacitor having first and second electrodes, the first electrode being coupled to the output of said driver circuit.

29. The voltage pumping circuit as claimed in claim 27 or 28, wherein said precharge means comprise: a second voltage pumping capacitor having first and second electrodes, the first electrode being coupled to the output of said input means; a first pull-up transistor with a gate connected to the supply voltage and a channel connected between the supply voltage and the second electrode of said second voltage pumping capacitor; a second pull-up transistor with a gate connected to the output of said voltage pumping means and a channel connected between the supply voltage and the second electrode of said second voltage pumping capacitor; a third pull-up transistor with a gate connected to the supply voltage and a channel connected between the supply voltage and the output of said voltage pumping means; and a fourth pull-up transistor with a gate connected to the second electrode of said second voltage pumping capacitor and a channel connected between the supply voltage and the output of said voltage pumping means.

30. A voltage pumping circuit as claimed in claim 27, 28 or 29, wherein said output control means comprise: a third voltage pumping capacitor having first and second electrodes, the first electrode being connected to the output of said input means, and the second electrode being connected to a control terminal of said output means; a fourth voltage pumping capacitor having first and second electrodes, the first electrode being connected to the output of said input means; a fifth pull-up transistor with a gate connected to the supply voltage and a channel connected between the supply voltage and the second electrode of said fourth voltage pumping capacitor; and a sixth pull-up transistor with a gate connected to the second electrode of said fourth voltage pumping capacitor and a channel connected between the second electrode of said third voltage pumping capacitor and the supply voltage.

31. A voltage pumping circuit as claimed in any of claims 27 to 30, wherein said enable signal is a signal generated in association with row or column address strobe signals, or a signal generated upon power-up of the semiconductor memory device.

32. A voltage pumping circuit for a semiconductor memory device, the circuit comprising: an input node for sensing transition of an enable signal input, for compensating for a voltage drop of a pumped voltage output from the voltage pumping circuit, comprising: voltage pumping means for generating said pumped voltage in response to transition of the enable signal input at said input node; precharge means coupled to said input node, for precharging the output of said voltage pumping means to a supply voltage during a non-active operation mode of the semiconductor memory device; output means for supplying the pumped voltage of said voltage pumping means during an active operation mode of the semiconductor memory device; and output control means for controlling operation of said output means in response to the enable signal input at the input node.

33. A voltage pumping circuit as claimed in claim 32, wherein said enable signal is a signal generated in association with row or column address strobe signals, or a signal generated upon a power-up of the semiconductor memory device.

34. A semiconductor memory device having electrical circuitry provided with a pumped voltage higher than a supply voltage, the device comprising: a voltage pumping node coupled to the circuitry; voltage pumping means for pumping up a voltage for a power-up cycle of the semiconductor memory device, to generate the pumped voltage; isolation means for supplying the pumped voltage to said voltage pumping node in response to the pumped voltage; active kicker means for compensating for a voltage drop of the pumped voltage in response to the signal output from the circuitry; detecting means for feeding-back a sensing signal indicative of variation of the pumped voltage to said voltage pumping means; and clamping means for receiving the sensing signal to clamp the pumped voltage to compensate for a voltage pull-up of the pumped voltage.

35. A semiconductor memory device as claimed in claim 34, wherein said voltage pumping means comprise: an oscillator for generating a pumping clock in response to states of the supply voltage and the sensing signal; and first and second charge pumps having first and second pumping nodes, said first and second charge pumps each operating complementarily in response to the pumping clock.

36. A semiconductor memory device as claimed in claim 35, wherein said isolation means comprise: a first isolation transistor with a gate connected to the first pumping node and a channel connected between the first pumping node and the voltage pumping node; and a second isolation transistor with a gate connected to the second pumping node and a channel connected between the second pumping node and the voltage pumping node.

37. A semiconductor memory device as claimed in claim 35 or 36, further comprising precharge means for precharging the output of said first and second pumping nodes to a predetermined voltage.

38. A semiconductor memory device as claimed in claim 34, 35, 36 or 37, further comprising means for precharging a voltage at the voltage pumping node to a predetermined voltage.

39. A semiconductor memory device as claimed in any of claims 34 to 38, wherein said active kicker means comprise: a logic combination circuit for receiving signals from the circuitry; a kicking node; a pre-kicker for setting a voltage at the kicking node to a first level when the output of the logic combination circuit is at a first state; a kicking driver converting the voltage at the kicking node from said first level to a second level when the output of the logic combination circuit is at a second state; and a third isolation transistor with a channel connected between the kicking node and the voltage pumping node, said third isolation transistor operating in response to the voltage at the kicking node.

40. A semiconductor memory device as claimed in any of claims 34 to 39, wherein said clamping means comprise a DC current path controllable by the sensing signal, disposed in series between the pumped voltage and the supply voltage.

41. A semiconductor memory device as claimed in any of claims 34 to 39, wherein said clamping means comprise a DC current path disposed in series between the pumped voltage and the supply voltage.

42. A voltage pumping circuit including voltage pumping means for supplying a pumped voltage to electrical circuitry and comprising: first switching means connected between said voltage pumping means and the electrical circuitry, for supplying the pumped voltage to the electrical circuitry in response to the pumped voltage; and second switching means comprising voltage kicking means, connected between input and output terminals of the electrical circuitry, for supplying a kicked voltage output from the voltage kicking means to the electrical circuitry in response to the output of the electrical circuitry.

43. A voltage pumping circuit as claimed in claim 42, wherein said first switching means comprise an insulated gate field effect MOS transistor with a gate connected to the pumped voltage and a channel connected between the pumped voltage and the electrical circuitry.

44. A voltage pumping circuit as claimed in claim 42 or 43, wherein said second switching means comprise an insulated gate field effect MOS transistor with a gate connected to the kicked voltage and a channel connected between the kicked voltage and the pumped voltage.

45. A semiconductor memory device including: a plurality of memory cells; a plurality of word lines coupled to the memory cells; a plurality of bit lines in pairs coupled to the memory cells; a plurality of input/output lines coupled to the bit lines; a plurality of sense amplifiers coupled to the bit line pairs, for amplifying a voltage difference between the bit lines in each pair; a plurality of isolation gates coupled between the bit lines and the input/output lines; and a plurality of word line drivers for selecting the word lines: said semiconductor memory device further comprising: a voltage pumping node coupled to electrical circuitry to which a pumped voltage is provided; a voltage pumping circuit for generating the pumped voltage for a power-up cycle of the semiconductor memory device; isolation means for supplying the pumped voltage to said voltage pumping node in response to the pumped voltage; active kicker means for compensating for a voltage drop of the pumped voltage in response to the signal output from the electrical circuitry; detecting means for feeding-back a sensing signal indicative of variation of the pumped voltage to said voltage pumping means; and clamping means for receiving the sensing signal to clamp the pumped voltage by compensating for a voltage pull-up of the pumped voltage.

46. A semiconductor memory device as claimed in claim 45, wherein said voltage pumping means comprise: an oscillator for generating a pumping clock in response to states of a supply voltage and the sensing signal; and first and second charge pumps having first and second pumping nodes, said first and second charge pumps each operating complementarily in response to the pumping clock.

47. A semiconductor memory device as claimed in claim 46, wherein said isolation means comprise: a first isolation transistor with a gate connected to the first pumping node and a channel connected between the first pumping node and the voltage pumping node; and a second isolation transistor with a gate connected to the second pumping node and a channel connected between the second pumping node and the voltage pumping node.

48. A semiconductor memory device as claimed in claim 46 or 47, further comprising means for precharging a voltage at the first and second pumping nodes to a predetermined voltage.

49. A semiconductor memory device as claimed in claim 45, 46, 47 or 48, further comprising means for precharging a voltage at the voltage pumping node to a predetermined voltage.

50. A semiconductor memory device as claimed in any of claims 45 to 49 wherein said active kicker means comprise: a logic combination circuit for receiving signals from the circuitry; a kicking node; a pre-kicker for setting a voltage at the kicking node to a first level when the output of the logic combination circuit is at a first state; a kicking driver converting the voltage at the kicking node from said first level to a second level when the output of the logic combination circuit is at a second state; and a third isolation transistor with a channel connected between the kicking node and the voltage pumping node, said third isolation transistor operating in response to the voltage at the kicking node.

51. A semiconductor memory device as claimed in any of claims 45 to 50, wherein said clamping means comprise a DC current path controllable by the sensing signal, disposed in series between the pumped voltage and the supply voltage.

52. A semiconductor memory device as claimed in any of claims 45 to 50, wherein said clamping means comprise a DC current path disposed in series between the pumped voltage and the supply voltage.

53. A semiconductor memory device as claimed in any of claims 45 to 50, wherein said clamping means comprise: a first clamping circuit for supplying a first voltage to the voltage pumping node if the supply voltage is identical to the first voltage; and a second clamping circuit for supplying a second voltage higher than the first voltage to the voltage pumping node if the supply voltage is identical to the second voltage.

54. A voltage pumping circuit substantially as hereinbefore described with reference to any of Figures 2 to 8 of the accompanying drawings.

55. A semiconductor memory device provided with a voltage pumping circuit according to any of the preceding claims.