KR940006504B1 - Clamper circuit of semiconductor memory device - Google Patents

Abstract

The excess voltage level of a certain node is clamped by transporting excessive voltage to other node. The clamper circuit includes a switch connected to a first and a second node. When a control signal is a first level, the switch is turned on so that the excessive charge on a first node is transported to a second node, and when a control signal is a second level, the switch is turned off so that the voltage level of a first node is not transported to a second node.

Description

Clamper Circuit of Semiconductor Memory Device

1 is a clamper circuit according to the prior art.

2 is a block diagram of a clamper circuit according to the present invention.

3 is an embodiment of a control signal according to the present invention.

4 is one embodiment of FIG.

5 is a voltage waveform diagram of FIG.

6 is another embodiment of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a clamper circuit for discharging more voltage than necessary to a node to another node.

The semiconductor memory device includes a clamper circuit, for example, in a voltage boostrap circuit, which releases it to another node when a certain voltage is applied to the node. It is a circuit for fixing the voltage level of a node to a predetermined desired voltage level and using the emitted voltage as an operating voltage of a circuit provided in a chip.

In this regard, a clamper circuit shown in the prior art is shown in FIG. In FIG. 1, (A) is a clamper circuit diagram and (B) is a voltage waveform diagram according to (A). In the diagram (A), node a is a node connected to an output terminal of a voltage boosting circuit (Vpp generator) (not shown), and a predetermined boosted voltage is applied, and node b is connected to each circuit in a chip and is required for node a. When the above voltage is applied, the node connects it to each of the above circuits. In the structure of FIG. (A), a transfer transistor M1 having a gate and a drain diode connected to the node a, a channel between the transfer transistor M1 and a node b It consists of a resistor r1 inserted into it. An operation according to the configuration of FIG. 1A will be described with reference to FIG. 2B, which is a voltage waveform diagram. For example, if the voltage across node a is "Va", the voltage across node b is "Vb", and the threshold voltage of the transmission transistor M1 is "Vt", the Va is "Vb +." The transfer transistor M1 is " turned on " when rising above Vt " (which means that more voltage than necessary is charged to the node a). Then, a current path is formed between the a and b nodes so that the excess voltage of the a node is discharged to the b node. This can be easily understood by looking at the voltage waveform of the above (B). Thus, the maximum potential of the node a does not rise above "Vb + Vt". And the role of the resistor (r1) is to suppress the fluctuation of the node b, for example, if the resistance value of the resistor (r1) to a large change in the current over time of the node b, that is, di / dt It is to reduce the voltage fluctuation of the node b.

However, the conventional circuit as shown in FIG. 1A causes the following problems. That is, when the clamper circuit as shown in FIG. 1A is undesired, that is, when it is not desired to operate the clamper circuit to reduce the current consumption, there is no other way to control it. If the voltage level of the node a is to be raised above "Vb + Vt", this cannot be controlled.

It is therefore an object of the present invention to provide a clamper circuit that operates only in a predetermined desired state.

In order to achieve the object of the present invention, the present invention provides a clamper circuit for discharging the voltage charged in the first node to the second node when the voltage charged in the first node reaches a predetermined voltage level. The second node may include a voltage charged to the first node through a switching operation connected between the first node and the second node and a control input of a predetermined control signal in response to an input of the control signal. And a switch configured to transmit a voltage charged to the first node in response to a switching-on operation of the switch corresponding to the first potential and the control signal when the control signal is input to the first potential. When a predetermined voltage level is reached, the second node is discharged to the second node, and the voltage charged to the first node is greater than or equal to the predetermined voltage level in response to a switching-off operation of the switch corresponding to the control signal. It is characterized in that the clamper circuit for performing an operation to block the discharge to the second node even when raised. The control signal may be a circuit provided in a chip, such as using an output signal of a detector of a voltage boosting circuit provided in a chip, or a predetermined detection circuit may be provided between an input terminal and a switch of the clamper circuit. It is a signal that can be easily realized as using an output signal of the detection circuit that outputs a different signal depending on the state of the input terminal.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a clamper circuit according to the present invention. 3 illustrates an example of a method of applying a control signal in the configuration of FIG. 2. 4 illustrates an embodiment of the circuit diagram based on the block diagram of FIG. 2, and FIG. 5 illustrates the voltage waveform. And another embodiment according to the configuration of FIG. 2 is shown in FIG.

2 is a block diagram constructed in accordance with the spirit of the present invention. The block diagram of FIG. 2 is a block diagram configured by briefly implementing the technical idea of the present invention. As can be easily understood in the configuration shown, the core of the present invention is a predetermined input node (i.e., A node) and an output node. (I.e., node B), a clamper circuit having a switch 100 operated by a predetermined control signal. Thus, by supplying or blocking the control signal in a predetermined desired state, it is possible to selectively discharge the voltage applied to the A node to the B node.

An example for generating a control signal for controlling the switch in FIG. 2 is shown in FIG. 3 is a view illustrating a node A and a node B in FIG. 2 as a Vcc node applying a power supply voltage and a Vpp node stepped up than the power supply voltage. It should be noted that the voltage levels across nodes A and B may vary. And a detector for detecting the voltage level of the Vpp node (the detailed circuit is omitted since it is a structure known in the art), and the output signal of the switch of the clamper circuit according to the present invention. Output to the control terminal of. The detector 10 is a circuit for generating a control signal capable of operating the clamper circuit 100 by detecting the high and low Vpp voltage, and it is well known that an inverter chain is provided therein. . In detail with respect to the director 10, the detector 10 inputs and compares a voltage applied to the A node of FIG. 2 and a predetermined reference voltage, respectively, and detects the voltage level applied to the A node. The detection signal is output as a control signal of FIG. 2 in response to the input of the low address strobe signal RAS. Thus, for example, before the low address strobe signal RAS is activated, the operation of detecting the voltage level of the A node is stopped to cause the clamper circuit of FIG. 2 to block the current flow from the unnecessary A node to the B node.

Looking at the detailed circuit of the clamper circuit according to the present invention. FIG. 4 is implemented by applying the block configuration of FIG. 2 according to the present invention to the above-mentioned FIG. 1A which is a conventional circuit. The configuration of Fig. 4 is as follows. That is, the clamper circuit according to the present invention comprises a source node of the A node, the B node, the NMOS transistor MN1 in which the gate and the drain are diode-connected to the A node, and the source terminal of the NMOS transistor MN1. A terminal is connected to PIO transistor MP1 for gate input of a predetermined control signal, and a resistor R1 connected at both ends between a drain terminal of the PIO transistor MP1 and the B node. The structural feature of FIG. 4 is that the switch 100 of FIG. 2 according to the present invention is implemented with an MPMOS transistor as shown. In the above configuration, if the voltage level of the node B is Vs, the switch MP1 according to the present invention is satisfied when the voltage level of the node A satisfies the condition that Vs + Vth (Vth is the threshold voltage of the NMO transistor MN1). If a control signal is applied to the control terminal of < RTI ID = 0.0 >) < / RTI > and " turns on " However, for example, the system (SyStem) operation requires the voltage of node A to be greater than Vs + Vth so that it does not need to discharge the charge, or the voltage of the node A is not large enough to cause a malfunction so that the battery needs to be discharged. If not, the clamper circuit is not operated by controlling the above control signal to turn " off " the switch MP1 according to the present invention, thereby reducing the current consumption.

For example, there may be a case where the voltage level of Vpp is boosted to Vcc + Vt or more and then immediately drops without the operation of the clamper circuit. At this time, the clamper circuit according to the related art causes unnecessary current consumption since the Vpp voltage level is unconditionally operated at the moment when the voltage level of the Vpp is increased above Vcc + Vt, but occurs in the detector 10 in the clamper circuit according to the present invention. Since there is a delay time until the control signal to be input to the PMOS transistor (MP1) of the clamper circuit (this is generated by a delay circuit composed of an inverter chain provided in the detector 10.) When the control signal is inputted to the control terminal of the PMO transistor transistor MP1 which is the switch of the clamper circuit after the delay time, the clamper circuit is not operated because the Vpp voltage level is already below Vcc + Vt. As a result, unnecessary current consumption is not generated. The delay time can be appropriately adjusted by the number of inverters of the delay circuit provided in the detector 10.

And this can be easily understood with reference to FIG. 5, which is a voltage waveform diagram of the FIG. 4 circuit. Referring to FIG. 5, the operation of FIG. 4 will be described in detail as follows. (I) Before section t1 in FIG. 5, the clamping circuit of FIG. In this case, the voltage charged to the A node is not discharged to the B node. At this time, the control signal output from the detector 10 is applied to the "high" level. Then, in response to the "high" input of the control signal, the PIO transistor MP1 of FIG. 4 is "turned off". Thus, the current path between node A and node B is not formed, so node A has a waveform as shown in FIG. (ii) In Fig. 5, between section t1 and t2, the clamper circuit of Fig. 4 clamps the voltage applied to node A to a certain level, and when the voltage applied to node A exceeds the predetermined level, it is transferred to node B. This is the case. The control signal output from the detector 10 of FIG. 3 is popular as " low. &Quot; Then, in response to the "low" input of the control signal, PIO transistor MP1 in FIG. 4 is "turned on". Thus, a current path is formed between node A and node B, and as shown in the configuration of FIG. 4, node A is clamped with a voltage of (V _B + V _T ) or less (where V _B is node _B ). And V _T is the threshold voltage of the NMOS transistor MN1). Thus, node A has a waveform as shown in FIG. 5. (iii) After the section t2 in FIG. In this case, the clamper circuit according to the present invention has the same operation condition as the above-described t1 section, and node A has a waveform as shown in FIG.

According to the same method as in the case of (i), (ii) and (iii), the voltage level of the node A can be adjusted in correspondence with the input level of the control signal. Therefore, the clamper circuit according to the present invention can suppress unnecessary current flow by supplying a control signal only during a desired operation to suppress current consumption of the clamper circuit. In addition, in the related art, whether the driving of the clamper circuit is determined only according to the voltage level of the A node, but the clamper circuit according to the present invention as shown in FIG. 4 is determined according to the voltage level of the A node in response to the control signal. This has the advantage that it is easy to adjust the voltage level of the falling node A.

6 is another embodiment according to the block configuration of FIG. 2 according to the present invention. In FIG. 6, the A node is configured to vary the voltage level by combining the clamper circuit according to the prior art and the clamper circuit according to the present invention. In Fig. 6, the symbol is the same as the circuit of Fig. 4 because the functions are the same, and the same symbol is used. The circuit of FIG. 6 has two clamper circuits between the A and B nodes. That is, the clamper circuit-1 has the same configuration as that of the FIG. 4 circuit, and the clamper circuit-2 has two NMO transistors (MN2) (MN3) and a resistor (R2) whose gates are diode-connected and serially connected to each other. ) Are configured in series with each other between the A and B nodes.

Referring to the operation of the clamper circuit of Figure 6 by the above configuration is as follows. The threshold voltages of the above-mentioned EnMOS transistors MN1, MN2, and MN3 are referred to as V _th1 , V _th2 , and V _th3 , respectively. At this time, the magnitude of each threshold voltage is configured as V _th1 <V _th2 + V _th3 . The clamper circuit-1 operates like the above-mentioned FIG. 4 circuit. When the voltage level of the node C reaches V _B + V _th 2, the clamper circuit-2 “turns on” the second ENMO transistor MN2, and when the voltage level of the node A reaches V _B + V _{th 2} + V _{th 3} or more. The third ENMO transistor MN3 is " turned on " so that a current path is generated from the A node to the B node to discharge the charge. So the sixth degree circuit, the voltage level of the node A is more than _{V B + V th2 V B +} V th2 + V th3 until it is below the predetermined desired by using a control signal from the clamper circuit -1 Each time the clamper circuit-1 is operated to adjust the voltage level of the node A. When the voltage level of the node A rises above V _B + V _th2 + V _th3 , at that moment, the clamper circuit-2 The second and third NMO transistors MN2 and MN3 are " turned on " to discharge the charge to the B node. Therefore, in the case of the circuit of FIG. 6, the voltage level at which the node A can rise is limited to V _B + V _th2 + V _th3 at maximum, and in any case of V _B + V _th1 or more, In response to the application, the voltage emission level of the A node can be adjusted.

The circuits of Figs. 4 and 6 according to the present invention are the best embodiment realized in consideration of the control signals in Fig. 2 and Fig. 3 according to the fact of the present invention. It should be noted that, within the technical scope, the configuration may vary, for example, a switch implemented with a PIO transistor can be implemented with another element.

As described above, the clamper circuit according to the present invention can operate only in a predetermined desired state, thereby suppressing current consumption and providing a more reliable clamper circuit. In addition, the clamper circuit according to the present invention has the advantage of limiting the rising level of the voltage applied to the input node to a specific voltage level and adjusting the voltage release level of the input node.

Claims (6)

A clamper circuit for emitting a charge assist voltage to a first node when a voltage charged to a first node reaches a predetermined voltage level, between the first node and the second node. And a switch connected to the control node by inputting a predetermined control signal to transmit a voltage charged to the first node to the second node through a switching operation in response to the input of the control signal. When inputted to the potential, in response to the switching-on operation of the switch corresponding to the control signal of the first potential, the voltage charged by the first node to the second node when the predetermined voltage level is reached. And the control signal is charged to the first node in response to a switching-off operation of the switch corresponding to the control signal of the second potential when the control signal is input at a second potential that is complementary to the first potential. Voltage Clamper circuit of FIG characterized by carrying out the operation to block the release to the second node to rise above the predetermined voltage level group. The method of claim 1, wherein the control signal inputs and compares a voltage applied to the first node and a predetermined reference voltage, respectively, to detect a voltage level applied to the first node and converts the detected signal into a low address strobe signal. And a detector output as a control signal in response to an input. A semiconductor memory device having a first node into which a voltage stepped up to an operating power supply voltage of a chip is introduced and a second node into which the operating power supply voltage is introduced, wherein the semiconductor memory device is formed between the first node and the second node. A switch connected to a first path to control-input a predetermined control signal to transmit a voltage charged to the first node to the second node through a switching operation in response to the input of the control signal; A first clamper circuit including at least a first NMOS transistor having a channel formed between the first node and diode-connected with a gate and a drain, and a first formed between the first node and the second node. A channel between the channel and the drain of the second MOS transistor, wherein the channel is connected on the second path and the gate and the diode are diode-connected, and between the drain and the first node of the second MOS transistor. And a second clamper circuit including at least a third NMOS transistor having a gate and a drain diode-connected thereto, wherein the voltage charged to the first node is higher than the operating power supply voltage, but through the second path. When the first voltage level that is below the level to be emitted is reached, the voltage charged to the first node is greater than the operating power supply voltage in response to the switching-on operation of the switch corresponding to the first control signal. When the first voltage level is reached, the first node discharges to the second node through the first clamper circuit, and when the voltage charged by the first node is the first voltage level, the first potential and complementary levels are increased. In response to the switch-off operation of the switch corresponding to the control signal of the second potential to prevent the voltage charged to the first node from being discharged to the second node, the first furnace The voltage charged to the first node is discharged through the second clamper circuit when the voltage charged to the second node reaches a second voltage level which is higher than the level to be emitted through the second path. Memory device. 4. The semiconductor memory device according to claim 3, wherein the switch is formed of a PMOS transistor which has a channel formed between the second node and the first NMOS transistor and gates the control signal. 5. The method of claim 4, wherein the control signal inputs and compares the voltage applied to the first node with a predetermined reference voltage, respectively, to detect the voltage level applied to the first node and converts the detected signal into a low address strobe signal. And a detector for outputting the control signal in response to an input. 4. The method of claim 3, wherein the first clamper circuit further comprises a first resistor connected between the switch and the second node, wherein the second clamper circuit is formed of the second enMOS transistor and the second node. And a second resistor connected between the semiconductor memory device.